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qualcommax: 6.6: make patches apply 

Drop backported patches already included in 6.6 and refresh the rest to
apply.

Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko 2024-03-22 11:08:54 +01:00
parent e8e7b3c106
commit d9386dc8e9
88 changed files with 106 additions and 6889 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
target/linux/qualcommax/patches-6.6/0001-v6.2-arm64-dts-qcom-ipq8074-add-A53-PLL-node.patch
View File

@ -1,32 +0,0 @@
From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:28 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
Add the required node for A53 PLL which will be used to provide the CPU
clock via APCS for APSS scaling.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -677,6 +677,14 @@
#mbox-cells = <1>;
};
+ a53pll: clock@b116000 {
+ compatible = "qcom,ipq8074-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;

134
target/linux/qualcommax/patches-6.6/0002-v6.2-thermal-drivers-tsens-Add-support-for-combined-inter.patch
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@ -1,134 +0,0 @@
From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:42 +0200
Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
signaling both up/low and critical trips.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 1 +
drivers/thermal/qcom/tsens-v0_1.c | 1 +
drivers/thermal/qcom/tsens-v1.c | 1 +
drivers/thermal/qcom/tsens-v2.c | 1 +
drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
drivers/thermal/qcom/tsens.h | 2 ++
6 files changed, 38 insertions(+), 6 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
static struct tsens_features tsens_8960_feat = {
.ver_major = VER_0,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 0,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
static struct tsens_features tsens_v0_1_feat = {
.ver_major = VER_0_1,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
static struct tsens_features tsens_v1_feat = {
.ver_major = VER_1_X,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -31,6 +31,7 @@
static struct tsens_features tsens_v2_feat = {
.ver_major = VER_2_X,
.crit_int = 1,
+ .combo_int = 0,
.adc = 0,
.srot_split = 1,
.max_sensors = 16,
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -532,6 +532,27 @@ static irqreturn_t tsens_irq_thread(int
return IRQ_HANDLED;
}
+/**
+ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
+ * @irq: irq number
+ * @data: tsens controller private data
+ *
+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
+ * critical handler first and then the up/low one.
+ *
+ * Return: IRQ_HANDLED
+ */
+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
+{
+ irqreturn_t ret;
+
+ ret = tsens_critical_irq_thread(irq, data);
+ if (ret != IRQ_HANDLED)
+ return ret;
+
+ return tsens_irq_thread(irq, data);
+}
+
static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
{
struct tsens_sensor *s = tz->devdata;
@@ -1074,13 +1095,18 @@ static int tsens_register(struct tsens_p
tsens_mC_to_hw(priv->sensor, 0));
}
- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
- if (ret < 0)
- return ret;
+ if (priv->feat->combo_int) {
+ ret = tsens_register_irq(priv, "combined",
+ tsens_combined_irq_thread);
+ } else {
+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
+ if (ret < 0)
+ return ret;
- if (priv->feat->crit_int)
- ret = tsens_register_irq(priv, "critical",
- tsens_critical_irq_thread);
+ if (priv->feat->crit_int)
+ ret = tsens_register_irq(priv, "critical",
+ tsens_critical_irq_thread);
+ }
return ret;
}
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -493,6 +493,7 @@ enum regfield_ids {
* struct tsens_features - Features supported by the IP
* @ver_major: Major number of IP version
* @crit_int: does the IP support critical interrupts?
+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
* @adc: do the sensors only output adc code (instead of temperature)?
* @srot_split: does the IP neatly splits the register space into SROT and TM,
* with SROT only being available to secure boot firmware?
@@ -502,6 +503,7 @@ enum regfield_ids {
struct tsens_features {
unsigned int ver_major;
unsigned int crit_int:1;
+ unsigned int combo_int:1;
unsigned int adc:1;
unsigned int srot_split:1;
unsigned int has_watchdog:1;

101
target/linux/qualcommax/patches-6.6/0003-v6.2-thermal-drivers-tsens-Allow-configuring-min-and-max-.patch
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@ -1,101 +0,0 @@
From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:43 +0200
Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
IPQ8074 and IPQ6018 dont support negative trip temperatures and support
up to 204 degrees C as the max trip temperature.
So, instead of always setting the -40 as min and 120 degrees C as max
allow it to be configured as part of the features.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 2 ++
drivers/thermal/qcom/tsens-v0_1.c | 2 ++
drivers/thermal/qcom/tsens-v1.c | 2 ++
drivers/thermal/qcom/tsens-v2.c | 2 ++
drivers/thermal/qcom/tsens.c | 4 ++--
drivers/thermal/qcom/tsens.h | 4 ++++
6 files changed, 14 insertions(+), 2 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
.adc = 1,
.srot_split = 0,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
struct tsens_plat_data data_8960 = {
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
.adc = 0,
.srot_split = 1,
.max_sensors = 16,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -573,8 +573,8 @@ static int tsens_set_trips(struct therma
dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
hw_id, __func__, low, high);
- cl_high = clamp_val(high, -40000, 120000);
- cl_low = clamp_val(low, -40000, 120000);
+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
high_val = tsens_mC_to_hw(s, cl_high);
low_val = tsens_mC_to_hw(s, cl_low);
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -499,6 +499,8 @@ enum regfield_ids {
* with SROT only being available to secure boot firmware?
* @has_watchdog: does this IP support watchdog functionality?
* @max_sensors: maximum sensors supported by this version of the IP
+ * @trip_min_temp: minimum trip temperature supported by this version of the IP
+ * @trip_max_temp: maximum trip temperature supported by this version of the IP
*/
struct tsens_features {
unsigned int ver_major;
@@ -508,6 +510,8 @@ struct tsens_features {
unsigned int srot_split:1;
unsigned int has_watchdog:1;
unsigned int max_sensors;
+ int trip_min_temp;
+ int trip_max_temp;
};
/**

74
target/linux/qualcommax/patches-6.6/0004-v6.2-thermal-drivers-tsens-Add-IPQ8074-support.patch
View File

@ -1,74 +0,0 @@
From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:44 +0200
Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
it only has one IRQ, that is used for up/low as well as critical.
It also does not support negative trip temperatures.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
drivers/thermal/qcom/tsens.c | 3 +++
drivers/thermal/qcom/tsens.h | 2 +-
3 files changed, 21 insertions(+), 1 deletion(-)
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
.trip_max_temp = 120000,
};
+static struct tsens_features ipq8074_feat = {
+ .ver_major = VER_2_X,
+ .crit_int = 1,
+ .combo_int = 1,
+ .adc = 0,
+ .srot_split = 1,
+ .max_sensors = 16,
+ .trip_min_temp = 0,
+ .trip_max_temp = 204000,
+};
+
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
/* ----- SROT ------ */
/* VERSION */
@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
.fields = tsens_v2_regfields,
};
+struct tsens_plat_data data_ipq8074 = {
+ .ops = &ops_generic_v2,
+ .feat = &ipq8074_feat,
+ .fields = tsens_v2_regfields,
+};
+
/* Kept around for backward compatibility with old msm8996.dtsi */
struct tsens_plat_data data_8996 = {
.num_sensors = 13,
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -981,6 +981,9 @@ static const struct of_device_id tsens_t
.compatible = "qcom,ipq8064-tsens",
.data = &data_8960,
}, {
+ .compatible = "qcom,ipq8074-tsens",
+ .data = &data_ipq8074,
+ }, {
.compatible = "qcom,mdm9607-tsens",
.data = &data_9607,
}, {
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -597,6 +597,6 @@ extern struct tsens_plat_data data_8916,
extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
/* TSENS v2 targets */
-extern struct tsens_plat_data data_8996, data_tsens_v2;
+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
#endif /* __QCOM_TSENS_H__ */

130
target/linux/qualcommax/patches-6.6/0005-v6.2-arm64-dts-qcom-ipq8074-add-thermal-nodes.patch
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@ -1,130 +0,0 @@
From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:45 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
IPQ8074 has a tsens v2.3.0 peripheral which monitors
temperatures around the various subsystems on the
die.
So lets add the tsens and thermal zone nodes, passive
CPU cooling will come in later patches after CPU frequency
scaling is supported.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -276,6 +276,16 @@
status = "disabled";
};
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq8074-tsens";
+ reg = <0x4a9000 0x1000>, /* TM */
+ <0x4a8000 0x1000>; /* SROT */
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ #qcom,sensors = <16>;
+ #thermal-sensor-cells = <1>;
+ };
+
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
@@ -876,4 +886,90 @@
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+
+ thermal-zones {
+ nss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 4>;
+ };
+
+ nss0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 5>;
+ };
+
+ nss1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 6>;
+ };
+
+ wcss-phya0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 7>;
+ };
+
+ wcss-phya1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 8>;
+ };
+
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 9>;
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 10>;
+ };
+
+ cpu2_thermal: cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 11>;
+ };
+
+ cpu3_thermal: cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 12>;
+ };
+
+ cluster_thermal: cluster-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 13>;
+ };
+
+ wcss-phyb0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 14>;
+ };
+
+ wcss-phyb1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 15>;
+ };
+ };
};

29
target/linux/qualcommax/patches-6.6/0006-v6.2-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch
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@ -1,29 +0,0 @@
From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:08:49 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
APCS now has support for providing the APSS clocks as the child device
for IPQ8074.
So, add the A53 PLL and XO clocks in order to use APCS as the CPU
clocksource for APSS scaling.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -682,6 +682,8 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
reg = <0x0b111000 0x1000>;
+ clocks = <&a53pll>, <&xo>;
+ clock-names = "pll", "xo";
#clock-cells = <1>;
#mbox-cells = <1>;

3601
target/linux/qualcommax/patches-6.6/0007-v6.2-clk-qcom-ipq8074-convert-to-parent-data.patch
View File

File diff suppressed because it is too large Load Diff

28
target/linux/qualcommax/patches-6.6/0008-v6.2-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch
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@ -1,28 +0,0 @@
From 8857b0ab6a562c473c5bded0efda9390b82a84d4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 27 Sep 2022 22:12:17 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: fix NAND node name
Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
Fix it to match nand-controller.yaml requirements.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927201218.1264506-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -348,7 +348,7 @@
status = "disabled";
};
- qpic_nand: nand@79b0000 {
+ qpic_nand: nand-controller@79b0000 {
compatible = "qcom,ipq6018-nand";
reg = <0x0 0x079b0000 0x0 0x10000>;
#address-cells = <1>;

39
target/linux/qualcommax/patches-6.6/0009-v6.2-dt-bindings-clock-qcom-ipq8074-add-missing-networkin.patch
View File

@ -1,39 +0,0 @@
From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 14:29:00 +0100
Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
resets
Add bindings for the missing networking resets found in IPQ8074 GCC.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -367,6 +367,20 @@
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
+#define GCC_PPE_FULL_RESET 132
+#define GCC_UNIPHY0_SOFT_RESET 133
+#define GCC_UNIPHY0_XPCS_RESET 134
+#define GCC_UNIPHY1_SOFT_RESET 135
+#define GCC_UNIPHY1_XPCS_RESET 136
+#define GCC_UNIPHY2_SOFT_RESET 137
+#define GCC_UNIPHY2_XPCS_RESET 138
+#define GCC_EDMA_HW_RESET 139
+#define GCC_NSSPORT1_RESET 140
+#define GCC_NSSPORT2_RESET 141
+#define GCC_NSSPORT3_RESET 142
+#define GCC_NSSPORT4_RESET 143
+#define GCC_NSSPORT5_RESET 144
+#define GCC_NSSPORT6_RESET 145
#define USB0_GDSC 0
#define USB1_GDSC 1

41
target/linux/qualcommax/patches-6.6/0010-v6.2-clk-qcom-ipq8074-add-missing-networking-resets.patch
View File

@ -1,41 +0,0 @@
From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 14:29:01 +0100
Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
Downstream QCA 5.4 kernel defines networking resets which are not present
in the mainline kernel but are required for the networking drivers.
So, port the downstream resets and avoid using magic values for mask,
construct mask for resets which require multiple bits to be set/cleared.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4665,6 +4665,20 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
+ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
+ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
};
static struct gdsc *gcc_ipq8074_gdscs[] = {

152
target/linux/qualcommax/patches-6.6/0011-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch
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@ -1,152 +0,0 @@
From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 16 Nov 2022 22:46:55 +0100
Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
It appears that having only .name populated in parent_data for clocks
which are only globally searchable currently will not work as the clk core
won't copy that name if there is no .fw_name present as well.
So, populate .fw_name for all parent clocks in parent_data.
Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
1 file changed, 26 insertions(+), 26 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -674,7 +674,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
- { .name = "pcie20_phy0_pipe_clk" },
+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -727,7 +727,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
- { .name = "pcie20_phy1_pipe_clk" },
+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -1131,7 +1131,7 @@ static const struct freq_tbl ftbl_nss_no
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "bias_pll_nss_noc_clk" },
+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
@@ -1356,7 +1356,7 @@ static const struct freq_tbl ftbl_nss_pp
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
@@ -1407,10 +1407,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -1459,10 +1459,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1690,12 +1690,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy1_gcc_rx_clk" },
- { .name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1752,12 +1752,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy1_gcc_tx_clk" },
- { .name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1814,10 +1814,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy2_gcc_rx_clk" },
- { .name = "uniphy2_gcc_tx_clk" },
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
@@ -1871,10 +1871,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy2_gcc_tx_clk" },
- { .name = "uniphy2_gcc_rx_clk" },
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {

36
target/linux/qualcommax/patches-6.6/0012-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch
View File

@ -1,36 +0,0 @@
From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 30 Oct 2022 18:57:03 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
Pass XO and sleep clocks to the GCC controller so it does not have to
find them by matching globaly by name.
If not passed directly, driver maintains backwards compatibility by then
falling back to global lookup.
Since we are here, set cell numbers in decimal instead of hex.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -363,9 +363,11 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- #clock-cells = <0x1>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
+ #clock-cells = <1>;
#power-domain-cells = <1>;
- #reset-cells = <0x1>;
+ #reset-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {

149
target/linux/qualcommax/patches-6.6/0013-v6.2-arm64-dts-qcom-add-PMP8074-DTSI.patch
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@ -1,149 +0,0 @@
From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:14 +0200
Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
controlled via SPMI.
Add DTSI for it providing GPIO, regulator, RTC and VADC support.
RTC is disabled by default as there is no built-in battery so it will
loose time unless board vendor added a battery, so make it optional.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmp8074_adc: adc@3100 {
+ compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-vadc@2 {
+ reg = <ADC5_VREF_VADC>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmic_die: die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm: xo-temp@76 {
+ reg = <ADC5_XO_THERM_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1: thermistor1@77 {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2: thermistor2@78 {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm3: thermistor3@79 {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph-pwr@131 {
+ reg = <ADC5_VPH_PWR>;
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
+ pmp8074_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ allow-set-time;
+ status = "disabled";
+ };
+
+ pmp8074_gpios: gpio@c000 {
+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+
+ regulators {
+ compatible = "qcom,pmp8074-regulators";
+
+ s3: s3 {
+ regulator-name = "vdd_s3";
+ regulator-min-microvolt = <592000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ s4: s4 {
+ regulator-name = "vdd_s4";
+ regulator-min-microvolt = <712000>;
+ regulator-max-microvolt = <992000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ l11: l11 {
+ regulator-name = "l11";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};

37
target/linux/qualcommax/patches-6.6/0014-v6.2-arm64-dts-qcom-ipq8074-hk01-add-VQMMC-supply.patch
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@ -1,37 +0,0 @@
From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:15 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
Since now we have control over the PMP8074 PMIC providing various system
voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
the SDHCI VQMMC supply.
This allows SDHCI controller to switch to 1.8V I/O mode and support high
speed modes like HS200 and HS400.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -3,6 +3,7 @@
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
+#include "pmp8074.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
@@ -84,6 +85,7 @@
&sdhc_1 {
status = "okay";
+ vqmmc-supply = <&l11>;
};
&qusb_phy_0 {

42
target/linux/qualcommax/patches-6.6/0015-v6.2-arm64-dts-qcom-hk01-use-GPIO-flags-for-tlmm.patch
View File

@ -1,42 +0,0 @@
From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 10:29:30 +0100
Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
harcoding the cell value.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -4,6 +4,7 @@
*/
#include "ipq8074.dtsi"
#include "pmp8074.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
@@ -52,12 +53,12 @@
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_qmp0 {

82
target/linux/qualcommax/patches-6.6/0016-v6.2-arm64-dts-qcom-ipq8074-Fix-up-comments.patch
View File

@ -1,82 +0,0 @@
From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 7 Nov 2022 15:55:17 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
Make sure all multiline C-style commends begin with just '/*' with
the comment text starting on a new line.
Also, fix up some whitespace within comments.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
4 files changed, 12 insertions(+), 9 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
#include "pmp8074.dtsi"
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#include "ipq8074-hk10.dtsi"
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -129,10 +129,10 @@
status = "disabled";
usb1_ssphy: phy@58200 {
- reg = <0x00058200 0x130>, /* Tx */
+ reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc*/
+ <0x00058800 0x1f8>, /* PCS */
+ <0x00058600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
@@ -172,10 +172,10 @@
status = "disabled";
usb0_ssphy: phy@78200 {
- reg = <0x00078200 0x130>, /* Tx */
+ reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc*/
+ <0x00078800 0x1f8>, /* PCS */
+ <0x00078600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;

60
target/linux/qualcommax/patches-6.6/0017-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch
View File

@ -1,60 +0,0 @@
From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 8 Nov 2022 15:23:57 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -320,35 +320,35 @@
interrupt-controller;
#interrupt-cells = <0x2>;
- serial_4_pins: serial4-pinmux {
+ serial_4_pins: serial4-state {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
drive-strength = <8>;
bias-disable;
};
- i2c_0_pins: i2c-0-pinmux {
+ i2c_0_pins: i2c-0-state {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
- hsuart_pins: hsuart-pins {
+ hsuart_pins: hsuart-state {
pins = "gpio46", "gpio47", "gpio48", "gpio49";
function = "blsp2_uart";
drive-strength = <8>;
bias-disable;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",

56
target/linux/qualcommax/patches-6.6/0018-v6.2-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-.patch
View File

@ -1,56 +0,0 @@
From 20afb6751739264ea41993877de93923911dfdc3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 6 Oct 2022 14:46:27 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: align TLMM pin configuration with
DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221006124659.217540-3-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++--
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -51,13 +51,13 @@
};
&tlmm {
- i2c_1_pins: i2c-1-pins {
+ i2c_1_pins: i2c-1-state {
pins = "gpio42", "gpio43";
function = "blsp2_i2c";
drive-strength = <8>;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -218,14 +218,14 @@
interrupt-controller;
#interrupt-cells = <2>;
- serial_3_pins: serial3-pinmux {
+ serial_3_pins: serial3-state {
pins = "gpio44", "gpio45";
function = "blsp2_uart";
drive-strength = <8>;
bias-pull-down;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",

24
target/linux/qualcommax/patches-6.6/0019-v6.3-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch
View File

@ -1,24 +0,0 @@
From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 16 Nov 2022 22:48:36 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
generation limit.
This allows the generic DWC code to configure the link speed correctly.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -768,6 +768,7 @@
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
+ max-link-speed = <2>;
#address-cells = <3>;
#size-cells = <2>;

26
target/linux/qualcommax/patches-6.6/0020-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch
View File

@ -1,26 +0,0 @@
From f356132229b18ceef5d5ef9103bbaa9bdeb84c8d Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 13 Jan 2023 17:44:47 +0100
Subject: [PATCH] PCI: qcom: Add IPQ8074 Gen3 port support
IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
Add compatible for Gen3 port which uses the same controller as IPQ6018.
Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1762,6 +1762,7 @@ static const struct of_device_id qcom_pc
{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },

38
target/linux/qualcommax/patches-6.6/0021-v6.3-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch
View File

@ -1,38 +0,0 @@
From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 8 Jan 2023 13:36:28 +0100
Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
Having only .name populated in parent_data for clocks which are only
globally searchable currently will not work as the clk core won't copy
that name if there is no .fw_name present as well.
So, populate .fw_name for usb3phy clocks in parent_data as they were
missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -928,7 +928,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
};
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
- { .name = "usb3phy_0_cc_pipe_clk" },
+ { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -996,7 +996,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
};
static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
- { .name = "usb3phy_1_cc_pipe_clk" },
+ { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};

26
target/linux/qualcommax/patches-6.6/0022-v6.4-arm64-dts-qcom-ipq8074-add-compatible-fallback-to.patch
View File

@ -1,26 +0,0 @@
From d93bd4630ce163f3761aedc0b342b072bee6db6b Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 22 Mar 2023 18:41:40 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: add compatible fallback to mailbox
IPQ8074 mailbox is compatible with IPQ6018.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-4-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -682,7 +682,8 @@
};
apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
+ compatible = "qcom,ipq8074-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
clocks = <&a53pll>, <&xo>;
clock-names = "pll", "xo";

199
target/linux/qualcommax/patches-6.6/0023-v6.5-arm64-dts-qcom-ipq8074-add-critical-thermal-trips.patch
View File

@ -1,199 +0,0 @@
From 56d3067cb694ba60d654e7f5ef231b6fabc4697f Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 7 Jun 2023 20:44:48 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add critical thermal trips
According to bindings, thermal zones must have associated trips as well.
Since we currently dont have CPUFreq support and thus no passive cooling
lets start by defining critical trips to protect the devices against
severe overheating.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -899,6 +899,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
+
+ trips {
+ nss-top-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
nss0-thermal {
@@ -906,6 +914,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
+
+ trips {
+ nss-0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
nss1-thermal {
@@ -913,6 +929,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
+
+ trips {
+ nss-1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phya0-thermal {
@@ -920,6 +944,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
+
+ trips {
+ wcss-phya0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phya1-thermal {
@@ -927,6 +959,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
+
+ trips {
+ wcss-phya1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu0_thermal: cpu0-thermal {
@@ -934,6 +974,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu1_thermal: cpu1-thermal {
@@ -941,6 +989,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 10>;
+
+ trips {
+ cpu1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu2_thermal: cpu2-thermal {
@@ -948,6 +1004,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 11>;
+
+ trips {
+ cpu2-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu3_thermal: cpu3-thermal {
@@ -955,6 +1019,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 12>;
+
+ trips {
+ cpu3-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cluster_thermal: cluster-thermal {
@@ -962,6 +1034,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 13>;
+
+ trips {
+ cluster-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phyb0-thermal {
@@ -969,6 +1049,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 14>;
+
+ trips {
+ wcss-phyb0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phyb1-thermal {
@@ -976,6 +1064,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 15>;
+
+ trips {
+ wcss-phyb1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
};
};

4
target/linux/qualcommax/patches-6.6/0024-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -121,6 +121,9 @@
@@ -203,6 +203,9 @@
#define QCOM_ID_SM6125 394
#define QCOM_ID_IPQ8070A 395
#define QCOM_ID_IPQ8071A 396
@ -26,4 +26,4 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+#define QCOM_ID_IPQ8174 399
#define QCOM_ID_IPQ6018 402
#define QCOM_ID_IPQ6028 403
#define QCOM_ID_IPQ6000 421
#define QCOM_ID_SDM429W 416

14
target/linux/qualcommax/patches-6.6/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch
View File

@ -25,9 +25,9 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -163,6 +163,7 @@ static const struct of_device_id blockli
{ .compatible = "ti,dra7", },
{ .compatible = "ti,omap3", },
@@ -177,6 +177,7 @@ static const struct of_device_id blockli
{ .compatible = "ti,am625", },
{ .compatible = "ti,am62a7", },
+ { .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
@ -35,7 +35,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
{ .compatible = "qcom,msm8974", },
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -31,6 +31,8 @@
@@ -30,6 +30,8 @@
#include <dt-bindings/arm/qcom,ids.h>
@ -44,7 +44,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -204,6 +206,57 @@ len_error:
@@ -203,6 +205,57 @@ len_error:
return ret;
}
@ -102,7 +102,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -218,6 +271,10 @@ static const struct qcom_cpufreq_match_d
@@ -217,6 +270,10 @@ static const struct qcom_cpufreq_match_d
.genpd_names = qcs404_genpd_names,
};
@ -113,7 +113,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -362,6 +419,7 @@ static const struct of_device_id qcom_cp
@@ -359,6 +416,7 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },

10
target/linux/qualcommax/patches-6.6/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
View File

@ -25,7 +25,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -165,6 +165,7 @@ static const struct of_device_id blockli
@@ -179,6 +179,7 @@ static const struct of_device_id blockli
{ .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
@ -35,7 +35,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
{ .compatible = "qcom,msm8960", },
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -33,6 +33,11 @@
@@ -32,6 +32,11 @@
#define IPQ6000_VERSION BIT(2)
@ -47,7 +47,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -257,6 +262,44 @@ static int qcom_cpufreq_ipq6018_name_ver
@@ -256,6 +261,44 @@ static int qcom_cpufreq_ipq6018_name_ver
return 0;
}
@ -92,7 +92,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -275,6 +318,10 @@ static const struct qcom_cpufreq_match_d
@@ -274,6 +317,10 @@ static const struct qcom_cpufreq_match_d
.get_version = qcom_cpufreq_ipq6018_name_version,
};
@ -103,7 +103,7 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -421,6 +468,7 @@ static const struct of_device_id qcom_cp
@@ -418,6 +465,7 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },

2
target/linux/qualcommax/patches-6.6/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch
View File

@ -19,7 +19,7 @@ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -685,8 +685,8 @@
@@ -721,8 +721,8 @@
compatible = "qcom,ipq8074-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;

27
target/linux/qualcommax/patches-6.6/0029-v6.3-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ5332-and-its.patch
View File

@ -1,27 +0,0 @@
From c0877a26b7ee54ef30d16ffdcdd37f2bcffe518e Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Wed, 8 Feb 2023 11:27:08 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its
variant
Add SOC ID for Qualcomm IPQ5332 and IPQ5322 variants.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208055709.13162-2-quic_kathirav@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 2 ++
1 file changed, 2 insertions(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -143,6 +143,8 @@
#define QCOM_ID_SC7280 487
#define QCOM_ID_SC7180P 495
#define QCOM_ID_SM6375 507
+#define QCOM_ID_IPQ5332 592
+#define QCOM_ID_IPQ5322 593
/*
* The board type and revision information, used by Qualcomm bootloaders and

33
target/linux/qualcommax/patches-6.6/0030-v6.4-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ9574-and-its.patch
View File

@ -1,33 +0,0 @@
From 725352e15e1d030885611a546eb1f2884851a407 Mon Sep 17 00:00:00 2001
From: Varadarajan Narayanan <quic_varada@quicinc.com>
Date: Tue, 14 Mar 2023 11:43:33 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ9574 and its
variants
Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550,
IPQ9514 and IPQ9510
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1678774414-14414-2-git-send-email-quic_varada@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 6 ++++++
1 file changed, 6 insertions(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -143,6 +143,12 @@
#define QCOM_ID_SC7280 487
#define QCOM_ID_SC7180P 495
#define QCOM_ID_SM6375 507
+#define QCOM_ID_IPQ9514 510
+#define QCOM_ID_IPQ9550 511
+#define QCOM_ID_IPQ9554 512
+#define QCOM_ID_IPQ9570 513
+#define QCOM_ID_IPQ9574 514
+#define QCOM_ID_IPQ9510 521
#define QCOM_ID_IPQ5332 592
#define QCOM_ID_IPQ5322 593

28
target/linux/qualcommax/patches-6.6/0031-v6.5-dt-bindings-arm-qcom-ids-add-SoC-ID-for-IPQ5312-and-.patch
View File

@ -1,28 +0,0 @@
From 614c778cf0d570642c50715adfa0b70930d8cf29 Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Tue, 9 May 2023 09:05:30 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: add SoC ID for IPQ5312 and
IPQ5302
Add the SoC ID for IPQ5312 and IPQ5302, which belong to the family of
IPQ5332 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230509033531.21468-2-quic_kathirav@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 2 ++
1 file changed, 2 insertions(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -151,6 +151,8 @@
#define QCOM_ID_IPQ9510 521
#define QCOM_ID_IPQ5332 592
#define QCOM_ID_IPQ5322 593
+#define QCOM_ID_IPQ5312 594
+#define QCOM_ID_IPQ5302 595
/*
* The board type and revision information, used by Qualcomm bootloaders and

25
target/linux/qualcommax/patches-6.6/0032-v6.5-dt-bindings-arm-qcom-ids-add-SoC-ID-for-IPQ5300.patch
View File

@ -1,25 +0,0 @@
From b3c72f2795467e3d43ee429b0ebd5f523ec08f60 Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Mon, 5 Jun 2023 13:35:28 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300
Add the SoC ID for IPQ5300, which belong to the family of IPQ5332 SoC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230605080531.3879-2-quic_kathirav@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -153,6 +153,7 @@
#define QCOM_ID_IPQ5322 593
#define QCOM_ID_IPQ5312 594
#define QCOM_ID_IPQ5302 595
+#define QCOM_ID_IPQ5300 624
/*
* The board type and revision information, used by Qualcomm bootloaders and

52
target/linux/qualcommax/patches-6.6/0033-v6.2-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC.patch
View File

@ -1,52 +0,0 @@
From feeef118fda562cf9081edef8ad464d89db070f4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 27 Sep 2022 22:12:18 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
The ARM timer is usually considered not part of SoC node, just like
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -510,14 +510,6 @@
clock-names = "xo";
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -769,6 +761,14 @@
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;

605
target/linux/qualcommax/patches-6.6/0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch
View File

@ -1,605 +0,0 @@
From 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:28 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Sort nodes properly
Order nodes by unit address if one exists and alphabetically otherwise.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++-------------
1 file changed, 281 insertions(+), 281 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -87,6 +87,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq6018", "qcom,scm";
+ };
+ };
+
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -123,12 +129,6 @@
};
};
- firmware {
- scm {
- compatible = "qcom,scm-ipq6018", "qcom,scm";
- };
- };
-
pmuv8: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
@@ -166,6 +166,28 @@
};
};
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: glink-channel {
+ compatible = "qcom,rpm-ipq6018";
+ qcom,glink-channels = "rpm_requests";
+
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
@@ -179,6 +201,102 @@
dma-ranges;
compatible = "simple-bus";
+ qusb_phy_1: qusb@59000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x00059000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: ssphy@78000 {
+ compatible = "qcom,ipq6018-qmp-usb3-phy";
+ reg = <0x0 0x00078000 0x0 0x1c4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: phy@78200 {
+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
+ <0x0 0x00078400 0x0 0x200>, /* Rx */
+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */
+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: qusb@79000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x00079000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ pcie_phy: phy@84000 {
+ compatible = "qcom,ipq6018-qmp-pcie-phy";
+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+
+ pcie_phy0: phy@84200 {
+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ #clock-cells = <0>;
+ };
+ };
+
+ mdio: mdio@90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
+ reg = <0x0 0x00090000 0x0 0x64>;
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ clock-names = "gcc_mdio_ahb_clk";
+ status = "disabled";
+ };
+
prng: qrng@e1000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;
@@ -257,6 +375,41 @@
reg = <0x0 0x01937000 0x0 0x21000>;
};
+ usb2: usb@70f8800 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x070F8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_SLEEP_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ clock-names = "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <24000000>;
+ resets = <&gcc GCC_USB1_BCR>;
+ status = "disabled";
+
+ dwc_1: usb@7000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x07000000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_1>;
+ phy-names = "usb2-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;
@@ -366,6 +519,49 @@
status = "disabled";
};
+ usb3: usb@8af8800 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x08af8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <24000000>;
+
+ resets = <&gcc GCC_USB0_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x08a00000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ clocks = <&xo>;
+ clock-names = "ref";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
#address-cells = <2>;
@@ -386,105 +582,6 @@
};
};
- pcie_phy: phy@84000 {
- compatible = "qcom,ipq6018-qmp-pcie-phy";
- reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&gcc GCC_PCIE0_AUX_CLK>,
- <&gcc GCC_PCIE0_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
-
- resets = <&gcc GCC_PCIE0_PHY_BCR>,
- <&gcc GCC_PCIE0PHY_PHY_BCR>;
- reset-names = "phy",
- "common";
-
- pcie_phy0: phy@84200 {
- reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
- <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
- <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_pcie0_pipe_clk_src";
- #clock-cells = <0>;
- };
- };
-
- pcie0: pci@20000000 {
- compatible = "qcom,pcie-ipq6018";
- reg = <0x0 0x20000000 0x0 0xf1d>,
- <0x0 0x20000f20 0x0 0xa8>,
- <0x0 0x20001000 0x0 0x1000>,
- <0x0 0x80000 0x0 0x4000>,
- <0x0 0x20100000 0x0 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
-
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- max-link-speed = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- phys = <&pcie_phy0>;
- phy-names = "pciephy";
-
- ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
- <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
-
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
- <&gcc GCC_PCIE0_AXI_M_CLK>,
- <&gcc GCC_PCIE0_AXI_S_CLK>,
- <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
- <&gcc PCIE0_RCHNG_CLK>;
- clock-names = "iface",
- "axi_m",
- "axi_s",
- "axi_bridge",
- "rchng";
-
- resets = <&gcc GCC_PCIE0_PIPE_ARES>,
- <&gcc GCC_PCIE0_SLEEP_ARES>,
- <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
- <&gcc GCC_PCIE0_AHB_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
- <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
- reset-names = "pipe",
- "sleep",
- "sticky",
- "axi_m",
- "axi_s",
- "ahb",
- "axi_m_sticky",
- "axi_s_sticky";
-
- status = "disabled";
- };
-
watchdog@b017000 {
compatible = "qcom,kpss-wdt";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
@@ -617,147 +714,74 @@
};
};
- mdio: mdio@90000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
- reg = <0x0 0x00090000 0x0 0x64>;
- clocks = <&gcc GCC_MDIO_AHB_CLK>;
- clock-names = "gcc_mdio_ahb_clk";
- status = "disabled";
- };
-
- qusb_phy_1: qusb@59000 {
- compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x00059000 0x0 0x180>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "cfg_ahb", "ref";
-
- resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
- status = "disabled";
- };
-
- usb2: usb@70f8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x070F8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clocks = <&gcc GCC_USB1_MASTER_CLK>,
- <&gcc GCC_USB1_SLEEP_CLK>,
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- clock-names = "core",
- "sleep",
- "mock_utmi";
-
- assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <24000000>;
- resets = <&gcc GCC_USB1_BCR>;
- status = "disabled";
-
- dwc_1: usb@7000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x07000000 0x0 0xcd00>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_1>;
- phy-names = "usb2-phy";
- tx-fifo-resize;
- snps,is-utmi-l1-suspend;
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- dr_mode = "host";
- };
- };
+ pcie0: pci@20000000 {
+ compatible = "qcom,pcie-ipq6018";
+ reg = <0x0 0x20000000 0x0 0xf1d>,
+ <0x0 0x20000f20 0x0 0xa8>,
+ <0x0 0x20001000 0x0 0x1000>,
+ <0x0 0x80000 0x0 0x4000>,
+ <0x0 0x20100000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
- ssphy_0: ssphy@78000 {
- compatible = "qcom,ipq6018-qmp-usb3-phy";
- reg = <0x0 0x00078000 0x0 0x1c4>;
- #address-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ max-link-speed = <3>;
+ #address-cells = <3>;
#size-cells = <2>;
- ranges;
-
- clocks = <&gcc GCC_USB0_AUX_CLK>,
- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
-
- resets = <&gcc GCC_USB0_PHY_BCR>,
- <&gcc GCC_USB3PHY_0_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
-
- usb0_ssphy: phy@78200 {
- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
- <0x0 0x00078400 0x0 0x200>, /* Rx */
- <0x0 0x00078800 0x0 0x1f8>, /* PCS */
- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_usb0_pipe_clk_src";
- };
- };
- qusb_phy_0: qusb@79000 {
- compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x00079000 0x0 0x180>;
- #phy-cells = <0>;
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "cfg_ahb", "ref";
+ ranges = <0x81000000 0 0x20200000 0 0x20200000
+ 0 0x10000>, /* downstream I/O */
+ <0x82000000 0 0x20220000 0 0x20220000
+ 0 0xfde0000>; /* non-prefetchable memory */
- resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
- status = "disabled";
- };
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
- usb3: usb@8af8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x8af8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
- <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_USB0_SLEEP_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
- clock-names = "cfg_noc",
- "core",
- "sleep",
- "mock_utmi";
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc PCIE0_RCHNG_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
- assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
- <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <133330000>,
- <24000000>;
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
- resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
-
- dwc_0: usb@8a00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x8a00000 0x0 0xcd00>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
- phy-names = "usb2-phy", "usb3-phy";
- clocks = <&xo>;
- clock-names = "ref";
- tx-fifo-resize;
- snps,is-utmi-l1-suspend;
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- dr_mode = "host";
- };
};
};
@@ -792,26 +816,4 @@
#interrupt-cells = <2>;
};
};
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: glink-channel {
- compatible = "qcom,rpm-ipq6018";
- qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
- };
- };
};

92
target/linux/qualcommax/patches-6.6/0035-v6.3-arm64-dts-qcom-ipq6018-Add-remove-some-newlines.patch
View File

@ -1,92 +0,0 @@
From 6db9ed9a128cbae1423d043f3debd8bfa77783fd Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:29 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Add/remove some newlines
Some lines were broken very aggresively, presumably to fit under 80 chars
and some places could have used a newline, particularly between subsequent
nodes. Address all that and remove redundant comments near PCIe ranges
while at it so as not to exceed 100 chars needlessly.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -102,26 +102,31 @@
opp-microvolt = <725000>;
clock-latency-ns = <200000>;
};
+
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <787500>;
clock-latency-ns = <200000>;
};
+
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;
clock-latency-ns = <200000>;
};
+
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-microvolt = <925000>;
clock-latency-ns = <200000>;
};
+
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;
clock-latency-ns = <200000>;
};
+
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500>;
@@ -131,8 +136,7 @@
pmuv8: pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci: psci {
@@ -734,24 +738,18 @@
phys = <&pcie_phy0>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x20200000 0 0x20200000
- 0 0x10000>, /* downstream I/O */
- <0x82000000 0 0x20220000 0 0x20220000
- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
+ <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,

25
target/linux/qualcommax/patches-6.6/0036-v6.3-arm64-dts-qcom-ipq6018-Use-lowercase-hex.patch
View File

@ -1,25 +0,0 @@
From 7356ae3e10abd1d71f06ff0b8a8e72aa7c955c57 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:30 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Use lowercase hex
One value escaped my previous lowercase hexification. Take care of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -381,7 +381,7 @@
usb2: usb@70f8800 {
compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x070F8800 0x0 0x400>;
+ reg = <0x0 0x070f8800 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;

28
target/linux/qualcommax/patches-6.6/0037-v6.3-arm64-dts-qcom-ipq6018-align-RPM-G-Link-node-with.patch
View File

@ -1,28 +0,0 @@
From 679ee73bbee28cab441008f8cca38160cc8f3d05 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 8 Feb 2023 11:15:39 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: align RPM G-Link node with
bindings
Bindings expect (and most of DTS use) the RPM G-Link node name to be
"rpm-requests".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208101545.45711-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -176,7 +176,7 @@
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
- rpm_requests: glink-channel {
+ rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq6018";
qcom,glink-channels = "rpm_requests";

27
target/linux/qualcommax/patches-6.6/0038-v6.4-arm64-dts-qcom-ipq6018-cp01-c1-drop-SPI-cs-select.patch
View File

@ -1,27 +0,0 @@
From afa8eb675fc6dd606783ed2350de90927d6fb9d3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 8 Mar 2023 13:59:01 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select
The SPI controller nodes do not use/allow cs-select property:
ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -36,7 +36,6 @@
};
&blsp1_spi1 {
- cs-select = <0>;
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";

92
target/linux/qualcommax/patches-6.6/0039-v6.5-arm64-dts-qcom-add-few-more-reserved-memory-region.patch
View File

@ -1,92 +0,0 @@
From 0cd4e90cb2dec02ff859f5c98f744f43a23aea65 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Fri, 26 May 2023 16:36:53 +0530
Subject: [PATCH] arm64: dts: qcom: add few more reserved memory region
In IPQ SoCs, bootloader will collect the system RAM contents upon crash
for the post morterm analysis. If we don't reserve the memory region used
by bootloader, obviously linux will consume it and upon next boot on
crash, bootloader will be loaded in the same region, which will lead to
loose some of the data, sometimes we may miss out critical information.
So lets reserve the region used by the bootloader.
Similarly SBL copies some data into the reserved region and it will be
used in the crash scenario. So reserve 1MB for SBL as well.
While at it, drop the size padding in the reserved memory region,
wherever applicable.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++--
2 files changed, 25 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -154,18 +154,28 @@
no-map;
};
+ bootloader@4a100000 {
+ reg = <0x0 0x4a100000 0x0 0x400000>;
+ no-map;
+ };
+
+ sbl@4a500000 {
+ reg = <0x0 0x4a500000 0x0 0x100000>;
+ no-map;
+ };
+
tz: memory@4a600000 {
- reg = <0x0 0x4a600000 0x0 0x00400000>;
+ reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
};
smem_region: memory@4aa00000 {
- reg = <0x0 0x4aa00000 0x0 0x00100000>;
+ reg = <0x0 0x4aa00000 0x0 0x100000>;
no-map;
};
q6_region: memory@4ab00000 {
- reg = <0x0 0x4ab00000 0x0 0x05500000>;
+ reg = <0x0 0x4ab00000 0x0 0x5500000>;
no-map;
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -85,17 +85,27 @@
#size-cells = <2>;
ranges;
+ bootloader@4a600000 {
+ reg = <0x0 0x4a600000 0x0 0x400000>;
+ no-map;
+ };
+
+ sbl@4aa00000 {
+ reg = <0x0 0x4aa00000 0x0 0x100000>;
+ no-map;
+ };
+
smem@4ab00000 {
compatible = "qcom,smem";
- reg = <0x0 0x4ab00000 0x0 0x00100000>;
+ reg = <0x0 0x4ab00000 0x0 0x100000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
memory@4ac00000 {
+ reg = <0x0 0x4ac00000 0x0 0x400000>;
no-map;
- reg = <0x0 0x4ac00000 0x0 0x00400000>;
};
};

49
target/linux/qualcommax/patches-6.6/0040-v6.5-arm64-dts-qcom-enable-the-download-mode-support.patch
View File

@ -1,49 +0,0 @@
From 9b2406aaba7841863ac041225316c1ec1c86ea36 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Fri, 26 May 2023 16:36:52 +0530
Subject: [PATCH] arm64: dts: qcom: enable the download mode support
Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the
download mode to collect the RAM dumps if system crashes, to perform
the post mortem analysis. Add support for the same.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++
2 files changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -90,6 +90,7 @@
firmware {
scm {
compatible = "qcom,scm-ipq6018", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x6100>;
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -112,6 +112,7 @@
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x6100>;
};
};
@@ -386,6 +387,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1937000 {
+ compatible = "qcom,tcsr-ipq8074", "syscon";
+ reg = <0x01937000 0x21000>;
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,

29
target/linux/qualcommax/patches-6.6/0041-v6.5-arm64-dts-qcom-ipq6018-correct-qrng-unit-address.patch
View File

@ -1,29 +0,0 @@
From 085058786a7890dd44ec623fe5ac74db870f6b93 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 19 Apr 2023 23:18:39 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: correct qrng unit address
Match unit-address to reg entry to fix dtbs W=1 warnings:
Warning (simple_bus_reg): /soc/qrng@e1000: simple-bus unit address format error, expected "e3000"
Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230419211856.79332-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -312,7 +312,7 @@
status = "disabled";
};
- prng: qrng@e1000 {
+ prng: qrng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;

28
target/linux/qualcommax/patches-6.6/0042-v6.5-arm64-dts-qcom-ipq6018-add-unit-address-to-soc-node.patch
View File

@ -1,28 +0,0 @@
From 393595d4ffbd0a1fafd5548f8de1b8487a037cf2 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 20 Apr 2023 08:36:04 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: add unit address to soc node
"soc" node is supposed to have unit address:
Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230420063610.11068-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -209,7 +209,7 @@
hwlocks = <&tcsr_mutex 3>;
};
- soc: soc {
+ soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x0 0xffffffff>;

34
target/linux/qualcommax/patches-6.6/0043-v6.5-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch
View File

@ -1,34 +0,0 @@
From 546f0617a22a481f3ca1f7e058aea0c40517c64e Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Fri, 26 May 2023 18:23:04 +0530
Subject: [PATCH] arm64: dts: qcom: ipq6018: add QFPROM node
IPQ6018 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -312,6 +312,13 @@
status = "disabled";
};
+ qfprom: efuse@a4000 {
+ compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
+ reg = <0x0 0x000a4000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
prng: qrng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;

37
target/linux/qualcommax/patches-6.6/0044-v6.5-arm64-dts-qcom-ipq6018-drop-incorrect-SPI-bus.patch
View File

@ -1,37 +0,0 @@
From b8420d478aa3fc739fcdba6b4b945850b356cb3b Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Sun, 16 Apr 2023 14:37:25 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: drop incorrect SPI bus
spi-max-frequency
The spi-max-frequency property belongs to SPI devices, not SPI
controller:
ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 --
1 file changed, 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -458,7 +458,6 @@
#size-cells = <0>;
reg = <0x0 0x078b5000 0x0 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
@@ -473,7 +472,6 @@
#size-cells = <0>;
reg = <0x0 0x078b6000 0x0 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";

29
target/linux/qualcommax/patches-6.6/0045-v6.5-arm64-dts-qcom-ipq8074-drop-incorrect-SPI-bus.patch
View File

@ -1,29 +0,0 @@
From e6e0e706940b64e3a77e0a4840037692f109bd5f Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Sun, 16 Apr 2023 14:37:26 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: drop incorrect SPI bus
spi-max-frequency
The spi-max-frequency property belongs to SPI devices, not SPI
controller:
ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -487,7 +487,6 @@
#size-cells = <0>;
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";

27
target/linux/qualcommax/patches-6.6/0046-v6.6-clk-qcom-gcc-ipq6018-Use-floor-ops-for-sdcc-clocks.patch
View File

@ -1,27 +0,0 @@
From 56e5ae0116aef87273cf1812d608645b076e4f02 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 25 Apr 2023 12:11:49 +0300
Subject: [PATCH] clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocks
SDCC clocks must be rounded down to avoid overclocking the controller.
Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
---
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -1702,7 +1702,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
.name = "usb0_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
.num_parents = 4,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};

27
target/linux/qualcommax/patches-6.6/0047-v6.6-clk-qcom-gcc-ipq6018-drop-redundant-F-define.patch
View File

@ -1,27 +0,0 @@
From 923f7d678b2ae3d522543058514d5605c185633b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 17 Apr 2023 19:44:07 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: drop redundant F define
The same exact F frequency table entry is defined in clk-rcg.h
Drop the redundant define to cleanup code.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
---
drivers/clk/qcom/gcc-ipq6018.c | 2 --
1 file changed, 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -26,8 +26,6 @@
#include "clk-regmap-mux.h"
#include "reset.h"
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
enum {
P_XO,
P_BIAS_PLL,

39
target/linux/qualcommax/patches-6.6/0048-v6.6-clk-qcom-gcc-ipq6018-update-UBI32-PLL.patch
View File

@ -1,39 +0,0 @@
From f4f0c8acee0e41c5fbae7a7ad06087668ddce0d6 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 26 May 2023 21:08:54 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: update UBI32 PLL
Update the UBI32 alpha PLL config to the latest values from the downstream
QCA 5.4 kernel.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq6018.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4143,15 +4143,20 @@ static struct clk_branch gcc_dcc_clk = {
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x3e,
- .alpha = 0x57,
+ .alpha = 0x6667,
.config_ctl_val = 0x240d6aa8,
.config_ctl_hi_val = 0x3c2,
+ .config_ctl_val = 0x240d4828,
+ .config_ctl_hi_val = 0x6,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.pre_div_val = 0x0,
.pre_div_mask = BIT(12),
.post_div_val = 0x0,
.post_div_mask = GENMASK(9, 8),
+ .alpha_en_mask = BIT(24),
+ .test_ctl_val = 0x1C0000C0,
+ .test_ctl_hi_val = 0x4000,
};
static const struct alpha_pll_config nss_crypto_pll_config = {

38
target/linux/qualcommax/patches-6.6/0049-v6.6-clk-qcom-gcc-ipq6018-remove-duplicate-initializers.patch
View File

@ -1,38 +0,0 @@
From 5ae7899765607e97e5eb34486336898c8d9ec654 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 1 Jun 2023 23:34:12 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: remove duplicate initializers
A recent change added new initializers for .config_ctl_val and
.config_ctl_hi_val but left the old values in place:
drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init]
4155 | .config_ctl_val = 0x240d4828,
| ^~~~~~~~~~
drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init]
4156 | .config_ctl_hi_val = 0x6,
| ^~~
Remove the unused ones now to avoid confusion.
Fixes: f4f0c8acee0e4 ("clk: qcom: gcc-ipq6018: update UBI32 PLL")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
---
drivers/clk/qcom/gcc-ipq6018.c | 2 --
1 file changed, 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4144,8 +4144,6 @@ static struct clk_branch gcc_dcc_clk = {
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x3e,
.alpha = 0x6667,
- .config_ctl_val = 0x240d6aa8,
- .config_ctl_hi_val = 0x3c2,
.config_ctl_val = 0x240d4828,
.config_ctl_hi_val = 0x6,
.main_output_mask = BIT(0),

132
target/linux/qualcommax/patches-6.6/0050-v6.6-soc-qcom-Add-RPM-processor-subsystem-driver.patch
View File

@ -1,132 +0,0 @@
From 8ddfa81d090c71fd6cb3cb8ca1d420c0da33a575 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan@gerhold.net>
Date: Thu, 15 Jun 2023 18:50:42 +0200
Subject: [PATCH] soc: qcom: Add RPM processor/subsystem driver
Add a simple driver for the qcom,rpm-proc compatible that registers the
"smd-edge" and populates other children defined in the device tree.
Note that the DT schema belongs to the remoteproc subsystem while this
driver is added inside soc/qcom. I argue that the RPM *is* a remoteproc,
but as an implementation detail in Linux it can currently not benefit
from anything provided by the remoteproc subsystem. The RPM firmware is
usually already loaded and started by earlier components in the boot
chain and is not meant to be ever restarted.
To avoid breaking existing kernel configurations the driver is always
built when smd-rpm.c is also built. They belong closely together anyway.
To avoid build errors CONFIG_RPMSG_QCOM_SMD must be also built-in if
rpm-proc is.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-9-a07dcdefd918@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/soc/qcom/Kconfig | 1 +
drivers/soc/qcom/Makefile | 2 +-
drivers/soc/qcom/rpm-proc.c | 77 +++++++++++++++++++++++++++++++++++++
3 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/qcom/rpm-proc.c
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -153,6 +153,7 @@ config QCOM_SMD_RPM
tristate "Qualcomm Resource Power Manager (RPM) over SMD"
depends on ARCH_QCOM || COMPILE_TEST
depends on RPMSG
+ depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
help
If you say yes to this option, support will be included for the
Resource Power Manager system found in the Qualcomm 8974 based
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_me
obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o
qcom_rpmh-y += rpmh-rsc.o
qcom_rpmh-y += rpmh.o
-obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
+obj-$(CONFIG_QCOM_SMD_RPM) += rpm-proc.o smd-rpm.o
obj-$(CONFIG_QCOM_SMEM) += smem.o
obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
--- /dev/null
+++ b/drivers/soc/qcom/rpm-proc.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/rpmsg/qcom_smd.h>
+
+static int rpm_proc_probe(struct platform_device *pdev)
+{
+ struct qcom_smd_edge *edge = NULL;
+ struct device *dev = &pdev->dev;
+ struct device_node *edge_node;
+ int ret;
+
+ edge_node = of_get_child_by_name(dev->of_node, "smd-edge");
+ if (edge_node) {
+ edge = qcom_smd_register_edge(dev, edge_node);
+ of_node_put(edge_node);
+ if (IS_ERR(edge))
+ return dev_err_probe(dev, PTR_ERR(edge),
+ "Failed to register smd-edge\n");
+ }
+
+ ret = devm_of_platform_populate(dev);
+ if (ret) {
+ dev_err(dev, "Failed to populate child devices: %d\n", ret);
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, edge);
+ return 0;
+err:
+ if (edge)
+ qcom_smd_unregister_edge(edge);
+ return ret;
+}
+
+static void rpm_proc_remove(struct platform_device *pdev)
+{
+ struct qcom_smd_edge *edge = platform_get_drvdata(pdev);
+
+ if (edge)
+ qcom_smd_unregister_edge(edge);
+}
+
+static const struct of_device_id rpm_proc_of_match[] = {
+ { .compatible = "qcom,rpm-proc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rpm_proc_of_match);
+
+static struct platform_driver rpm_proc_driver = {
+ .probe = rpm_proc_probe,
+ .remove_new = rpm_proc_remove,
+ .driver = {
+ .name = "qcom-rpm-proc",
+ .of_match_table = rpm_proc_of_match,
+ },
+};
+
+static int __init rpm_proc_init(void)
+{
+ return platform_driver_register(&rpm_proc_driver);
+}
+arch_initcall(rpm_proc_init);
+
+static void __exit rpm_proc_exit(void)
+{
+ platform_driver_unregister(&rpm_proc_driver);
+}
+module_exit(rpm_proc_exit);
+
+MODULE_DESCRIPTION("Qualcomm RPM processor/subsystem driver");
+MODULE_AUTHOR("Stephan Gerhold <stephan@gerhold.net>");
+MODULE_LICENSE("GPL");

93
target/linux/qualcommax/patches-6.6/0051-v6.6-arm64-dts-qcom-Add-rpm-proc-node-for-GLINK.patch
View File

@ -1,93 +0,0 @@
From 7e1acc8b92a3b67db1e5255adae2851d58d74434 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan@gerhold.net>
Date: Thu, 15 Jun 2023 18:50:44 +0200
Subject: [PATCH] arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms
Rather than having the RPM GLINK channels as the only child of a dummy
top-level rpm-glink node, switch to representing the RPM as remoteproc
like all the other remoteprocs (modem DSP, ...).
This allows assigning additional subdevices to it like the MPM
interrupt-controller or rpm-master-stats.
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6375
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++----
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++--
arch/arm64/boot/dts/qcom/msm8996.dtsi | 113 +++++++++----------
arch/arm64/boot/dts/qcom/msm8998.dtsi | 102 ++++++++---------
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 126 ++++++++++-----------
arch/arm64/boot/dts/qcom/qcs404.dtsi | 152 +++++++++++++-------------
arch/arm64/boot/dts/qcom/sdm630.dtsi | 132 +++++++++++-----------
arch/arm64/boot/dts/qcom/sm6115.dtsi | 128 +++++++++++-----------
arch/arm64/boot/dts/qcom/sm6125.dtsi | 140 ++++++++++++------------
arch/arm64/boot/dts/qcom/sm6375.dtsi | 126 ++++++++++-----------
10 files changed, 566 insertions(+), 529 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -145,6 +145,32 @@
method = "smc";
};
+ rpm: remoteproc {
+ compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-ipq6018";
+ qcom,glink-channels = "rpm_requests";
+
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -181,28 +207,6 @@
};
};
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-ipq6018";
- qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
- };
- };
-
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;

2
target/linux/qualcommax/patches-6.6/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch
View File

@ -22,7 +22,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -618,8 +618,8 @@
@@ -619,8 +619,8 @@
compatible = "qcom,ipq6018-apcs-apps-global";
reg = <0x0 0x0b111000 0x0 0x1000>;
#clock-cells = <1>;

4
target/linux/qualcommax/patches-6.6/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -2120,6 +2120,26 @@ static struct clk_branch gcc_blsp1_qup5_
@@ -2119,6 +2119,26 @@ static struct clk_branch gcc_blsp1_qup5_
},
};
@ -47,7 +47,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0700c,
.clkr = {
@@ -4276,6 +4296,7 @@ static struct clk_regmap *gcc_ipq6018_cl
@@ -4275,6 +4295,7 @@ static struct clk_regmap *gcc_ipq6018_cl
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,

4
target/linux/qualcommax/patches-6.6/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -95,42 +95,49 @@
@@ -96,42 +96,49 @@
};
cpu_opp_table: opp-table-cpu {
@ -71,7 +71,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clock-latency-ns = <200000>;
};
};
@@ -321,6 +328,11 @@
@@ -322,6 +329,11 @@
reg = <0x0 0x000a4000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;

4
target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -458,6 +458,26 @@
@@ -459,6 +459,26 @@
qcom,ee = <0>;
};
@ -42,7 +42,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x078b1000 0x0 0x200>;
@@ -466,6 +486,36 @@
@@ -467,6 +487,36 @@
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";

8
target/linux/qualcommax/patches-6.6/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch
View File

@ -36,7 +36,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -430,6 +430,12 @@
@@ -431,6 +431,12 @@
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<24000000>;
@ -49,7 +49,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
@@ -628,6 +634,13 @@
@@ -629,6 +635,13 @@
<133330000>,
<24000000>;
@ -65,7 +65,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -611,6 +611,13 @@
@@ -632,6 +632,13 @@
<133330000>,
<19200000>;
@ -79,7 +79,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
power-domains = <&gcc USB0_GDSC>;
resets = <&gcc GCC_USB0_BCR>;
@@ -653,6 +660,13 @@
@@ -674,6 +681,13 @@
<133330000>,
<19200000>;

2
target/linux/qualcommax/patches-6.6/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -342,6 +342,16 @@
@@ -343,6 +343,16 @@
clock-names = "core";
};

2
target/linux/qualcommax/patches-6.6/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch
View File

@ -55,7 +55,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
};
L2_0: l2-cache {
@@ -888,6 +893,122 @@
@@ -889,6 +894,122 @@
};
};

4
target/linux/qualcommax/patches-6.6/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -3523,6 +3523,22 @@ static struct clk_branch gcc_prng_ahb_cl
@@ -3522,6 +3522,22 @@ static struct clk_branch gcc_prng_ahb_cl
},
};
@ -40,7 +40,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.clkr = {
@@ -4362,6 +4378,7 @@ static struct clk_regmap *gcc_ipq6018_cl
@@ -4361,6 +4377,7 @@ static struct clk_regmap *gcc_ipq6018_cl
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,

58
target/linux/qualcommax/patches-6.6/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch
View File

@ -20,52 +20,8 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -233,6 +233,43 @@ static const struct qmp_phy_init_tbl ipq
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
};
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+ /* PLL and Loop filter settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+ /* SSC settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1591,6 +1628,26 @@ static const char * const qmp_phy_vreg_l
"vdda-phy", "vdda-pll",
@@ -1314,6 +1314,26 @@ static const struct qmp_usb_offsets qmp_
.rx = 0x1000,
};
+static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
@ -91,12 +47,12 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
.lanes = 1,
@@ -2534,7 +2591,7 @@ static const struct of_device_id qmp_usb
.data = &msm8996_usb3phy_cfg,
}, {
@@ -2238,7 +2258,7 @@ err_node_put:
static const struct of_device_id qmp_usb_of_match_table[] = {
{
.compatible = "qcom,ipq6018-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
+ .data = &ipq6018_usb3phy_cfg,
}, {
.compatible = "qcom,sc7180-qmp-usb3-phy",
.data = &sc7180_usb3phy_cfg,
.compatible = "qcom,ipq8074-qmp-usb3-phy",
.data = &ipq8074_usb3phy_cfg,

2
target/linux/qualcommax/patches-6.6/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -529,6 +529,20 @@
@@ -536,6 +536,20 @@
status = "disabled";
};

4
target/linux/qualcommax/patches-6.6/0100-clk-qcom-clk-rcg2-introduce-support-for-multiple-con.patch
View File

@ -176,7 +176,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
return 0;
}
@@ -351,6 +408,7 @@ static int __clk_rcg2_set_rate(struct cl
@@ -353,6 +410,7 @@ static int __clk_rcg2_set_rate(struct cl
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_tbl *f;
@ -184,7 +184,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
switch (policy) {
case FLOOR:
@@ -366,7 +424,15 @@ static int __clk_rcg2_set_rate(struct cl
@@ -368,7 +426,15 @@ static int __clk_rcg2_set_rate(struct cl
if (!f)
return -EINVAL;

8
target/linux/qualcommax/patches-6.6/0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch
View File

@ -23,7 +23,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1676,13 +1676,21 @@ static struct clk_regmap_div nss_port4_t
@@ -1675,13 +1675,21 @@ static struct clk_regmap_div nss_port4_t
},
};
@ -49,7 +49,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
{ }
@@ -1738,13 +1746,21 @@ static struct clk_regmap_div nss_port5_r
@@ -1737,13 +1745,21 @@ static struct clk_regmap_div nss_port5_r
},
};
@ -75,7 +75,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
{ }
@@ -1800,13 +1816,21 @@ static struct clk_regmap_div nss_port5_t
@@ -1799,13 +1815,21 @@ static struct clk_regmap_div nss_port5_t
},
};
@ -101,7 +101,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
{ }
@@ -1857,13 +1881,21 @@ static struct clk_regmap_div nss_port6_r
@@ -1856,13 +1880,21 @@ static struct clk_regmap_div nss_port6_r
},
};

4
target/linux/qualcommax/patches-6.6/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch
View File

@ -19,7 +19,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -85,6 +85,16 @@
@@ -86,6 +86,16 @@
#size-cells = <2>;
ranges;
@ -36,7 +36,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
bootloader@4a600000 {
reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
@@ -107,6 +117,21 @@
@@ -108,6 +118,21 @@
reg = <0x0 0x4ac00000 0x0 0x400000>;
no-map;
};

2
target/linux/qualcommax/patches-6.6/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -399,8 +399,8 @@
@@ -407,8 +407,8 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;

6
target/linux/qualcommax/patches-6.6/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -734,7 +734,7 @@
@@ -755,7 +755,7 @@
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
ranges = <0 0xb00a000 0xffd>;
@ -21,7 +21,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xffd>;
@@ -847,8 +847,7 @@
@@ -868,8 +868,7 @@
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
@ -31,7 +31,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142
@@ -909,8 +908,7 @@
@@ -930,8 +929,7 @@
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */

10
target/linux/qualcommax/patches-6.6/0112-remoteproc-qcom-Add-PRNG-proxy-clock.patch
View File

@ -86,7 +86,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
qcom_q6v5_unprepare(&wcss->q6v5);
return 0;
@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
@@ -899,7 +909,21 @@ static int q6v5_alloc_memory_region(stru
return 0;
}
@ -109,7 +109,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
{
int ret;
@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
@@ -989,7 +1013,7 @@ static int q6v5_wcss_init_clock(struct q
return 0;
}
@ -118,7 +118,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
{
wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
if (IS_ERR(wcss->cx_supply))
@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
@@ -1033,12 +1057,14 @@ static int q6v5_wcss_probe(struct platfo
if (ret)
goto free_rproc;
@ -136,7 +136,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
if (ret)
goto free_rproc;
}
@@ -1087,6 +1113,7 @@ static int q6v5_wcss_remove(struct platf
@@ -1084,6 +1110,7 @@ static void q6v5_wcss_remove(struct plat
}
static const struct wcss_data wcss_ipq8074_res_init = {
@ -144,7 +144,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
.firmware_name = "IPQ8074/q6_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
@@ -1096,6 +1123,8 @@ static const struct wcss_data wcss_ipq80
@@ -1093,6 +1120,8 @@ static const struct wcss_data wcss_ipq80
};
static const struct wcss_data wcss_qcs404_res_init = {

6
target/linux/qualcommax/patches-6.6/0113-remoteproc-qcom-Add-secure-PIL-support.patch
View File

@ -115,7 +115,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
if (ret)
return ret;
@@ -1036,6 +1068,9 @@ static int q6v5_wcss_probe(struct platfo
@@ -1035,6 +1067,9 @@ static int q6v5_wcss_probe(struct platfo
if (!desc)
return -EINVAL;
@ -125,7 +125,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
desc->firmware_name, sizeof(*wcss));
if (!rproc) {
@@ -1049,6 +1084,7 @@ static int q6v5_wcss_probe(struct platfo
@@ -1048,6 +1083,7 @@ static int q6v5_wcss_probe(struct platfo
wcss->version = desc->version;
wcss->requires_force_stop = desc->requires_force_stop;
@ -133,7 +133,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -1120,6 +1156,7 @@ static const struct wcss_data wcss_ipq80
@@ -1117,6 +1153,7 @@ static const struct wcss_data wcss_ipq80
.wcss_q6_reset_required = true,
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,

8
target/linux/qualcommax/patches-6.6/0114-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch
View File

@ -65,7 +65,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
if (wcss->need_mem_protection)
ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
WCNSS_PAS_ID, wcss->mem_region,
@@ -1072,7 +1095,7 @@ static int q6v5_wcss_probe(struct platfo
@@ -1071,7 +1094,7 @@ static int q6v5_wcss_probe(struct platfo
return -EPROBE_DEFER;
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
@ -74,7 +74,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
if (!rproc) {
dev_err(&pdev->dev, "failed to allocate rproc\n");
return -ENOMEM;
@@ -1085,6 +1108,7 @@ static int q6v5_wcss_probe(struct platfo
@@ -1084,6 +1107,7 @@ static int q6v5_wcss_probe(struct platfo
wcss->version = desc->version;
wcss->requires_force_stop = desc->requires_force_stop;
wcss->need_mem_protection = desc->need_mem_protection;
@ -82,7 +82,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -1150,7 +1174,8 @@ static int q6v5_wcss_remove(struct platf
@@ -1147,7 +1171,8 @@ static void q6v5_wcss_remove(struct plat
static const struct wcss_data wcss_ipq8074_res_init = {
.init_clock = ipq8074_init_clock,
@ -92,7 +92,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
@@ -1163,7 +1188,7 @@ static const struct wcss_data wcss_qcs40
@@ -1160,7 +1185,7 @@ static const struct wcss_data wcss_qcs40
.init_clock = qcs404_init_clock,
.init_regulator = qcs404_init_regulator,
.crash_reason_smem = WCSS_CRASH_REASON,

2
target/linux/qualcommax/patches-6.6/0115-remoteproc-qcom-Add-ssr-subdevice-identifier.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1179,6 +1179,7 @@ static const struct wcss_data wcss_ipq80
@@ -1176,6 +1176,7 @@ static const struct wcss_data wcss_ipq80
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,

6
target/linux/qualcommax/patches-6.6/0116-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch
View File

@ -48,7 +48,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
}
return 0;
@@ -929,9 +933,9 @@ static int q6v5_wcss_init_mmio(struct q6
@@ -928,9 +932,9 @@ static int q6v5_wcss_init_mmio(struct q6
return -EINVAL;
}
@ -61,7 +61,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
return 0;
}
@@ -1179,6 +1183,7 @@ static const struct wcss_data wcss_ipq80
@@ -1176,6 +1180,7 @@ static const struct wcss_data wcss_ipq80
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
@ -69,7 +69,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
.ssr_name = "q6wcss",
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
@@ -1193,6 +1198,7 @@ static const struct wcss_data wcss_qcs40
@@ -1190,6 +1195,7 @@ static const struct wcss_data wcss_qcs40
.version = WCSS_QCS404,
.aon_reset_required = false,
.wcss_q6_reset_required = false,

2
target/linux/qualcommax/patches-6.6/0118-clk-qcom-Add-WCSSAON-reset.patch
View File

@ -15,7 +15,7 @@ Acked-by: Stephen Boyd <sboyd@kernel.org>
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4711,6 +4711,7 @@ static const struct qcom_reset_map gcc_i
@@ -4710,6 +4710,7 @@ static const struct qcom_reset_map gcc_i
[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },

6
target/linux/qualcommax/patches-6.6/0119-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch
View File

@ -22,7 +22,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
};
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
@@ -1150,6 +1151,7 @@ static int q6v5_wcss_probe(struct platfo
@@ -1149,6 +1150,7 @@ static int q6v5_wcss_probe(struct platfo
desc->sysmon_name,
desc->ssctl_id);
@ -30,7 +30,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
ret = rproc_add(rproc);
if (ret)
goto free_rproc;
@@ -1188,6 +1190,7 @@ static const struct wcss_data wcss_ipq80
@@ -1185,6 +1187,7 @@ static const struct wcss_data wcss_ipq80
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
.need_mem_protection = true,
@ -38,7 +38,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
};
static const struct wcss_data wcss_qcs404_res_init = {
@@ -1204,6 +1207,7 @@ static const struct wcss_data wcss_qcs40
@@ -1201,6 +1204,7 @@ static const struct wcss_data wcss_qcs40
.ssctl_id = 0x12,
.ops = &q6v5_wcss_qcs404_ops,
.requires_force_stop = false,

12
target/linux/qualcommax/patches-6.6/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch
View File

@ -16,7 +16,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -141,6 +141,32 @@
@@ -142,6 +142,32 @@
};
};
@ -46,10 +46,10 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ };
+ };
+
soc: soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -417,6 +443,11 @@
soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -425,6 +451,11 @@
reg = <0x01937000 0x21000>;
};
@ -61,7 +61,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
@@ -949,6 +980,56 @@
@@ -970,6 +1001,56 @@
"axi_s_sticky";
status = "disabled";
};

2
target/linux/qualcommax/patches-6.6/0121-arm64-dts-ipq8074-Add-WLAN-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -1030,6 +1030,117 @@
@@ -1051,6 +1051,117 @@
};
};
};

19
target/linux/qualcommax/patches-6.6/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch
View File

@ -12,15 +12,10 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -343,6 +343,113 @@
status = "disabled";
};
+ qfprom: efuse@a4000 {
+ compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
+ reg = <0x000a4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
@@ -349,6 +349,106 @@
reg = <0x000a4000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpr_efuse_speedbin: speedbin@125 {
+ reg = <0x125 0x1>;
@ -121,8 +116,6 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ reg = <0x23c 0x1>;
+ bits = <0 7>;
+ };
+ };
+
};
prng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;

2
target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch
View File

@ -45,7 +45,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
};
L2_0: l2-cache {
@@ -83,6 +87,54 @@
@@ -84,6 +88,54 @@
};
};

8
target/linux/qualcommax/patches-6.6/0136-remoteproc-qcom-wcss-populate-driver-data-for-IPQ601.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -970,7 +970,7 @@ static int q6v5_alloc_memory_region(stru
@@ -969,7 +969,7 @@ static int q6v5_alloc_memory_region(stru
return 0;
}
@ -21,7 +21,7 @@ Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
{
int ret;
@@ -1179,7 +1179,7 @@ static int q6v5_wcss_remove(struct platf
@@ -1176,7 +1176,7 @@ static void q6v5_wcss_remove(struct plat
}
static const struct wcss_data wcss_ipq8074_res_init = {
@ -30,7 +30,7 @@ Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
.q6_firmware_name = "IPQ8074/q6_fw.mdt",
.m3_firmware_name = "IPQ8074/m3_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
@@ -1193,6 +1193,20 @@ static const struct wcss_data wcss_ipq80
@@ -1190,6 +1190,20 @@ static const struct wcss_data wcss_ipq80
.need_auto_boot = false,
};
@ -51,7 +51,7 @@ Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
static const struct wcss_data wcss_qcs404_res_init = {
.init_clock = qcs404_init_clock,
.init_regulator = qcs404_init_regulator,
@@ -1212,6 +1226,7 @@ static const struct wcss_data wcss_qcs40
@@ -1209,6 +1223,7 @@ static const struct wcss_data wcss_qcs40
static const struct of_device_id q6v5_wcss_of_match[] = {
{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },

2
target/linux/qualcommax/patches-6.6/0137-arm64-dts-qcom-ipq6018-add-SDHCI-node.patch
View File

@ -13,7 +13,7 @@ Tested-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -469,6 +469,29 @@
@@ -470,6 +470,29 @@
};
};

2
target/linux/qualcommax/patches-6.6/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -178,6 +178,11 @@
@@ -179,6 +179,11 @@
regulator-max-microvolt = <1062500>;
regulator-always-on;
};

2
target/linux/qualcommax/patches-6.6/0400-mtd-rawnand-add-support-for-TH58NYG3S0HBAI4.patch
View File

@ -30,7 +30,7 @@ Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -55,6 +55,9 @@ struct nand_flash_dev nand_flash_ids[] =
@@ -58,6 +58,9 @@ struct nand_flash_dev nand_flash_ids[] =
{ .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
NAND_ECC_INFO(40, SZ_1K) },

4
target/linux/qualcommax/patches-6.6/0901-regulator-add-Qualcomm-CPR-regulators.patch
View File

@ -25,7 +25,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -1524,4 +1524,37 @@ config REGULATOR_QCOM_LABIBB
@@ -1663,4 +1663,37 @@ config REGULATOR_QCOM_LABIBB
boost regulator and IBB can be used as a negative boost regulator
for LCD display panel.
@ -65,7 +65,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
endif
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -110,6 +110,9 @@ obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qco
@@ -116,6 +116,9 @@ obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qco
obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_SPMI) += qcom_spmi-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_USB_VBUS) += qcom_usb_vbus-regulator.o

12
target/linux/qualcommax/patches-6.6/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch
View File

@ -19,7 +19,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -361,7 +361,7 @@ static const struct freq_tbl ftbl_nss_pp
@@ -360,7 +360,7 @@ static const struct freq_tbl ftbl_nss_pp
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo" },
@ -28,7 +28,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
@@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po
@@ -526,12 +526,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data
gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo" },
@ -46,7 +46,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
};
static const struct parent_map
@@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po
@@ -573,12 +573,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data
gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo" },
@ -64,7 +64,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
};
static const struct parent_map
@@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po
@@ -714,10 +714,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo" },
@ -78,7 +78,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po
@@ -750,10 +750,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo" },
@ -92,7 +92,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1898,12 +1898,11 @@ static const struct freq_tbl ftbl_ubi32_
@@ -1897,12 +1897,11 @@ static const struct freq_tbl ftbl_ubi32_
{ }
};

4
target/linux/qualcommax/patches-6.6/0905-remoteproc-q6v5_wcss-change-ssr-name-for-ipq6018-wif.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1143,8 +1143,8 @@ static int q6v5_wcss_probe(struct platfo
@@ -1142,8 +1142,8 @@ static int q6v5_wcss_probe(struct platfo
if (ret)
goto free_rproc;
@ -29,7 +29,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
if (desc->ssctl_id)
wcss->sysmon = qcom_add_sysmon_subdev(rproc,
@@ -1201,7 +1201,7 @@ static const struct wcss_data wcss_ipq60
@@ -1198,7 +1198,7 @@ static const struct wcss_data wcss_ipq60
.aon_reset_required = true,
.wcss_q6_reset_required = true,
.bcr_reset_required = false,

2
target/linux/qualcommax/patches-6.6/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -807,6 +807,102 @@
@@ -808,6 +808,102 @@
};
};

2
target/linux/qualcommax/patches-6.6/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -1155,6 +1155,7 @@
@@ -1156,6 +1156,7 @@
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";

2
target/linux/qualcommax/patches-6.6/0908-remoteproc-qcom_q6v5_wcss-add-optional-qdss_at-clock.patch
View File

@ -40,7 +40,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
@@ -981,6 +987,12 @@ static int ipq_init_clock(struct q6v5_wc
@@ -980,6 +986,12 @@ static int ipq_init_clock(struct q6v5_wc
dev_err(wcss->dev, "Failed to get prng clock\n");
return ret;
}

2
target/linux/qualcommax/patches-6.6/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -928,8 +928,8 @@
@@ -929,8 +929,8 @@
"wcss_reset",
"wcss_q6_reset";

2
target/linux/qualcommax/patches-6.6/0910-arm64-dts-qcom-ipq6018-change-voltage-to-perf-levels.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -106,42 +106,42 @@
@@ -107,42 +107,42 @@
opp-864000000 {
opp-hz = /bits/ 64 <864000000>;