kernel/sifiveu: Restore kernel files for v6.1
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. See: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html for the original discussion. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
This commit is contained in:
Zoltan HERPAI
parent
9905057d7e
commit
bafdd7a67b
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@ -0,0 +1,392 @@
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CONFIG_64BIT=y
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CONFIG_ARCH_CLOCKSOURCE_INIT=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_MMAP_RND_BITS=18
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CONFIG_ARCH_MMAP_RND_BITS_MAX=24
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CONFIG_ARCH_MMAP_RND_BITS_MIN=18
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
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CONFIG_ARCH_RV64I=y
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CONFIG_ARCH_SELECT_MEMORY_MODEL=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_STACKWALK=y
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CONFIG_ARCH_WANTS_THP_SWAP=y
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CONFIG_ASN1=y
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CONFIG_ASSOCIATIVE_ARRAY=y
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CONFIG_ATA=y
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CONFIG_ATA_VERBOSE_ERROR=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_CAVIUM_PTP=y
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CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
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CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
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CONFIG_CC_NO_ARRAY_BOUNDS=y
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CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
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CONFIG_CLK_SIFIVE=y
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CONFIG_CLK_SIFIVE_PRCI=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CLZ_TAB=y
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CONFIG_CMODEL_MEDANY=y
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# CONFIG_CMODEL_MEDLOW is not set
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CONFIG_COMMON_CLK=y
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CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
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# CONFIG_COMPAT_32BIT_TIME is not set
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CONFIG_COMPAT_BRK=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTEXT_TRACKING=y
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CONFIG_CONTEXT_TRACKING_IDLE=y
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CONFIG_COREDUMP=y
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CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
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CONFIG_CPU_ISOLATION=y
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CONFIG_CPU_RMAP=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CRC7=y
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CONFIG_CRC_ITU_T=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_DRBG=y
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CONFIG_CRYPTO_DRBG_HMAC=y
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CONFIG_CRYPTO_DRBG_MENU=y
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CONFIG_CRYPTO_ECHAINIV=y
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CONFIG_CRYPTO_HMAC=y
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CONFIG_CRYPTO_JITTERENTROPY=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
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CONFIG_CRYPTO_LIB_SHA1=y
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CONFIG_CRYPTO_LIB_SHA256=y
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CONFIG_CRYPTO_LIB_UTILS=y
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CONFIG_CRYPTO_RNG=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_RNG_DEFAULT=y
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CONFIG_CRYPTO_RSA=y
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CONFIG_CRYPTO_SHA256=y
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CONFIG_CRYPTO_SHA512=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DECOMPRESS_GZIP=y
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DMA_DIRECT_REMAP=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_DUMMY_CONSOLE=y
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CONFIG_EDAC=y
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# CONFIG_EDAC_DEBUG is not set
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CONFIG_EDAC_LEGACY_SYSFS=y
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CONFIG_EDAC_SIFIVE=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EFI=y
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CONFIG_EFIVAR_FS=m
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# CONFIG_EFI_BOOTLOADER_CONTROL is not set
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# CONFIG_EFI_CAPSULE_LOADER is not set
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# CONFIG_EFI_COCO_SECRET is not set
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# CONFIG_EFI_DISABLE_PCI_DMA is not set
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# CONFIG_EFI_DISABLE_RUNTIME is not set
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CONFIG_EFI_EARLYCON=y
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CONFIG_EFI_ESRT=y
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CONFIG_EFI_GENERIC_STUB=y
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CONFIG_EFI_PARAMS_FROM_FDT=y
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CONFIG_EFI_RUNTIME_WRAPPERS=y
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CONFIG_EFI_STUB=y
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# CONFIG_EFI_TEST is not set
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# CONFIG_EFI_ZBOOT is not set
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CONFIG_ELF_CORE=y
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CONFIG_ERRATA_SIFIVE=y
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CONFIG_ERRATA_SIFIVE_CIP_1200=y
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CONFIG_ERRATA_SIFIVE_CIP_453=y
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# CONFIG_ERRATA_THEAD is not set
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CONFIG_EXCLUSIVE_SYSTEM_RAM=y
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CONFIG_EXT4_FS=y
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CONFIG_FAILOVER=y
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CONFIG_FAT_FS=y
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CONFIG_FHANDLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FONT_8x16=y
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CONFIG_FONT_AUTOSELECT=y
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CONFIG_FONT_SUPPORT=y
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CONFIG_FPU=y
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CONFIG_FRAME_POINTER=y
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_FW_LOADER_SYSFS=y
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CONFIG_GCC11_NO_ARRAY_BOUNDS=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CSUM=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IOREMAP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_INJECTION=y
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CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GLOB=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_CDEV_V1=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_SIFIVE=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HID=y
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CONFIG_HID_GENERIC=y
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CONFIG_HOTPLUG_PCI=y
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# CONFIG_HOTPLUG_PCI_CPCI is not set
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CONFIG_HOTPLUG_PCI_PCIE=y
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CONFIG_HOTPLUG_PCI_SHPC=y
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CONFIG_HVC_DRIVER=y
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CONFIG_HVC_RISCV_SBI=y
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CONFIG_HW_CONSOLE=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_COMPAT=y
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CONFIG_I2C_HELPER_AUTO=y
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CONFIG_I2C_OCORES=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_INPUT=y
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# CONFIG_IOMMU_DEBUGFS is not set
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CONFIG_IOMMU_SUPPORT=y
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CONFIG_IO_URING=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_JBD2=y
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CONFIG_KALLSYMS=y
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CONFIG_KEYS=y
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CONFIG_LEDS_PWM=y
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CONFIG_LEDS_TRIGGER_DISK=y
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CONFIG_LEGACY_PTYS=y
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CONFIG_LEGACY_PTY_COUNT=256
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CONFIG_LIBFDT=y
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CONFIG_LOCALVERSION_AUTO=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_LOCK_SPIN_ON_OWNER=y
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CONFIG_MACB=y
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# CONFIG_MACB_PCI is not set
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CONFIG_MACB_USE_HWSTAMP=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MFD_SYSCON=y
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CONFIG_MICROSEMI_PHY=y
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CONFIG_MIGRATION=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_CADENCE=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MMC_SPI=y
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CONFIG_MMIOWB=y
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CONFIG_MODULES_USE_ELF_RELA=y
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CONFIG_MODULE_SECTIONS=y
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CONFIG_MPILIB=y
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CONFIG_MQ_IOSCHED_DEADLINE=y
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CONFIG_MQ_IOSCHED_KYBER=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NET_FAILOVER=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_PTP_CLASSIFY=y
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CONFIG_NET_SELFTESTS=y
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CONFIG_NLS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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# CONFIG_NONPORTABLE is not set
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CONFIG_NR_CPUS=8
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CONFIG_NVMEM=y
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CONFIG_NVMEM_SYSFS=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_DMA_DEFAULT_COHERENT=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_KOBJ=y
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CONFIG_OF_MDIO=y
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CONFIG_OID_REGISTRY=y
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CONFIG_PADATA=y
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CONFIG_PAGE_OFFSET=0xff60000000000000
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CONFIG_PAGE_POOL=y
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CONFIG_PAGE_REPORTING=y
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CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
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CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
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CONFIG_PCI=y
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CONFIG_PCIEAER=y
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CONFIG_PCIEAER_INJECT=m
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CONFIG_PCIEASPM=y
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CONFIG_PCIEASPM_DEFAULT=y
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# CONFIG_PCIEASPM_PERFORMANCE is not set
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# CONFIG_PCIEASPM_POWERSAVE is not set
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# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCIE_DPC=y
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CONFIG_PCIE_DW=y
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CONFIG_PCIE_DW_HOST=y
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CONFIG_PCIE_ECRC=y
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CONFIG_PCIE_FU740=y
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CONFIG_PCIE_PTM=y
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CONFIG_PCIE_XILINX=y
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CONFIG_PCI_DEBUG=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DOMAINS_GENERIC=y
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CONFIG_PCI_ECAM=y
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CONFIG_PCI_HOST_COMMON=y
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CONFIG_PCI_HOST_GENERIC=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_MSI_IRQ_DOMAIN=y
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CONFIG_PCI_SW_SWITCHTEC=y
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CONFIG_PGTABLE_LEVELS=5
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CONFIG_PHYLIB=y
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CONFIG_PHYLINK=y
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CONFIG_PHYS_ADDR_T_64BIT=y
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CONFIG_PORTABLE=y
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CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_GPIO=y
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CONFIG_POWER_RESET_GPIO_RESTART=y
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CONFIG_POWER_RESET_RESTART=y
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CONFIG_POWER_RESET_SYSCON=y
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CONFIG_POWER_RESET_SYSCON_POWEROFF=y
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CONFIG_PPS=y
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CONFIG_PREEMPT_NONE_BUILD=y
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CONFIG_PRINTK_TIME=y
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CONFIG_PTP_1588_CLOCK=y
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
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CONFIG_PWM=y
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CONFIG_PWM_SIFIVE=y
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CONFIG_PWM_SYSFS=y
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CONFIG_QUEUED_RWLOCKS=y
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CONFIG_RANDSTRUCT_NONE=y
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CONFIG_RAS=y
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CONFIG_RATIONAL=y
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CONFIG_RCU_TRACE=y
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CONFIG_RD_GZIP=y
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||||
CONFIG_REALTEK_PHY=y
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CONFIG_REGMAP=y
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||||
CONFIG_REGMAP_MMIO=y
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# CONFIG_RESET_ATTACK_MITIGATION is not set
|
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RESET_SIMPLE=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RISCV=y
|
||||
CONFIG_RISCV_ALTERNATIVE=y
|
||||
# CONFIG_RISCV_BOOT_SPINWAIT is not set
|
||||
CONFIG_RISCV_DMA_NONCOHERENT=y
|
||||
CONFIG_RISCV_INTC=y
|
||||
CONFIG_RISCV_ISA_C=y
|
||||
CONFIG_RISCV_ISA_SVPBMT=y
|
||||
CONFIG_RISCV_ISA_ZICBOM=y
|
||||
CONFIG_RISCV_SBI=y
|
||||
CONFIG_RISCV_SBI_V01=y
|
||||
CONFIG_RISCV_TIMER=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_EFI is not set
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_DEBUG=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_SIFIVE=y
|
||||
CONFIG_SERIAL_SIFIVE_CONSOLE=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SIFIVE_CCACHE=y
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
|
||||
CONFIG_SOC_SIFIVE=y
|
||||
# CONFIG_SOC_STARFIVE is not set
|
||||
# CONFIG_SOC_VIRT is not set
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_SIFIVE=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKTRACE=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
# CONFIG_SYSFB_SIMPLEFB is not set
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TOOLCHAIN_HAS_ZICBOM=y
|
||||
CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
|
||||
CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TUNE_GENERIC=y
|
||||
CONFIG_UCS2_STRING=y
|
||||
CONFIG_UEVENT_HELPER_PATH=""
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
|
||||
CONFIG_USB_EHCI_PCI=y
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_NET_DRIVERS=y
|
||||
CONFIG_USB_PCI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
# CONFIG_USB_UHCI_HCD is not set
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PCI=y
|
||||
# CONFIG_USB_XHCI_PLATFORM is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_VGA_ARB=y
|
||||
CONFIG_VGA_ARB_MAX_GPUS=16
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
# CONFIG_VT_HW_CONSOLE_BINDING is not set
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
|
||||
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
||||
Date: Wed, 17 Feb 2021 06:06:14 -0800
|
||||
Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
|
||||
sifive,u74-mc
|
||||
|
||||
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
||||
---
|
||||
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
|
||||
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
|
||||
@@ -39,7 +39,7 @@
|
||||
};
|
||||
};
|
||||
cpu1: cpu@1 {
|
||||
- compatible = "sifive,bullet0", "riscv";
|
||||
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
@@ -63,7 +63,7 @@
|
||||
};
|
||||
};
|
||||
cpu2: cpu@2 {
|
||||
- compatible = "sifive,bullet0", "riscv";
|
||||
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
@@ -87,7 +87,7 @@
|
||||
};
|
||||
};
|
||||
cpu3: cpu@3 {
|
||||
- compatible = "sifive,bullet0", "riscv";
|
||||
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
@@ -111,7 +111,7 @@
|
||||
};
|
||||
};
|
||||
cpu4: cpu@4 {
|
||||
- compatible = "sifive,bullet0", "riscv";
|
||||
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
|
||||
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
||||
Date: Mon, 13 Sep 2021 02:18:30 -0700
|
||||
Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
|
||||
|
||||
Add gpio-poweroff node to allow powering off the system.
|
||||
|
||||
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
||||
---
|
||||
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
|
||||
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
|
||||
@@ -86,6 +86,11 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gpio-poweroff {
|
||||
+ compatible = "gpio-poweroff";
|
||||
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
|
||||
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
||||
Date: Fri, 14 May 2021 05:27:51 -0700
|
||||
Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
|
||||
|
||||
Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
|
||||
|
||||
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
||||
---
|
||||
arch/riscv/Kconfig | 8 +++++
|
||||
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
|
||||
.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
|
||||
3 files changed, 47 insertions(+)
|
||||
|
||||
--- a/arch/riscv/Kconfig
|
||||
+++ b/arch/riscv/Kconfig
|
||||
@@ -711,6 +711,14 @@ config PORTABLE
|
||||
select OF
|
||||
select MMU
|
||||
|
||||
+menu "CPU Power Management"
|
||||
+
|
||||
+source "drivers/cpuidle/Kconfig"
|
||||
+
|
||||
+source "drivers/cpufreq/Kconfig"
|
||||
+
|
||||
+endmenu
|
||||
+
|
||||
menu "Power management options"
|
||||
|
||||
source "kernel/power/Kconfig"
|
||||
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
|
||||
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
|
||||
@@ -30,6 +30,7 @@
|
||||
i-cache-size = <16384>;
|
||||
reg = <0>;
|
||||
riscv,isa = "rv64imac";
|
||||
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
|
||||
status = "disabled";
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
@@ -54,6 +55,7 @@
|
||||
reg = <1>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
|
||||
next-level-cache = <&l2cache>;
|
||||
cpu1_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
@@ -78,6 +80,7 @@
|
||||
reg = <2>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
|
||||
next-level-cache = <&l2cache>;
|
||||
cpu2_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
@@ -102,6 +105,7 @@
|
||||
reg = <3>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
|
||||
next-level-cache = <&l2cache>;
|
||||
cpu3_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
@@ -126,6 +130,7 @@
|
||||
reg = <4>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
|
||||
next-level-cache = <&l2cache>;
|
||||
cpu4_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
|
||||
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
|
||||
@@ -80,6 +80,40 @@
|
||||
label = "d4";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ fu540_c000_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-350000000 {
|
||||
+ opp-hz = /bits/ 64 <350000000>;
|
||||
+ };
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ };
|
||||
+ opp-999999999 {
|
||||
+ opp-hz = /bits/ 64 <999999999>;
|
||||
+ };
|
||||
+ opp-1400000000 {
|
||||
+ opp-hz = /bits/ 64 <1400000000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ operating-points-v2 = <&fu540_c000_opp_table>;
|
||||
+};
|
||||
+&cpu1 {
|
||||
+ operating-points-v2 = <&fu540_c000_opp_table>;
|
||||
+};
|
||||
+&cpu2 {
|
||||
+ operating-points-v2 = <&fu540_c000_opp_table>;
|
||||
+};
|
||||
+&cpu3 {
|
||||
+ operating-points-v2 = <&fu540_c000_opp_table>;
|
||||
+};
|
||||
+&cpu4 {
|
||||
+ operating-points-v2 = <&fu540_c000_opp_table>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
Loading…
Reference in New Issue