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drop unmaintained packages

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SVN-Revision: 33723
This commit is contained in:
John Crispin 2012-10-11 10:05:13 +00:00
parent 06218a992e
commit a95775e4b2
108 changed files with 0 additions and 24332 deletions
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48
package/ltq-kpi2udp/Makefile
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@ -1,48 +0,0 @@
#
# Copyright (C) 2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=drv_kpi2udp
PKG_VERSION:=2.2.0
PKG_RELEASE:=1
PKG_SOURCE:=drv_kpi2udp-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
PKG_MD5SUM:=af3855609554c7f3d2c3df8c597f50a7
include $(INCLUDE_DIR)/package.mk
define KernelPackage/ltq-kpi2udp
SUBMENU:=Voice over IP
TITLE:=TAPI KPI2UDP plug-in
URL:=http://www.lantiq.com/
DEPENDS:=+kmod-ltq-tapi @TARGET_lantiq
FILES:=$(PKG_BUILD_DIR)/drv_kpi2udp.ko
AUTOLOAD:=$(call AutoLoad,26,drv_kpi2udp)
MAINTAINER:=John Crispin <blogic@openwrt.org>
endef
define KernelPackage/ltq-kpi2udp/description
RTP packet path accelleration into IP stack (strongly recommended)
endef
CONFIGURE_ARGS += --enable-kernelincl="$(LINUX_DIR)/include" \
--enable-tapiincl="$(STAGING_DIR)/usr/include/drv_tapi" \
--with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \
--enable-warning \
--enable-linux-26 \
--enable-kernelbuild="$(LINUX_DIR)" \
ARCH=$(LINUX_KARCH)
define Build/Configure
(cd $(PKG_BUILD_DIR); aclocal && autoconf && automake)
$(call Build/Configure/Default)
endef
$(eval $(call KernelPackage,ltq-kpi2udp))

11
package/ltq-kpi2udp/patches/100-configure.patch
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@ -1,11 +0,0 @@
--- a/configure.in
+++ b/configure.in
@@ -113,7 +113,7 @@
AC_ARG_ENABLE(kernelbuild,
AS_HELP_STRING(--enable-kernelbuild=x,Set the target kernel build path),
[
- if test -r $enableval/include/linux/autoconf.h; then
+ if test -r $enableval/include/generated/autoconf.h; then
AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
else
AC_MSG_ERROR([The kernel build directory is not valid or not configured!])

29
package/ltq-kpi2udp/patches/110-ifx_udp_redirect.patch
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@ -1,29 +0,0 @@
--- a/ifx_udp_redirect.c
+++ b/ifx_udp_redirect.c
@@ -256,7 +256,7 @@
{
if (redtab.channels[i].in_use == IFX_TRUE)
{
- if (redtab.channels[i].sk->sk_lock.owner != 0)
+ if (redtab.channels[i].sk->sk_lock.owned != 0)
return IFX_TRUE;
}
}
@@ -545,7 +545,7 @@
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
if (sk->num != htons(sport))
#else
- if (((struct inet_sock *)sk)->num != htons(sport))
+ if (((struct inet_sock *)sk)->inet_num != htons(sport))
#endif
{
return CALL_MK_SESSION_ERR;
@@ -628,7 +628,7 @@
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
if((vsock != NULL)&&(vsk != NULL)&&(vsk->num > 0))
#else
- if((vsock != NULL)&&(vsk != NULL)&&(((struct inet_sock *)vsk)->num > 0))
+ if((vsock != NULL)&&(vsk != NULL)&&(((struct inet_sock *)vsk)->inet_num > 0))
#endif
{
/*printk("[KPI2UDP] releasing vsock...%p, ops %p\n", vsock, vsock->ops);*/

47
package/ltq-tapidemo/Config.in
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@ -1,47 +0,0 @@
choice
prompt "board selection"
depends on PACKAGE_ltq-tapidemo
default VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3 if TARGET_lantiq_danube
default VOICE_CPE_TAPIDEMO_BOARD_EASY508xx if TARGET_lantiq_ar9
default VOICE_CPE_TAPIDEMO_BOARD_EASY80910 if TARGET_lantiq_vr9
help
Select the target platform.
config VOICE_CPE_TAPIDEMO_BOARD_EASY50712
bool "Danube reference board"
config VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3
bool "Danube reference board V3"
config VOICE_CPE_TAPIDEMO_BOARD_EASY508xx
bool "AR9/GR9 reference board"
config VOICE_CPE_TAPIDEMO_BOARD_EASY80910
bool "VR9 reference board"
endchoice
config VOICE_CPE_TAPIDEMO_QOS
bool "enable QOS support"
depends on PACKAGE_ltq-tapidemo
select PACKAGE_kmod-ltq-kpi2udp
default y
help
Option to enable the KPI2UDP RTP packet acceleration path
(highly recommended for VoIP).
config VOICE_CPE_TAPIDEMO_FAX_T.38_FW
bool "enable T.38 fax relay"
depends on (TARGET_lantiq_ar9 || TARGET_lantiq_vr9) && PACKAGE_ltq-tapidemo
default n
help
enable T.38 fax relay demo.
config VOICE_CPE_TAPIDEMO_FW_FILE
string "override default firmware file"
depends on PACKAGE_ltq-tapidemo
default "falcon_voip_fw.bin" if TARGET_lantiq_falcon
config VOICE_CPE_TAPIDEMO_BBD_FILE
string "override default coefficient file"
depends on PACKAGE_ltq-tapidemo
default "falcon_bbd.bin" if TARGET_lantiq_falcon

82
package/ltq-tapidemo/Makefile
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@ -1,82 +0,0 @@
#
# Copyright (C) 2008-2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=tapidemo
PKG_VERSION:=5.1.0.53
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
PKG_MD5SUM:=c970becc46b2935fb9e18f795d4e8469
PKG_FIXUP:=autoreconf
include $(INCLUDE_DIR)/ltqtapi.mk
include $(INCLUDE_DIR)/package.mk
define Package/ltq-tapidemo
SUBMENU:=Telephony
SECTION:=net
CATEGORY:=Network
TITLE:=TAPIdemo application for Lantiq boards
URL:=http://www.lantiq.com/
DEPENDS:=$(LTQ_TAPI_DEPENDS) +libpthread
MAINTAINER:=John Crispin <blogic@openwrt.org>
MENU:=1
endef
define Package/ltq-tapidemo/description
Voice Access mini-PBX Demo Application
endef
define Package/ltq-tapidemo/config
source "$(SOURCE)/Config.in"
endef
TARGET_LDFLAGS+=-lpthread
CONFIGURE_ARGS += \
ARCH=$(LINUX_KARCH) \
--enable-linux-26 \
--enable-kernelincl="$(LINUX_DIR)/include" \
--with-drvincl="$(STAGING_DIR)/usr/include" \
--with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \
--with-ifxos-lib=$(STAGING_DIR)/usr/lib \
$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_QOS,qos) \
$(call autoconf_bool,CONFIG_VOICE_CPE_TAPIDEMO_FAX_T,fax-t38) \
--enable-trace \
--enable-fs
ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712),y)
CONFIGURE_ARGS += --enable-boardname=EASY50712
endif
ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3),y)
CONFIGURE_ARGS += --enable-boardname=EASY50712_V3
endif
ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY508xx),y)
CONFIGURE_ARGS += --enable-boardname=EASY508XX
endif
ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY80910),y)
CONFIGURE_ARGS += --enable-boardname=EASY508XX
endif
ifneq ($(CONFIG_VOICE_CPE_TAPIDEMO_FW_FILE),)
CONFIGURE_ARGS += --with-fw-file="$(strip $(subst ",, $(CONFIG_VOICE_CPE_TAPIDEMO_FW_FILE)))"
endif
ifneq ($(CONFIG_VOICE_CPE_TAPIDEMO_BBD_FILE), "")
CONFIGURE_ARGS += --with-bbd-file="$(strip $(subst ",, $(CONFIG_VOICE_CPE_TAPIDEMO_BBD_FILE)))"
endif
define Package/ltq-tapidemo/install
$(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d/
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/tapidemo $(1)/usr/sbin
$(INSTALL_BIN) ./files/bringup_tapidemo $(1)/etc/init.d/tapidemo
endef
$(eval $(call BuildPackage,ltq-tapidemo))

89
package/ltq-tapidemo/files/bringup_tapidemo
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@ -1,89 +0,0 @@
#!/bin/sh /etc/rc.common
# (C) 2008 openwrt.org
START=96
[ ! -f /dev/vmmc10 ] && {
mknod /dev/vmmc10 c 122 10
mknod /dev/vmmc11 c 122 11
mknod /dev/vmmc12 c 122 12
mknod /dev/vmmc13 c 122 13
mknod /dev/vmmc14 c 122 14
mknod /dev/vmmc15 c 122 15
mknod /dev/vmmc16 c 122 16
mknod /dev/vmmc17 c 122 17
mknod /dev/vmmc18 c 122 18
}
TD_EXTRA_FLAGS_FXO=
TD_EXTRA_FLAGS_KPI2UDP=
TD_DOWNLOAD_PATH=/lib/firmware/
DEV_NODE_TERIDIAN=ter10
# Show help
help()
{
echo "Usage:"
echo " - $0 WAN-IF-NAME - start TAPIDEMO without FXO support"
echo " - $0 WAN-IF-NAME fxo - start TAPIDEMO with FXO support."
echo " - $0 stop - stop TAPIDEMO"
}
# Check if device node for Teridian exists
checkFxoSupport()
{
if [ ! -e /dev/$DEV_NODE_TERIDIAN ];then
echo "FXO support is disabled. Can not find required driver's device node."
else
TD_EXTRA_FLAGS_FXO="-x"
fi
}
# Check if module drv_kpi2udp is loaded
checkKpi2UdpSupport()
{
tmp=`cat /proc/modules | grep 'drv_kpi2udp '`
if [ "$tmp" != "" ]; then
TD_EXTRA_FLAGS_KPI2UDP="-q"
fi
}
start()
{
TD_WANIF=$1
TD_WANIF_IP=`ifconfig $TD_WANIF | grep 'inet addr:' | cut -f2 -d: | cut -f1 -d' '`
if [ "$TD_WANIF_IP" = "" ]; then
echo "Error, getting IP address for network device $TD_WANIF failed."
exit 1
fi
if [ "$2" = "" ];then
# FXO support is disabled.
continue
elif [ "$2" = "fxo" ];then
checkFxoSupport
else
echo "Error, unknown second parameter."
help
exit 1
fi
checkKpi2UdpSupport
if [ -r /etc/rc.conf ]; then
. /etc/rc.conf
fi
TD_DEBUG_LEVEL=$tapiDebugLevel
if [ "$TD_DEBUG_LEVEL" = "" ]; then
TD_DEBUG_LEVEL=3
fi
/usr/sbin/tapidemo -d $TD_DEBUG_LEVEL $TD_EXTRA_FLAGS_FXO $TD_EXTRA_FLAGS_KPI2UDP -i $TD_WANIF_IP -l $TD_DOWNLOAD_PATH &
}
stop()
{
killall tapidemo > /dev/null 2> /dev/null
}

61
package/ltq-tapidemo/patches/100-ifxmips.patch
View File

@ -1,61 +0,0 @@
--- a/src/board_easy50712.c
+++ b/src/board_easy50712.c
@@ -32,7 +32,9 @@
#ifdef OLD_BSP
#include "asm/danube/port.h"
#else
- #include "asm/ifx/ifx_gpio.h"
+#ifdef FXO
+# include "asm/ifx/ifx_gpio.h"
+#endif
#endif
/* ============================= */
--- a/src/board_easy508xx.c
+++ b/src/board_easy508xx.c
@@ -32,8 +32,6 @@
#endif /* FXO */
#include "pcm.h"
-#include "asm/ifx/ifx_gpio.h"
-
#ifdef TD_DECT
#include "td_dect.h"
#endif /* TD_DECT */
--- a/src/common.c
+++ b/src/common.c
@@ -7117,7 +7117,7 @@ IFX_return_t Common_GPIO_ClosePort(IFX_c
IFX_return_t Common_GPIO_ReservePin(IFX_int32_t nFd, IFX_int32_t nPort,
IFX_int32_t nPin, IFX_int32_t nModule)
{
-#ifndef OLD_BSP
+#if !defined(OLD_BSP) && defined(IFX_GPIO_IOC_PIN_RESERVE)
TD_PARAMETER_CHECK((NO_GPIO_FD >= nFd), nFd, IFX_ERROR);
IFX_return_t nRet;
@@ -7155,7 +7155,7 @@ IFX_return_t Common_GPIO_ReservePin(IFX_
IFX_return_t Common_GPIO_FreePin(IFX_int32_t nFd, IFX_int32_t nPort,
IFX_int32_t nPin, IFX_int32_t nModule)
{
-#ifndef OLD_BSP
+#if !defined(OLD_BSP) && defined(IFX_GPIO_IOC_PIN_RESERVE)
TD_PARAMETER_CHECK((NO_GPIO_FD >= nFd), nFd, IFX_ERROR);
IFX_return_t nRet;
--- a/src/common.h
+++ b/src/common.h
@@ -79,12 +79,12 @@
#ifdef OLD_BSP
#include "asm/danube/port.h"
#else
- #include "asm/ifx/ifx_gpio.h"
+ /*#include "asm/ifx/ifx_gpio.h"*/
#endif
#endif
#if (defined(AR9) || defined(VR9))
- #include "asm/ifx/ifx_gpio.h"
+ /*#include "asm/ifx/ifx_gpio.h"*/
#endif
#ifdef TD_DECT

141
package/ltq-tapidemo/patches/110-filename.patch
View File

@ -1,141 +0,0 @@
--- a/configure.in
+++ b/configure.in
@@ -1665,6 +1665,30 @@ AC_ARG_WITH(cflags,
]
)
+dnl overwrite default FW file name
+AC_ARG_WITH(fw-file,
+ AS_HELP_STRING(
+ [--with-fw-file=val],
+ [overwrite default FW file name]
+ ),
+ [
+ AC_MSG_RESULT([using firmware file $withval])
+ AC_DEFINE_UNQUOTED([TD_FW_FILE], ["$withval"], [using firmware file])
+ ]
+)
+
+dnl overwrite default BBD file name
+AC_ARG_WITH(bbd-file,
+ AS_HELP_STRING(
+ [--with-bbd-file=val],
+ [overwrite default BBD file name]
+ ),
+ [
+ AC_MSG_RESULT([using BBD file $withval])
+ AC_DEFINE_UNQUOTED([TD_BBD_FILE], ["$withval"], [using BBD file])
+ ]
+)
+
AC_CONFIG_FILES([Makefile])
AC_CONFIG_FILES([src/Makefile])
--- a/src/device_vmmc.c
+++ b/src/device_vmmc.c
@@ -49,40 +49,55 @@
#ifdef USE_FILESYSTEM
+#ifdef TD_BBD_FILE
+ IFX_char_t* sBBD_CRAM_File_VMMC = TD_BBD_FILE;
+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = TD_BBD_FILE;
+#else
+ /** File holding coefficients. */
+#ifdef DANUBE
+ /** Prepare file names for DANUBE */
+ IFX_char_t* sBBD_CRAM_File_VMMC = "danube_bbd.bin";
+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "danube_bbd_fxs.bin";
+#elif AR9
+ IFX_char_t* sBBD_CRAM_File_VMMC = "ar9_bbd.bin";
+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "ar9_bbd_fxs.bin";
+#elif VINAX
+ IFX_char_t* sBBD_CRAM_File_VMMC = "bbd.bin";
+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "";
+#elif VR9
+ IFX_char_t* sBBD_CRAM_File_VMMC = "vr9_bbd.bin";
+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "vr9_bbd_fxs.bin";
+#else
+#endif
+#endif /* TD_BBD_FILE */
+#ifdef TD_FW_FILE
+ IFX_char_t* sPRAMFile_VMMC = TD_FW_FILE;
+ IFX_char_t* sPRAMFile_VMMC_Old = TD_FW_FILE;
+ IFX_char_t* sDRAMFile_VMMC = "";
+#else
#ifdef DANUBE
/** Prepare file names for DANUBE */
IFX_char_t* sPRAMFile_VMMC = "voice_danube_firmware.bin";
IFX_char_t* sPRAMFile_VMMC_Old = "danube_firmware.bin";
IFX_char_t* sDRAMFile_VMMC = "";
- /** File holding coefficients. */
- IFX_char_t* sBBD_CRAM_File_VMMC = "danube_bbd.bin";
- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "danube_bbd_fxs.bin";
#elif AR9
/** Prepare file names for AR9 */
IFX_char_t* sPRAMFile_VMMC = "voice_ar9_firmware.bin";
IFX_char_t* sPRAMFile_VMMC_Old = "ar9_firmware.bin";
IFX_char_t* sDRAMFile_VMMC = "";
- /** File holding coefficients. */
- IFX_char_t* sBBD_CRAM_File_VMMC = "ar9_bbd.bin";
- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "ar9_bbd_fxs.bin";
#elif VINAX
/** Prepare file names for VINAX */
IFX_char_t* sPRAMFile_VMMC = "voice_vinax_firmware.bin";
IFX_char_t* sPRAMFile_VMMC_Old = "firmware.bin";
IFX_char_t* sDRAMFile_VMMC = "";
- /** File holding coefficients. */
- IFX_char_t* sBBD_CRAM_File_VMMC = "bbd.bin";
- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "";
#elif VR9
/** Prepare file names for VR9 */
IFX_char_t* sPRAMFile_VMMC = "voice_vr9_firmware.bin";
IFX_char_t* sPRAMFile_VMMC_Old = "vr9_firmware.bin";
IFX_char_t* sDRAMFile_VMMC = "";
- /** File holding coefficients. */
- IFX_char_t* sBBD_CRAM_File_VMMC = "vr9_bbd.bin";
- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "vr9_bbd_fxs.bin";
#else
#endif
+#endif /* TD_FW_FILE */
#endif /* USE_FILESYSTEM */
/** Device names */
--- a/src/common.c
+++ b/src/common.c
@@ -509,6 +509,10 @@ IFX_return_t Common_CheckDownloadPath(IF
if (IFX_TRUE != Common_FindBBD_CRAM(pCpuDevice, psPath, psFile))
{
ret = IFX_ERROR;
+ if(bPrintTrace)
+ TRACE(TAPIDEMO, DBG_LEVEL_LOW,
+ ("Download path %s does not contain the required file %s.\n",
+ psPath, psFile));
}
if ((IFX_SUCCESS == ret) &&
@@ -521,6 +525,10 @@ IFX_return_t Common_CheckDownloadPath(IF
{
ret = Common_CheckFileExists(psFile);
}
+ if(bPrintTrace && ret != IFX_SUCCESS)
+ TRACE(TAPIDEMO, DBG_LEVEL_LOW,
+ ("Download path %s does not contain the required file %s.\n",
+ psPath, psFile));
}
#ifndef TAPI_VERSION4
if (IFX_SUCCESS == ret)
@@ -532,13 +540,6 @@ IFX_return_t Common_CheckDownloadPath(IF
}
#endif
- if (IFX_ERROR == ret)
- {
- if(bPrintTrace)
- TRACE(TAPIDEMO, DBG_LEVEL_LOW,
- ("Download path %s does not contain the required files.\n",
- psPath));
- }
return ret;
} /* Common_CheckDownloadPath */

73
package/owsip/Makefile
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@ -1,73 +0,0 @@
#
# Copyright (C) 2012 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
OWSIP_VERSION=2012-02-14
OWSIP_RELEASE=1
PKG_NAME:=owsip
PKG_VERSION:=$(OWSIP_VERSION)$(if $(OWSIP_RELEASE),.$(OWSIP_RELEASE))
PKG_RELEASE:=1
PKG_REV:=da53a53db28b47ca1714ffba72d0df5bea357706
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=git://nbd.name/owsip.git
PKG_SOURCE_SUBDIR:=owsip-$(PKG_VERSION)
PKG_SOURCE_VERSION:=$(PKG_REV)
PKG_SOURCE_PROTO:=git
PKG_MIRROR_MD5SUM:=74b0ab930321c4f85f220ff3852e210a
include $(INCLUDE_DIR)/ltqtapi.mk
include $(INCLUDE_DIR)/package.mk
define Package/owsip-template
SUBMENU:=Telephony
SECTION:=net
CATEGORY:=Network
TITLE:=owsip using $(2)
VARIANT:=$(1)
DEPENDS:=+librt +libuci +libubox +pjsip-$(1) $(3)
endef
Package/owsip-oss=$(call Package/owsip-template,oss,OSS,BROKEN)
Package/owsip-ltq-tapi=$(call Package/owsip-template,ltq-tapi,Lantiq VMMC,$(LTQ_TAPI_DEPENDS) +kmod-ltq-kpi2udp)
define Package/owsip-$(BUILD_VARIANT)/description
OpenWrt sip daemon - $(BUILD_VARIANT)
endef
USE_LOCAL=$(shell ls ./src/ 2>/dev/null >/dev/null && echo 1)
ifneq ($(USE_LOCAL),)
define Build/Prepare
$(CP) ./src/* $(PKG_BUILD_DIR)/
endef
endif
EXTRA_CFLAGS=-I$(STAGING_DIR)/usr/include -I$(STAGING_DIR)/include \
-I$(STAGING_DIR)/usr/pjsip-$(BUILD_VARIANT)/include
EXTRA_LDFLAGS=-L$(STAGING_DIR)/usr/lib -L$(STAGING_DIR)/usr/pjsip-$(BUILD_VARIANT)/lib
define Build/Compile
PKG_CONFIG_PATH=$(STAGING_DIR)/usr/pjsip-$(BUILD_VARIANT)/lib/pkgconfig \
BACKEND=$(BUILD_VARIANT) CFLAGS="$(EXTRA_CFLAGS)" LDFLAGS="$(EXTRA_LDFLAGS)" $(MAKE) -C $(PKG_BUILD_DIR) $(TARGET_CONFIGURE_OPTS)
endef
define Package/owsip-$(BUILD_VARIANT)/conffiles
/etc/config/telephony.conf
endef
define Package/owsip-$(BUILD_VARIANT)/install
$(INSTALL_DIR) $(1)/usr/bin $(1)/etc/init.d $(1)/etc/config $(1)/etc/uci-defaults
$(INSTALL_BIN) $(PKG_BUILD_DIR)/owsip_ua $(1)/usr/bin
$(INSTALL_BIN) ./files/telephony.init $(1)/etc/init.d/telephony
$(INSTALL_DATA) ./files/telephony.conf $(1)/etc/config/telephony
$(INSTALL_DATA) ./files/telephony.defaults $(1)/etc/uci-defaults/telephony
endef
$(eval $(call BuildPackage,owsip-oss))
$(eval $(call BuildPackage,owsip-ltq-tapi))

32
package/owsip/files/telephony.conf
View File

@ -1,32 +0,0 @@
config general general
option name owsip
option backend ltq_tapi
option ossdev 0
option log_level 3
option interface nas0
option local_port 5060
option rtp_port 4000
option locale germany
config stun stun
option host stun.myrealm.com
option port 3478
config account example1
option realm myrealm1.com
option username myuser1
option password mypass1
option disabled 1
config account example2
option realm myrealm2.com
option username myuser2
option password mypass2
option disabled 1
config contact
option desc "example contact description"
option code "example"
option dial "0123456789"
option type realm

55
package/owsip/files/telephony.defaults
View File

@ -1,55 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2011 OpenWrt.org
# based on ar71xx
#
COMMIT_TELEPHONY=0
set_relay() {
local cfg="relay_$1"
local gpio=$1
local val=$2
uci -q get telephony.$cfg && return 0
uci batch <<EOF
set telephony.$cfg='relay'
set telephony.$cfg.gpio='$gpio'
set telephony.$cfg.value='$val'
EOF
COMMIT_TELEPHONY=1
}
set_port() {
local cfg="port$1"
local id=$1
local led=$2
uci -q get telephony.$cfg && return 0
uci batch <<EOF
set telephony.$cfg='port'
set telephony.$cfg.id='$id'
set telephony.$cfg.led='$led'
set telephony.$cfg.noring='0'
set telephony.$cfg.nodial='0'
EOF
COMMIT_TELEPHONY=1
}
. /lib/lantiq.sh
board=$(lantiq_board_name)
case "$board" in
ARV7525PW)
set_relay 31 1
set_port 0 "soc:green:fxs1"
#set_port 1 "soc:green:fxs2"
;;
esac
[ "$COMMIT_TELEPHONY" == "1" ] && uci commit telephony
exit 0

33
package/owsip/files/telephony.init
View File

@ -1,33 +0,0 @@
#!/bin/sh /etc/rc.common
START=80
SERVICE_WRITE_PID=1
SERVICE_DAEMONIZE=1
SERVICE_PID_FILE=/var/run/owsip.pid
. /lib/functions.sh
relay_set () {
local cfg="$1"
local gpio value
config_get gpio "$cfg" gpio
config_get value "$cfg" value
[ -n "gpio" ] || return 0
[ ! -f "/sys/class/gpio/gpio$gpio/direction" ] &&
echo "$gpio" > /sys/class/gpio/export
[ -f "/sys/class/gpio/gpio$gpio/direction" ] && {
echo "out" > /sys/class/gpio/gpio$gpio/direction
echo "$value" > /sys/class/gpio/gpio$gpio/value
}
}
start() {
config_load telephony
config_foreach relay_set relay
service_start /usr/bin/owsip_ua
}
stop() {
service_stop /usr/bin/owsip_ua
}

101
package/pjsip/Makefile
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@ -1,101 +0,0 @@
#
# Copyright (C) 2010-2012 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=pjsip
PKG_VERSION:=1.14.2
PKG_RELEASE:=1
PKG_SOURCE:=pjproject-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=http://www.pjsip.org/release/$(PKG_VERSION)/
PKG_MD5SUM:=05428502384c16e7abd85f047e6e2f6c
PKG_INSTALL:=1
PKG_BUILD_PARALLEL:=1
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/pjproject-$(PKG_VERSION)
include $(INCLUDE_DIR)/ltqtapi.mk
PKG_BUILD_DEPENDS:=$(LTQ_TAPI_BUILD_DEPENDS)
include $(INCLUDE_DIR)/package.mk
define Package/pjsip-template
SECTION:=lib
CATEGORY:=Libraries
URL:=http://www.pjsip.org/
MAINTAINER:=John Crispin <blogic@openwrt.org>
TITLE:=pjsip-$(1)
VARIANT:=$(1)
DEPENDS:=+libuuid $(2)
endef
CONFIGURE_PREFIX=/usr/pjsip-$(BUILD_VARIANT)
ifeq ($(BUILD_VARIANT),oss)
CONFIGURE_ARGS += \
--disable-floating-point \
--enable-g711-codec \
--disable-l16-codec \
--disable-g722-codec \
--disable-g7221-codec \
--disable-gsm-codec \
--disable-ilbc-coder \
--disable-libsamplerate \
--disable-ipp \
--disable-ssl \
--enable-oss \
--enable-sound
endif
ifeq ($(BUILD_VARIANT),ltq-tapi)
CONFIGURE_ARGS += \
--disable-floating-point \
--enable-g711-codec \
--disable-l16-codec \
--disable-g722-codec \
--disable-g7221-codec \
--disable-ilbc-coder \
--disable-gsm-codec \
--disable-libsamplerate \
--disable-ipp \
--disable-ssl \
--enable-sound \
--enable-ltq-tapi
EXTRA_CFLAGS:=-I$(STAGING_DIR)/usr/include/drv_tapi -I$(STAGING_DIR)/usr/include/drv_vmmc
endif
Package/pjsip-oss=$(call Package/pjsip-template,oss,BROKEN)
Package/pjsip-ltq-tapi=$(call Package/pjsip-template,ltq-tapi,$(LTQ_TAPI_DEPENDS))
USE_LOCAL=$(shell ls ./src/ 2>/dev/null >/dev/null && echo 1)
ifneq ($(USE_LOCAL),)
define Build/Prepare
$(CP) ./src/* $(PKG_BUILD_DIR)
endef
endif
define Build/Configure
(cd $(PKG_BUILD_DIR); autoconf aconfigure.ac > aconfigure)
$(call Build/Configure/Default)
endef
define Build/Compile
+CFLAGS="$(TARGET_CFLAGS) $(EXTRA_CFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS)" \
CXXFLAGS="$(TARGET_CFLAGS) $(EXTRA_CFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS)" \
LDFLAGS="$(TARGET_LDFLAGS) -lc $(LIBGCC_S) -lm" \
$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH)
endef
define Build/InstallDev
$(INSTALL_DIR) $(1)/usr
$(CP) $(PKG_INSTALL_DIR)/usr/pjsip-$(BUILD_VARIANT) $(1)/usr
endef
$(eval $(call BuildPackage,pjsip-oss))
$(eval $(call BuildPackage,pjsip-ltq-tapi))

78
package/pjsip/patches/0001-configure-fixup.patch
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@ -1,78 +0,0 @@
Index: pjproject-1.14.2/aconfigure.ac
===================================================================
--- pjproject-1.14.2.orig/aconfigure.ac 2012-04-27 03:22:15.000000000 +0200
+++ pjproject-1.14.2/aconfigure.ac 2012-08-13 14:42:33.204641678 +0200
@@ -48,9 +48,8 @@
CROSS_COMPILE=`echo ${CC} | sed 's/gcc//'`
fi
-if test "$AR" = ""; then AR="${CROSS_COMPILE}ar rv"; fi
+AR="${AR} rv"
AC_SUBST(AR)
-if test "$LD" = ""; then LD="$CC"; fi
AC_SUBST(LD)
if test "$LDOUT" = ""; then LDOUT="-o "; fi
AC_SUBST(LDOUT)
@@ -584,13 +583,7 @@
;;
*)
dnl # Check if ALSA is available
- ac_pjmedia_snd=pa_unix
- AC_CHECK_HEADER(alsa/version.h,
- [AC_SUBST(ac_pa_use_alsa,1)
- LIBS="$LIBS -lasound"
- ],
- [AC_SUBST(ac_pa_use_alsa,0)])
- AC_MSG_RESULT([Checking sound device backend... unix])
+ AC_SUBST(ac_pa_use_alsa,0)
dnl # Check if OSS is disabled
AC_SUBST(ac_pa_use_oss,1)
@@ -617,6 +610,15 @@
fi]
)
+AC_ARG_ENABLE(ltq_tapi,
+ AC_HELP_STRING([--enable-ltq-tapi],
+ [PJMEDIA will use ltq tapi backend]),
+ [if test "$enable_ltq_tapi" = "yes"; then
+ [ac_pjmedia_snd=ltqtapi]
+ AC_MSG_RESULT([Checking if external sound is set... yes])
+ fi]
+ )
+
dnl # Include resampling small filter
AC_SUBST(ac_no_small_filter)
AC_ARG_ENABLE(small-filter,
@@ -737,14 +739,6 @@
AC_MSG_RESULT([Checking if iLBC codec is disabled...no]))
dnl # Include libsamplerate
-AC_ARG_ENABLE(libsamplerate,
- AC_HELP_STRING([--enable-libsamplerate],
- [Link with libsamplerate when available. Note that PJMEDIA_RESAMPLE_IMP must also be configured]),
- [ AC_CHECK_LIB(samplerate,src_new) ],
- AC_MSG_RESULT([Skipping libsamplerate detection])
- )
-
-dnl # Include libsamplerate
AC_SUBST(ac_resample_dll)
AC_ARG_ENABLE(resample_dll,
AC_HELP_STRING([--enable-resample-dll],
Index: pjproject-1.14.2/pjmedia/build/os-auto.mak.in
===================================================================
--- pjproject-1.14.2.orig/pjmedia/build/os-auto.mak.in 2011-10-14 06:15:15.000000000 +0200
+++ pjproject-1.14.2/pjmedia/build/os-auto.mak.in 2012-08-13 14:40:47.680637171 +0200
@@ -125,4 +125,11 @@
export CFLAGS += -DPJMEDIA_AUDIO_DEV_HAS_PORTAUDIO=0 -DPJMEDIA_AUDIO_DEV_HAS_WMME=0
endif
-
+#
+# Lantiq tapi backend
+#
+ifeq ($(AC_PJMEDIA_SND),ltqtapi)
+export CFLAGS += -DPJMEDIA_AUDIO_DEV_HAS_PORTAUDIO=0 -DPJMEDIA_AUDIO_DEV_HAS_WMME=0
+export PJMEDIA_AUDIODEV_OBJS += tapi_dev.o
+export CFLAGS += -DPJMEDIA_AUDIO_DEV_HAS_TAPI_DEVICE=1
+endif

1333
package/pjsip/patches/0002-register-tapi.patch
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File diff suppressed because it is too large Load Diff

207
package/pjsip/patches/0003-adds-PJ_DEF-pj_status_t-pjsua_add_snd_port-int-id.patch
View File

@ -1,207 +0,0 @@
--- a/pjsip/include/pjsua-lib/pjsua.h
+++ b/pjsip/include/pjsua-lib/pjsua.h
@@ -1543,6 +1543,8 @@ PJ_DECL(pjmedia_endpt*) pjsua_get_pjmedi
PJ_DECL(pj_pool_factory*) pjsua_get_pool_factory(void);
+PJ_DECL(pj_status_t) pjsua_add_snd_port(int id, pjsua_conf_port_id *p_id);
+
/*****************************************************************************
* Utilities.
--- a/pjsip/include/pjsua-lib/pjsua_internal.h
+++ b/pjsip/include/pjsua-lib/pjsua_internal.h
@@ -261,6 +261,8 @@ typedef struct pjsua_stun_resolve
} pjsua_stun_resolve;
+#define MAX_PORT 2
+
/**
* Global pjsua application data.
*/
@@ -336,7 +338,7 @@ struct pjsua_data
pj_bool_t aud_open_cnt;/**< How many # device is opened */
pj_bool_t no_snd; /**< No sound (app will manage it) */
pj_pool_t *snd_pool; /**< Sound's private pool. */
- pjmedia_snd_port *snd_port; /**< Sound port. */
+ pjmedia_snd_port *snd_port[MAX_PORT]; /**< Sound port. */
pj_timer_entry snd_idle_timer;/**< Sound device idle timer. */
pjmedia_master_port *null_snd; /**< Master port for null sound. */
pjmedia_port *null_port; /**< Null port. */
--- a/pjsip/src/pjsua-lib/pjsua_media.c
+++ b/pjsip/src/pjsua-lib/pjsua_media.c
@@ -588,7 +588,7 @@ static void check_snd_dev_idle()
* It is idle when there is no port connection in the bridge and
* there is no active call.
*/
- if ((pjsua_var.snd_port!=NULL || pjsua_var.null_snd!=NULL) &&
+ if ((pjsua_var.snd_port[0]!=NULL || pjsua_var.null_snd!=NULL) &&
pjsua_var.snd_idle_timer.id == PJ_FALSE &&
pjmedia_conf_get_connect_count(pjsua_var.mconf) == 0 &&
call_cnt == 0 &&
@@ -2008,7 +2008,7 @@ PJ_DEF(pj_status_t) pjsua_conf_connect(
pj_assert(status == PJ_SUCCESS);
/* Check if sound device is instantiated. */
- need_reopen = (pjsua_var.snd_port==NULL && pjsua_var.null_snd==NULL &&
+ need_reopen = (pjsua_var.snd_port[0]==NULL && pjsua_var.null_snd==NULL &&
!pjsua_var.no_snd);
/* Check if sound device need to reopen because it needs to modify
@@ -2072,7 +2072,7 @@ PJ_DEF(pj_status_t) pjsua_conf_connect(
/* The bridge version */
/* Create sound port if none is instantiated */
- if (pjsua_var.snd_port==NULL && pjsua_var.null_snd==NULL &&
+ if (pjsua_var.snd_port[0]==NULL && pjsua_var.null_snd==NULL &&
!pjsua_var.no_snd)
{
pj_status_t status;
@@ -2686,9 +2686,9 @@ static pj_status_t update_initial_aud_pa
pjmedia_aud_param param;
pj_status_t status;
- PJ_ASSERT_RETURN(pjsua_var.snd_port != NULL, PJ_EBUG);
+ PJ_ASSERT_RETURN(pjsua_var.snd_port[0] != NULL, PJ_EBUG);
- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
status = pjmedia_aud_stream_get_param(strm, &param);
if (status != PJ_SUCCESS) {
@@ -2754,7 +2754,7 @@ static pj_status_t open_snd_dev(pjmedia_
1000 / param->base.clock_rate));
status = pjmedia_snd_port_create2( pjsua_var.snd_pool,
- param, &pjsua_var.snd_port);
+ param, &pjsua_var.snd_port[0]);
if (status != PJ_SUCCESS)
return status;
@@ -2812,13 +2812,13 @@ static pj_status_t open_snd_dev(pjmedia_
}
/* Connect sound port to the bridge */
- status = pjmedia_snd_port_connect(pjsua_var.snd_port,
+ status = pjmedia_snd_port_connect(pjsua_var.snd_port[0],
conf_port );
if (status != PJ_SUCCESS) {
pjsua_perror(THIS_FILE, "Unable to connect conference port to "
"sound device", status);
- pjmedia_snd_port_destroy(pjsua_var.snd_port);
- pjsua_var.snd_port = NULL;
+ pjmedia_snd_port_destroy(pjsua_var.snd_port[0]);
+ pjsua_var.snd_port[0] = NULL;
return status;
}
@@ -2833,7 +2833,7 @@ static pj_status_t open_snd_dev(pjmedia_
pjmedia_aud_param si;
pj_str_t tmp;
- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
status = pjmedia_aud_stream_get_param(strm, &si);
if (status == PJ_SUCCESS)
status = pjmedia_aud_dev_get_info(si.rec_id, &rec_info);
@@ -2876,12 +2876,12 @@ static pj_status_t open_snd_dev(pjmedia_
static void close_snd_dev(void)
{
/* Close sound device */
- if (pjsua_var.snd_port) {
+ if (pjsua_var.snd_port[0]) {
pjmedia_aud_dev_info cap_info, play_info;
pjmedia_aud_stream *strm;
pjmedia_aud_param param;
- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
pjmedia_aud_stream_get_param(strm, &param);
if (pjmedia_aud_dev_get_info(param.rec_id, &cap_info) != PJ_SUCCESS)
@@ -2893,9 +2893,9 @@ static void close_snd_dev(void)
"%s sound capture device",
play_info.name, cap_info.name));
- pjmedia_snd_port_disconnect(pjsua_var.snd_port);
- pjmedia_snd_port_destroy(pjsua_var.snd_port);
- pjsua_var.snd_port = NULL;
+ pjmedia_snd_port_disconnect(pjsua_var.snd_port[0]);
+ pjmedia_snd_port_destroy(pjsua_var.snd_port[0]);
+ pjsua_var.snd_port[0] = NULL;
}
/* Close null sound device */
@@ -2984,6 +2984,35 @@ PJ_DEF(pj_status_t) pjsua_set_snd_dev( i
return PJ_SUCCESS;
}
+PJ_DEF(pj_status_t) pjsua_add_snd_port(int id, pjsua_conf_port_id *p_id)
+{
+ unsigned alt_cr_cnt = 1;
+ unsigned alt_cr = 0;
+ pj_status_t status = -1;
+ pjmedia_snd_port_param param;
+ unsigned samples_per_frame;
+ pjmedia_port *port;
+ const pj_str_t name = pj_str("tapi2");
+ alt_cr = pjsua_var.media_cfg.clock_rate;
+ samples_per_frame = alt_cr *
+ pjsua_var.media_cfg.audio_frame_ptime *
+ pjsua_var.media_cfg.channel_count / 1000;
+ status = create_aud_param(&param.base,
+ pjsua_var.play_dev,
+ pjsua_var.cap_dev,
+ alt_cr,
+ pjsua_var.media_cfg.channel_count,
+ samples_per_frame, 16);
+ if (status != PJ_SUCCESS)
+ return status;
+ param.base.rec_id = id;
+ param.base.play_id = id;
+ param.options = 0;
+ status = pjmedia_snd_port_create2(pjsua_var.snd_pool,
+ &param, &pjsua_var.snd_port[id]);
+ return PJ_SUCCESS;
+}
+
/*
* Get currently active sound devices. If sound devices has not been created
@@ -3088,7 +3117,7 @@ PJ_DEF(pj_status_t) pjsua_set_ec(unsigne
pjsua_var.media_cfg.ec_options = options;
if (pjsua_var.snd_port)
- status = pjmedia_snd_port_set_ec(pjsua_var.snd_port, pjsua_var.pool,
+ status = pjmedia_snd_port_set_ec(pjsua_var.snd_port[0], pjsua_var.pool,
tail_ms, options);
PJSUA_UNLOCK();
@@ -3111,7 +3140,7 @@ PJ_DEF(pj_status_t) pjsua_get_ec_tail(un
*/
PJ_DEF(pj_bool_t) pjsua_snd_is_active(void)
{
- return pjsua_var.snd_port != NULL;
+ return pjsua_var.snd_port[0] != NULL;
}
@@ -3135,7 +3164,7 @@ PJ_DEF(pj_status_t) pjsua_snd_set_settin
if (pjsua_snd_is_active()) {
pjmedia_aud_stream *strm;
- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
status = pjmedia_aud_stream_set_cap(strm, cap, pval);
} else {
status = PJ_SUCCESS;
@@ -3181,7 +3210,7 @@ PJ_DEF(pj_status_t) pjsua_snd_get_settin
/* Sound is active, retrieve from device directly */
pjmedia_aud_stream *strm;
- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
status = pjmedia_aud_stream_get_cap(strm, cap, pval);
} else {
/* Otherwise retrieve from internal param */

190
package/uboot-lantiq/Makefile
View File

@ -1,190 +0,0 @@
#
# Copyright (C) 2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=u-boot
PKG_VERSION:=2010.03
PKG_MD5SUM:=2bf5ebf497dddc52440b1ea386cc1332
PKG_RELEASE:=1
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
PKG_TARGETS:=bin
include $(INCLUDE_DIR)/package.mk
ifeq ($(DUMP),)
STAMP_CONFIGURED:=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/.configured
STAMP_BUILT:=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/.built
endif
define Package/uboot-lantiq-template
SECTION:=boot
CATEGORY:=Boot Loaders
DEPENDS:=@TARGET_lantiq_danube
URL:=http://www.denx.de/wiki/U-Boot
VARIANT:=$(1)
TITLE:=$(1) ($(2))
MAINTAINER:=John Crispin <blogic@openwrt.org>
endef
#Lantiq
Package/uboot-lantiq-easy50712_DDR166M_flash=$(call Package/uboot-lantiq-template,easy50712_DDR166M_flash,NOR)
Package/uboot-lantiq-easy50712_DDR166M_ramboot=$(call Package/uboot-lantiq-template,easy50712_DDR166M_ramboot,RAM)
Package/uboot-lantiq-easy50812_DDR166M_flash=$(call Package/uboot-lantiq-template,easy50812_DDR166M_flash,NOR)
Package/uboot-lantiq-easy50812_DDR166M_ramboot=$(call Package/uboot-lantiq-template,easy50812_DDR166M_ramboot,RAM)
DDR_CONFIG_easy50712_DDR166M_ramboot:=easy50712_DDR166M
DDR_CONFIG_easy50812_DDR166M_ramboot:=easy50812
#Siemens
Package/uboot-lantiq-gigaSX76X_DDRsamsung166_flash=$(call Package/uboot-lantiq-template,gigaSX76X_DDRsamsung166_flash,NOR)
Package/uboot-lantiq-gigaSX76X_DDRsamsung166_ramboot=$(call Package/uboot-lantiq-template,gigaSX76X_DDRsamsung166_ramboot,RAM)
DDR_CONFIG_gigaSX76X_DDRsamsung166_ramboot:=easy50712_DDR166M
#Arcadyan
Package/uboot-lantiq-arv3527P_flash=$(call Package/uboot-lantiq-template,arv3527P_flash,NOR)
Package/uboot-lantiq-arv3527P_ramboot=$(call Package/uboot-lantiq-template,arv3527P_ramboot,RAM)
Package/uboot-lantiq-arv3527P_brnboot=$(call Package/uboot-lantiq-template,arv3527P_brnboot,BRN)
Package/uboot-lantiq-arv4518PW_flash=$(call Package/uboot-lantiq-template,arv4518PW_flash,NOR)
Package/uboot-lantiq-arv4518PW_ramboot=$(call Package/uboot-lantiq-template,arv4518PW_ramboot,RAM)
Package/uboot-lantiq-arv4518PW_brnboot=$(call Package/uboot-lantiq-template,arv4518PW_brnboot,BRN)
Package/uboot-lantiq-arv4519PW_flash=$(call Package/uboot-lantiq-template,arv4519PW_flash,NOR)
Package/uboot-lantiq-arv4519PW_ramboot=$(call Package/uboot-lantiq-template,arv4519PW_ramboot,RAM)
Package/uboot-lantiq-arv4519PW_brnboot=$(call Package/uboot-lantiq-template,arv4519PW_brnboot,BRN)
Package/uboot-lantiq-arv4520PW_flash=$(call Package/uboot-lantiq-template,arv4520PW_flash,NOR)
Package/uboot-lantiq-arv4520PW_ramboot=$(call Package/uboot-lantiq-template,arv4520PW_ramboot,RAM)
Package/uboot-lantiq-arv4520PW_brnboot=$(call Package/uboot-lantiq-template,arv4520PW_brnboot,BRN)
Package/uboot-lantiq-arv4525PW_flash=$(call Package/uboot-lantiq-template,arv4525PW_flash,NOR)
Package/uboot-lantiq-arv4525PW_ramboot=$(call Package/uboot-lantiq-template,arv4525PW_ramboot,RAM)
Package/uboot-lantiq-arv4525PW_brnboot=$(call Package/uboot-lantiq-template,arv4525PW_brnboot,BRN)
Package/uboot-lantiq-arv7525PW_flash=$(call Package/uboot-lantiq-template,arv7525PW_flash,NOR)
Package/uboot-lantiq-arv7525PW_ramboot=$(call Package/uboot-lantiq-template,arv7525PW_ramboot,RAM)
Package/uboot-lantiq-arv7525PW_brnboot=$(call Package/uboot-lantiq-template,arv7525PW_brnboot,BRN)
Package/uboot-lantiq-arv452CPW_flash=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
Package/uboot-lantiq-arv452CPW_ramboot=$(call Package/uboot-lantiq-template,arv452CPW_ramboot,RAM)
Package/uboot-lantiq-arv452CPW_brnboot=$(call Package/uboot-lantiq-template,arv452CPW_brnboot,BRN)
Package/uboot-lantiq-arv752DPW_flash=$(call Package/uboot-lantiq-template,arv752DPW_flash,NOR)
Package/uboot-lantiq-arv752DPW_ramboot=$(call Package/uboot-lantiq-template,arv752DPW_ramboot,RAM)
Package/uboot-lantiq-arv752DPW_brnboot=$(call Package/uboot-lantiq-template,arv752DPW_brnboot,BRN)
Package/uboot-lantiq-arv752DPW22_flash=$(call Package/uboot-lantiq-template,arv752DPW22_flash,NOR)
Package/uboot-lantiq-arv752DPW22_ramboot=$(call Package/uboot-lantiq-template,arv752DPW22_ramboot,RAM)
Package/uboot-lantiq-arv752DPW22_brnboot=$(call Package/uboot-lantiq-template,arv752DPW22_brnboot,BRN)
Package/uboot-lantiq-arv7518PW_flash=$(call Package/uboot-lantiq-template,arv7518PW_flash,NOR)
Package/uboot-lantiq-arv7518PW_ramboot=$(call Package/uboot-lantiq-template,arv7518PW_ramboot,RAM)
Package/uboot-lantiq-arv7518PW_brnboot=$(call Package/uboot-lantiq-template,arv7518PW_brnboot,BRN)
DDR_CONFIG_arv3527P_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv4518PW_ramboot:=arcadyan_psc166_64
DDR_CONFIG_arv4519PW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv4520PW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv4525PW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv7525PW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv452CPW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166_64
DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166_64
DDR_CONFIG_arv7518PW_ramboot:=arcadyan_psc166_64
define Build/Prepare
$(PKG_UNPACK)
cp -r $(CP_OPTS) $(FILES_DIR)/* $(PKG_BUILD_DIR)/
$(Build/Patch)
find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
endef
UBOOT_MAKE_OPTS:= \
CROSS_COMPILE=$(TARGET_CROSS) \
ENDIANNESS= \
V=1
define Build/Configure/Target
$(MAKE) -s -C $(PKG_BUILD_DIR) \
$(UBOOT_MAKE_OPTS) \
O=$(PKG_BUILD_DIR)/$(BUILD_VARIANT) \
$(1)_config
endef
define Build/Configure
$(call Build/Configure/Target,$(BUILD_VARIANT))
endef
define Build/Compile/Target
$(MAKE) -s -C $(PKG_BUILD_DIR) \
$(UBOOT_MAKE_OPTS) \
O=$(PKG_BUILD_DIR)/$(1) \
all
endef
define Build/Compile
$(call Build/Compile/Target,$(BUILD_VARIANT))
endef
define Package/uboot-lantiq-$(BUILD_VARIANT)/install
mkdir -p $(1)
ifneq ($(findstring flash,$(BUILD_VARIANT)),)
dd \
if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot-bootstrap.bin \
of=$(1)/u-boot-bootstrap.bin \
bs=64k conv=sync
else
dd \
if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.bin \
of=$(1)/u-boot.bin \
bs=64k conv=sync
endif
ifneq ($(findstring ramboot,$(BUILD_VARIANT)),)
if [ -e $(DDR_CONFIG_$(BUILD_VARIANT)).conf ]; then \
perl ./gct \
$(DDR_CONFIG_$(BUILD_VARIANT)).conf \
$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.srec \
$(1)/u-boot.asc; \
fi
endif
endef
$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_flash))
$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_flash))
$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-gigaSX76X_DDRsamsung166_flash))
$(eval $(call BuildPackage,uboot-lantiq-gigaSX76X_DDRsamsung166_ramboot))
#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_flash))
#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_brnboot))
#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_ramboot))

71
package/uboot-lantiq/arcadyan_psc166_32.conf
View File

@ -1,71 +0,0 @@
0xbf800060 0x7
0xbf800010 0x0
0xbf800020 0x0
0xbf800200 0x02
0xbf800210 0x0
0xbf801000 0x1b1b
0xbf801010 0x0
0xbf801020 0x0
0xbf801030 0x0
0xbf801040 0x0
0xbf801050 0x200
0xbf801060 0x605
0xbf801070 0x0303
0xbf801080 0x102
0xbf801090 0x70a
0xbf8010a0 0x203
0xbf8010b0 0xc02
0xbf8010c0 0x1c8
0xbf8010d0 0x1
0xbf8010e0 0x0
0xbf8010f0 0x120
0xbf801100 0xc800
0xbf801110 0xd
0xbf801120 0x301
0xbf801130 0x200
0xbf801140 0xa04
0xbf801150 0x1700
0xbf801160 0x1717
0xbf801170 0x0
0xbf801180 0x52
0xbf801190 0x0
0xbf8011a0 0x0
0xbf8011b0 0x0
0xbf8011c0 0x510
0xbf8011d0 0x4e20
0xbf8011e0 0x8235
0xbf8011f0 0x0
0xbf801200 0x0
0xbf801210 0x0
0xbf801220 0x0
0xbf801230 0x0
0xbf801240 0x0
0xbf801250 0x0
0xbf801260 0x0
0xbf801270 0x0
0xbf801280 0x0
0xbf801290 0x0
0xbf8012a0 0x0
0xbf8012b0 0x0
0xbf8012c0 0x0
0xbf8012d0 0x500
0xbf8012e0 0x0
0xbf800060 0x05
0xbf801030 0x100

141
package/uboot-lantiq/arcadyan_psc166_64.conf
View File

@ -1,141 +0,0 @@
0xbf800060 0x7
0xbf800010 0x0
0xbf800020 0x0
0xbf800200 0x02
0xbf800210 0x0
;REG32(MC_DC0) = 0x00001B1B;
0xbf801000 0x1b1b
;REG32(MC_DC1) = 0x00000000;
0xbf801010 0x0
;REG32(MC_DC2) = 0x00000000;
0xbf801020 0x0
;REG32(MC_DC3) = 0x00000000;
0xbf801030 0x0
;REG32(MC_DC4) = 0x00000000;
0xbf801040 0x0
;REG32(MC_DC5) = 0x00000200;
0xbf801050 0x200
;REG32(MC_DC6) = 0x00000306;
; 0xbf801060 0x0306
0xbf801060 0x0605
;REG32(MC_DC7) = 0x00000303;
; 0xbf801070 0x302
; 0xbf801070 0x0203
0xbf801070 0x0303
;REG32(MC_DC8) = 0x00000102;
0xbf801080 0x102
;REG32(MC_DC9) = 0x0000070A;
0xbf801090 0x70a
; 0xbf801090 0x608
;REG32(MC_DC10) = 0x00000203;
0xbf8010a0 0x203
;REG32(MC_DC11) = 0x00000C02;
0xbf8010b0 0xc02
; 0xbf8010b0 0x0a02
;REG32(MC_DC12) = 0x000001C8;
0xbf8010c0 0x1c8
;REG32(MC_DC13) = 0x00000001;
0xbf8010d0 0x1
;REG32(MC_DC14) = 0x00000000;
0xbf8010e0 0x0
;REG32(MC_DC15) = 0x00000F5F;
; 0xbf8010f0 0xf5f
; 0xbf8010f0 0xf3c
0xbf8010f0 0x130
;REG32(MC_DC16) = 0x0000C800;
0xbf801100 0xc800
;REG32(MC_DC17) = 0x0000000D;
; 0xbf801110 0xd
0xbf801110 0xd
;REG32(MC_DC18) = 0x00000300;
; 0xbf801120 0x300
0xbf801120 0x301
;REG32(MC_DC19) = 0x00000300;
; 0xbf801130 0x300
0xbf801130 0x200
;REG32(MC_DC20) = 0x00000A04;
; 0xbf801140 0xa04
0xbf801140 0xa03
;REG32(MC_DC21) = 0x00001c00;
; 0xbf801150 0xd00
; 0xbf801150 0x1f00
0xbf801150 0x1b00
;REG32(MC_DC22) = 0x00001E1E;
; 0xbf801160 0xd0d
; 0xbf801160 0x1f1f
0xbf801160 0x1b1b
;REG32(MC_DC23) = 0x00000000;
0xbf801170 0x0
;//Disable ECC
;REG32(MC_DC24) = 0x0000007F;
; 0xbf801180 0x7f
; 0xbf801180 0x062
; 0xbf801180 0x37f
0xbf801180 0x59
;REG32(MC_DC25) = 0x00000000;
0xbf801190 0x0
;REG32(MC_DC26) = 0x00000000;
0xbf8011a0 0x0
;REG32(MC_DC27) = 0x00000000;
0xbf8011b0 0x0
;REG32(MC_DC28) = 0x00000A24;
; 0xbf8011c0 0xa24
0xbf8011c0 0x510
;REG32(MC_DC29) = 0x00002D89;
; 0xbf8011d0 0x2d89
; 0xbf8011d0 0x2d92
0xbf8011d0 0x4e20
;REG32(MC_DC30) = 0x00000022;
; 0xbf8011e0 0x8300
0xbf8011e0 0x8235
;REG32(MC_DC31) = 0x00000000;
0xbf8011f0 0x0
;REG32(MC_DC32) = 0x00000000;
0xbf801200 0x0
;REG32(MC_DC33) = 0x00000000;
0xbf801210 0x0
;REG32(MC_DC34) = 0x00000000;
0xbf801220 0x0
;REG32(MC_DC35) = 0x00000000;
0xbf801230 0x0
;REG32(MC_DC36) = 0x00000000;
0xbf801240 0x0
;REG32(MC_DC37) = 0x00000000;
0xbf801250 0x0
;REG32(MC_DC38) = 0x00000000;
0xbf801260 0x0
;REG32(MC_DC39) = 0x00000000;
0xbf801270 0x0
;REG32(MC_DC40) = 0x00000000;
0xbf801280 0x0
;REG32(MC_DC41) = 0x00000000;
0xbf801290 0x0
;REG32(MC_DC42) = 0x00000000;
0xbf8012a0 0x0
;REG32(MC_DC43) = 0x00000000;
0xbf8012b0 0x0
;REG32(MC_DC44) = 0x00000000;
0xbf8012c0 0x0
;REG32(MC_DC45) = 0x00000600;
0xbf8012d0 0x500
;REG32(MC_DC46) = 0x00000000;
0xbf8012e0 0x0
0xbf800060 0x05
0xbf801030 0x100

134
package/uboot-lantiq/easy50712_DDR166M.conf
View File

@ -1,134 +0,0 @@
0xbf800060 0x7
0xbf800010 0x0
0xbf800020 0x0
0xbf800200 0x02
0xbf800210 0x0
;REG32(MC_DC0) = 0x00001B1B;
0xbf801000 0x1b1b
;REG32(MC_DC1) = 0x00000000;
0xbf801010 0x0
;REG32(MC_DC2) = 0x00000000;
0xbf801020 0x0
;REG32(MC_DC3) = 0x00000000;
0xbf801030 0x0
;REG32(MC_DC4) = 0x00000000;
0xbf801040 0x0
;REG32(MC_DC5) = 0x00000200;
0xbf801050 0x200
;REG32(MC_DC6) = 0x00000306;
; 0xbf801060 0x0306
0xbf801060 0x0605
;REG32(MC_DC7) = 0x00000303;
0xbf801070 0x302
; 0xbf801070 0x0203
;REG32(MC_DC8) = 0x00000102;
0xbf801080 0x102
;REG32(MC_DC9) = 0x0000070A;
0xbf801090 0x70a
; 0xbf801090 0x608
;REG32(MC_DC10) = 0x00000203;
0xbf8010a0 0x203
;REG32(MC_DC11) = 0x00000C02;
0xbf8010b0 0xc02
; 0xbf8010b0 0x0a02
;REG32(MC_DC12) = 0x000001C8;
0xbf8010c0 0x1c8
;REG32(MC_DC13) = 0x00000001;
0xbf8010d0 0x1
;REG32(MC_DC14) = 0x00000000;
0xbf8010e0 0x0
;REG32(MC_DC15) = 0x00000F5F;
; 0xbf8010f0 0xf5f
0xbf8010f0 0xf3c
;REG32(MC_DC16) = 0x0000C800;
0xbf801100 0xc800
;REG32(MC_DC17) = 0x0000000D;
; 0xbf801110 0xd
0xbf801110 0xd
;REG32(MC_DC18) = 0x00000300;
0xbf801120 0x300
;REG32(MC_DC19) = 0x00000300;
; 0xbf801130 0x300
0xbf801130 0x200
;REG32(MC_DC20) = 0x00000A04;
; 0xbf801140 0xa04
0xbf801140 0xa04
;REG32(MC_DC21) = 0x00001c00;
0xbf801150 0xd00
; 0xbf801150 0x1f00
;REG32(MC_DC22) = 0x00001E1E;
0xbf801160 0xd0d
; 0xbf801160 0x1f1f
;REG32(MC_DC23) = 0x00000000;
0xbf801170 0x0
;//Disable ECC
;REG32(MC_DC24) = 0x0000007F;
; 0xbf801180 0x7f
0xbf801180 0x062
; 0xbf801180 0x37f
;REG32(MC_DC25) = 0x00000000;
0xbf801190 0x0
;REG32(MC_DC26) = 0x00000000;
0xbf8011a0 0x0
;REG32(MC_DC27) = 0x00000000;
0xbf8011b0 0x0
;REG32(MC_DC28) = 0x00000A24;
; 0xbf8011c0 0xa24
0xbf8011c0 0x510
;REG32(MC_DC29) = 0x00002D89;
0xbf8011d0 0x2d89
; 0xbf8011d0 0x2d92
;REG32(MC_DC30) = 0x00000022;
0xbf8011e0 0x8300
; 0xbf8011e0 0x8235
;REG32(MC_DC31) = 0x00000000;
0xbf8011f0 0x0
;REG32(MC_DC32) = 0x00000000;
0xbf801200 0x0
;REG32(MC_DC33) = 0x00000000;
0xbf801210 0x0
;REG32(MC_DC34) = 0x00000000;
0xbf801220 0x0
;REG32(MC_DC35) = 0x00000000;
0xbf801230 0x0
;REG32(MC_DC36) = 0x00000000;
0xbf801240 0x0
;REG32(MC_DC37) = 0x00000000;
0xbf801250 0x0
;REG32(MC_DC38) = 0x00000000;
0xbf801260 0x0
;REG32(MC_DC39) = 0x00000000;
0xbf801270 0x0
;REG32(MC_DC40) = 0x00000000;
0xbf801280 0x0
;REG32(MC_DC41) = 0x00000000;
0xbf801290 0x0
;REG32(MC_DC42) = 0x00000000;
0xbf8012a0 0x0
;REG32(MC_DC43) = 0x00000000;
0xbf8012b0 0x0
;REG32(MC_DC44) = 0x00000000;
0xbf8012c0 0x0
;REG32(MC_DC45) = 0x00000600;
0xbf8012d0 0x500
;REG32(MC_DC46) = 0x00000000;
0xbf8012e0 0x0
0xbf800060 0x05
0xbf801030 0x100

55
package/uboot-lantiq/easy50812.conf
View File

@ -1,55 +0,0 @@
0xbf800060 0x0000000f
0xbf800010 0x00000000
0xbf800020 0x00000000
0xbf800200 0x00000002
0xbf800210 0x00000000
0xbf801000 0x00001b1b
0xbf801010 0x00000000
0xbf801020 0x00000000
0xbf801030 0x00000000
0xbf801040 0x00000000
0xbf801050 0x00000200
0xbf801060 0x00000306
0xbf801070 0x00000303
0xbf801080 0x00000102
0xbf801090 0x0000070a
0xbf8010a0 0x00000203
0xbf8010b0 0x00000c02
0xbf8010c0 0x000001c8
0xbf8010d0 0x00000001
0xbf8010e0 0x00000000
0xbf8010f0 0x00000139
0xbf801100 0x00002200
0xbf801110 0x0000000d
0xbf801120 0x00000301
0xbf801130 0x00000200
0xbf801140 0x00000a04
0xbf801150 0x00001800
0xbf801160 0x00001818
0xbf801170 0x00000000
0xbf801180 0x00000059
0xbf801190 0x00000000
0xbf8011a0 0x00000000
0xbf8011b0 0x00000000
0xbf8011c0 0x00000514
0xbf8011d0 0x00002d93
0xbf8011e0 0x00008235
0xbf8011f0 0x00000000
0xbf801200 0x00000000
0xbf801210 0x00000000
0xbf801220 0x00000000
0xbf801230 0x00000000
0xbf801240 0x00000000
0xbf801250 0x00000000
0xbf801260 0x00000000
0xbf801270 0x00000000
0xbf801280 0x00000000
0xbf801290 0x00000000
0xbf8012a0 0x00000000
0xbf8012b0 0x00000000
0xbf8012c0 0x00000000
0xbf8012d0 0x00000600
0xbf8012e0 0x00000000
0xbf800060 0x0000000d
0xbf801030 0x00000100

62
package/uboot-lantiq/files/board/arcadyan/Makefile
View File

@ -1,62 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
COBJS-y += board.o athrs26_phy.o
SOBJS = lowlevel_init.o pmuenable.o
BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

48
package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c
View File

@ -1,48 +0,0 @@
/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2007
* Vlad Lungu vlad.lungu@windriver.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
phys_size_t bootstrap_initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return CONFIG_SYS_MAX_RAM;
}
int bootstrap_checkboard(void)
{
return 0;
}
int bootstrap_misc_init_r(void)
{
set_io_port_base(0);
return 0;
}

812
package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c
View File

@ -1,812 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright © 2003 Atheros Communications, Inc., All Rights Reserved.
*/
/*
* Manage the atheros ethernet PHY.
*
* All definitions in this file are operating system independent!
*/
#include <config.h>
#include <linux/types.h>
#include <common.h>
#include <miiphy.h>
//#include "phy.h"
//#include "ar7100_soc.h"
#include "athrs26_phy.h"
#define phy_reg_read(base, addr, reg, datap) \
miiphy_read("lq_cpe_eth", addr, reg, datap);
#define phy_reg_write(base, addr, reg, data) \
miiphy_write("lq_cpe_eth", addr, reg, data);
/* PHY selections and access functions */
typedef enum {
PHY_SRCPORT_INFO,
PHY_PORTINFO_SIZE,
} PHY_CAP_TYPE;
typedef enum {
PHY_SRCPORT_NONE,
PHY_SRCPORT_VLANTAG,
PHY_SRCPORT_TRAILER,
} PHY_SRCPORT_TYPE;
#ifdef DEBUG
#define DRV_DEBUG 1
#endif
//#define DRV_DEBUG 1
#define DRV_DEBUG_PHYERROR 0x00000001
#define DRV_DEBUG_PHYCHANGE 0x00000002
#define DRV_DEBUG_PHYSETUP 0x00000004
#if DRV_DEBUG
int athrPhyDebug = DRV_DEBUG_PHYERROR|DRV_DEBUG_PHYCHANGE|DRV_DEBUG_PHYSETUP;
#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6) \
{ \
if (athrPhyDebug & (FLG)) { \
logMsg(X0, X1, X2, X3, X4, X5, X6); \
} \
}
#define DRV_MSG(x,a,b,c,d,e,f) \
logMsg(x,a,b,c,d,e,f)
#define DRV_PRINT(FLG, X) \
{ \
if (athrPhyDebug & (FLG)) { \
printf X; \
} \
}
#else /* !DRV_DEBUG */
#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
#define DRV_MSG(x,a,b,c,d,e,f)
#define DRV_PRINT(DBG_SW,X)
#endif
#define ATHR_LAN_PORT_VLAN 1
#define ATHR_WAN_PORT_VLAN 2
#define ENET_UNIT_LAN 0
#define TRUE 1
#define FALSE 0
#define ATHR_PHY0_ADDR 0x0
#define ATHR_PHY1_ADDR 0x1
#define ATHR_PHY2_ADDR 0x2
#define ATHR_PHY3_ADDR 0x3
#define ATHR_PHY4_ADDR 0x4
/*
* Track per-PHY port information.
*/
typedef struct {
BOOL isEnetPort; /* normal enet port */
BOOL isPhyAlive; /* last known state of link */
int ethUnit; /* MAC associated with this phy port */
uint32_t phyBase;
uint32_t phyAddr; /* PHY registers associated with this phy port */
uint32_t VLANTableSetting; /* Value to be written to VLAN table */
} athrPhyInfo_t;
/*
* Per-PHY information, indexed by PHY unit number.
*/
static athrPhyInfo_t athrPhyInfo[] = {
{TRUE, /* phy port 0 -- LAN port 0 */
FALSE,
ENET_UNIT_LAN,
0,
ATHR_PHY0_ADDR,
ATHR_LAN_PORT_VLAN
},
{TRUE, /* phy port 1 -- LAN port 1 */
FALSE,
ENET_UNIT_LAN,
0,
ATHR_PHY1_ADDR,
ATHR_LAN_PORT_VLAN
},
{TRUE, /* phy port 2 -- LAN port 2 */
FALSE,
ENET_UNIT_LAN,
0,
ATHR_PHY2_ADDR,
ATHR_LAN_PORT_VLAN
},
{TRUE, /* phy port 3 -- LAN port 3 */
FALSE,
ENET_UNIT_LAN,
0,
ATHR_PHY3_ADDR,
ATHR_LAN_PORT_VLAN
},
{TRUE, /* phy port 4 -- WAN port or LAN port 4 */
FALSE,
1,
0,
ATHR_PHY4_ADDR,
ATHR_LAN_PORT_VLAN /* Send to all ports */
},
{FALSE, /* phy port 5 -- CPU port (no RJ45 connector) */
TRUE,
ENET_UNIT_LAN,
0,
0x00,
ATHR_LAN_PORT_VLAN /* Send to all ports */
},
};
#ifdef CFG_ATHRHDR_EN
typedef struct {
uint8_t data[ATHRHDR_MAX_DATA];
uint8_t len;
uint32_t seq;
} cmd_resp_t;
typedef struct {
uint16_t reg_addr;
uint16_t cmd_len;
uint8_t *reg_data;
}cmd_write_t;
static cmd_write_t cmd_write,cmd_read;
static cmd_resp_t cmd_resp;
static struct eth_device *lan_mac;
//static atomic_t seqcnt = ATOMIC_INIT(0);
static int seqcnt = 0;
static int cmd = 1;
//volatile uchar AthrHdrPkt[60];
#endif
#define ATHR_GLOBALREGBASE 0
//#define ATHR_PHY_MAX (sizeof(athrPhyInfo) / sizeof(athrPhyInfo[0]))
#define ATHR_PHY_MAX 5
/* Range of valid PHY IDs is [MIN..MAX] */
#define ATHR_ID_MIN 0
#define ATHR_ID_MAX (ATHR_PHY_MAX-1)
/* Convenience macros to access myPhyInfo */
#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort)
#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive)
#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit)
#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase)
#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr)
#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting)
#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \
(ATHR_IS_ENET_PORT(phyUnit) && \
ATHR_ETHUNIT(phyUnit) == (ethUnit))
#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN))
/* Forward references */
BOOL athrs26_phy_is_link_alive(int phyUnit);
//static uint32_t athrs26_reg_read(uint16_t reg_addr);
static void athrs26_reg_write(uint16_t reg_addr,
uint32_t reg_val);
/******************************************************************************
*
* athrs26_phy_is_link_alive - test to see if the specified link is alive
*
* RETURNS:
* TRUE --> link is alive
* FALSE --> link is down
*/
void athrs26_reg_init(void)
{
athrs26_reg_write(0x200, 0x200);
athrs26_reg_write(0x300, 0x200);
athrs26_reg_write(0x400, 0x200);
athrs26_reg_write(0x500, 0x200);
athrs26_reg_write(0x600, 0x7d);
#ifdef S26_VER_1_0
phy_reg_write(0, 0, 29, 41);
phy_reg_write(0, 0, 30, 0);
phy_reg_write(0, 1, 29, 41);
phy_reg_write(0, 1, 30, 0);
phy_reg_write(0, 2, 29, 41);
phy_reg_write(0, 2, 30, 0);
phy_reg_write(0, 3, 29, 41);
phy_reg_write(0, 3, 30, 0);
phy_reg_write(0, 4, 29, 41);
phy_reg_write(0, 4, 30, 0);
#endif
athrs26_reg_write(0x38, 0xc000050e);
#ifdef CFG_ATHRHDR_EN
athrs26_reg_write(0x104, 0x4804);
#else
athrs26_reg_write(0x104, 0x4004);
#endif
athrs26_reg_write(0x60, 0xffffffff);
athrs26_reg_write(0x64, 0xaaaaaaaa);
athrs26_reg_write(0x68, 0x55555555);
athrs26_reg_write(0x6c, 0x0);
athrs26_reg_write(0x70, 0x41af);
}
BOOL
athrs26_phy_is_link_alive(int phyUnit)
{
uint16_t phyHwStatus;
uint32_t phyBase;
uint32_t phyAddr;
phyBase = ATHR_PHYBASE(phyUnit);
phyAddr = ATHR_PHYADDR(phyUnit);
phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
if (phyHwStatus & ATHR_STATUS_LINK_PASS)
return TRUE;
return FALSE;
}
/******************************************************************************
*
* athrs26_phy_setup - reset and setup the PHY associated with
* the specified MAC unit number.
*
* Resets the associated PHY port.
*
* RETURNS:
* TRUE --> associated PHY is alive
* FALSE --> no LINKs on this ethernet unit
*/
BOOL
athrs26_phy_setup(int ethUnit)
{
int phyUnit;
uint16_t phyHwStatus;
uint16_t timeout;
int liveLinks = 0;
uint32_t phyBase = 0;
BOOL foundPhy = FALSE;
uint32_t phyAddr = 0;
uint32_t regVal;
/* See if there's any configuration data for this enet */
/* start auto negogiation on each phy */
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
continue;
}
foundPhy = TRUE;
phyBase = ATHR_PHYBASE(phyUnit);
phyAddr = ATHR_PHYADDR(phyUnit);
phy_reg_write(phyBase, phyAddr, ATHR_AUTONEG_ADVERT,
ATHR_ADVERTISE_ALL);
/* Reset PHYs*/
phy_reg_write(phyBase, phyAddr, ATHR_PHY_CONTROL,
ATHR_CTRL_AUTONEGOTIATION_ENABLE
| ATHR_CTRL_SOFTWARE_RESET);
}
if (!foundPhy) {
return FALSE; /* No PHY's configured for this ethUnit */
}
/*
* After the phy is reset, it takes a little while before
* it can respond properly.
*/
sysMsDelay(1000);
/*
* Wait up to .75 seconds for ALL associated PHYs to finish
* autonegotiation. The only way we get out of here sooner is
* if ALL PHYs are connected AND finish autonegotiation.
*/
for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) {
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
continue;
}
timeout=20;
for (;;) {
phyHwStatus = 0;
phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL, &phyHwStatus);
if (ATHR_RESET_DONE(phyHwStatus)) {
DRV_PRINT(DRV_DEBUG_PHYSETUP,
("Port %d, Neg Success\n", phyUnit));
break;
}
if (timeout == 0) {
DRV_PRINT(DRV_DEBUG_PHYSETUP,
("Port %d, Negogiation timeout\n", phyUnit));
break;
}
if (--timeout == 0) {
DRV_PRINT(DRV_DEBUG_PHYSETUP,
("Port %d, Negogiation timeout\n", phyUnit));
break;
}
sysMsDelay(150);
}
}
/*
* All PHYs have had adequate time to autonegotiate.
* Now initialize software status.
*
* It's possible that some ports may take a bit longer
* to autonegotiate; but we can't wait forever. They'll
* get noticed by mv_phyCheckStatusChange during regular
* polling activities.
*/
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
continue;
}
if (athrs26_phy_is_link_alive(phyUnit)) {
liveLinks++;
ATHR_IS_PHY_ALIVE(phyUnit) = TRUE;
} else {
ATHR_IS_PHY_ALIVE(phyUnit) = FALSE;
}
phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit),
ATHR_PHY_SPEC_STATUS, &regVal);
DRV_PRINT(DRV_DEBUG_PHYSETUP,
("eth%d: Phy Specific Status=%4.4x\n", ethUnit, regVal));
}
#if 0
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
athrs26_reg_write(0x200, 0x200);
athrs26_reg_write(0x300, 0x200);
athrs26_reg_write(0x400, 0x200);
athrs26_reg_write(0x500, 0x200);
athrs26_reg_write(0x600, 0x200);
athrs26_reg_write(0x38, 0x50e);
#endif
#ifndef CFG_ATHRHDR_EN
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
athrs26_reg_init();
#endif
return (liveLinks > 0);
}
/******************************************************************************
*
* athrs26_phy_is_fdx - Determines whether the phy ports associated with the
* specified device are FULL or HALF duplex.
*
* RETURNS:
* 1 --> FULL
* 0 --> HALF
*/
int
athrs26_phy_is_fdx(int ethUnit)
{
int phyUnit;
uint32_t phyBase;
uint32_t phyAddr;
uint16_t phyHwStatus;
int ii = 200;
if (ethUnit == ENET_UNIT_LAN)
return TRUE;
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
continue;
}
if (athrs26_phy_is_link_alive(phyUnit)) {
phyBase = ATHR_PHYBASE(phyUnit);
phyAddr = ATHR_PHYADDR(phyUnit);
do {
phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
sysMsDelay(10);
} while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
if (phyHwStatus & ATHER_STATUS_FULL_DEPLEX)
return TRUE;
}
}
return FALSE;
}
/******************************************************************************
*
* athrs26_phy_speed - Determines the speed of phy ports associated with the
* specified device.
*
* RETURNS:
* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
* AG7100_PHY_SPEED_1000T;
*/
BOOL
athrs26_phy_speed(int ethUnit)
{
int phyUnit;
uint16_t phyHwStatus;
uint32_t phyBase;
uint32_t phyAddr;
int ii = 200;
if (ethUnit == ENET_UNIT_LAN)
return _100BASET;
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
continue;
}
if (athrs26_phy_is_link_alive(phyUnit)) {
phyBase = ATHR_PHYBASE(phyUnit);
phyAddr = ATHR_PHYADDR(phyUnit);
do {
phy_reg_read(phyBase, phyAddr,
ATHR_PHY_SPEC_STATUS, &phyHwStatus);
sysMsDelay(10);
}while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >>
ATHER_STATUS_LINK_SHIFT);
switch(phyHwStatus) {
case 0:
return _10BASET;
case 1:
return _100BASET;
case 2:
return _1000BASET;
default:
DRV_PRINT(DRV_DEBUG_PHYERROR, ("Unkown speed read!\n"));
}
}
}
return _10BASET;
}
/*****************************************************************************
*
* athr_phy_is_up -- checks for significant changes in PHY state.
*
* A "significant change" is:
* dropped link (e.g. ethernet cable unplugged) OR
* autonegotiation completed + link (e.g. ethernet cable plugged in)
*
* When a PHY is plugged in, phyLinkGained is called.
* When a PHY is unplugged, phyLinkLost is called.
*/
int
athrs26_phy_is_up(int ethUnit)
{
int phyUnit;
uint16_t phyHwStatus;
athrPhyInfo_t *lastStatus;
int linkCount = 0;
int lostLinks = 0;
int gainedLinks = 0;
uint32_t phyBase;
uint32_t phyAddr;
#ifdef CFG_ATHRHDR_REG
/* if using header to config s26, the link of MAC0 should always be up */
if (ethUnit == ENET_UNIT_LAN)
return 1;
#endif
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
continue;
}
phyBase = ATHR_PHYBASE(phyUnit);
phyAddr = ATHR_PHYADDR(phyUnit);
lastStatus = &athrPhyInfo[phyUnit];
phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */
/* See if we've lost link */
if (phyHwStatus & ATHR_STATUS_LINK_PASS) {
linkCount++;
} else {
lostLinks++;
DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n",
ethUnit, phyUnit));
lastStatus->isPhyAlive = FALSE;
}
} else { /* last known link status was DEAD */
/* Check for reset complete */
phy_reg_read(phyBase, phyAddr, ATHR_PHY_STATUS, &phyHwStatus);
if (!ATHR_RESET_DONE(phyHwStatus))
continue;
/* Check for AutoNegotiation complete */
if (ATHR_AUTONEG_DONE(phyHwStatus)) {
//printk("autoneg done\n");
gainedLinks++;
linkCount++;
DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n",
ethUnit, phyUnit));
lastStatus->isPhyAlive = TRUE;
}
}
}
return (linkCount);
#if 0
if (linkCount == 0) {
if (lostLinks) {
/* We just lost the last link for this MAC */
phyLinkLost(ethUnit);
}
} else {
if (gainedLinks == linkCount) {
/* We just gained our first link(s) for this MAC */
phyLinkGained(ethUnit);
}
}
#endif
}
#ifdef CFG_ATHRHDR_EN
void athr_hdr_timeout(void){
eth_halt();
NetState = NETLOOP_FAIL;
}
void athr_hdr_handler(uchar *recv_pkt, unsigned dest, unsigned src, unsigned len){
header_receive_pkt(recv_pkt);
NetState = NETLOOP_SUCCESS;
}
static int
athrs26_header_config_reg (struct eth_device *dev, uint8_t wr_flag,
uint16_t reg_addr, uint16_t cmd_len,
uint8_t *val)
{
at_header_t at_header;
reg_cmd_t reg_cmd;
uchar *AthrHdrPkt;
AthrHdrPkt = NetTxPacket;
if(AthrHdrPkt == NULL) {
printf("Null packet\n");
return;
}
memset(AthrHdrPkt,0,60);
/*fill at_header*/
at_header.reserved0 = 0x10; //default
at_header.priority = 0;
at_header.type = 0x5;
at_header.broadcast = 0;
at_header.from_cpu = 1;
at_header.reserved1 = 0x01; //default
at_header.port_num = 0;
AthrHdrPkt[0] = at_header.port_num;
AthrHdrPkt[0] |= at_header.reserved1 << 4;
AthrHdrPkt[0] |= at_header.from_cpu << 6;
AthrHdrPkt[0] |= at_header.broadcast << 7;
AthrHdrPkt[1] = at_header.type;
AthrHdrPkt[1] |= at_header.priority << 4;
AthrHdrPkt[1] |= at_header.reserved0 << 6;
/*fill reg cmd*/
if(cmd_len > 4)
cmd_len = 4;//only support 32bits register r/w
reg_cmd.reg_addr = reg_addr&0x3FFFC;
reg_cmd.cmd_len = cmd_len;
reg_cmd.cmd = wr_flag;
reg_cmd.reserved2 = 0x5; //default
reg_cmd.seq_num = seqcnt;
AthrHdrPkt[2] = reg_cmd.reg_addr & 0xff;
AthrHdrPkt[3] = (reg_cmd.reg_addr & 0xff00) >> 8;
AthrHdrPkt[4] = (reg_cmd.reg_addr & 0x30000) >> 16;
AthrHdrPkt[4] |= reg_cmd.cmd_len << 4;
AthrHdrPkt[5] = reg_cmd.cmd << 4;
AthrHdrPkt[5] |= reg_cmd.reserved2 << 5;
AthrHdrPkt[6] = (reg_cmd.seq_num & 0x7f) << 1;
AthrHdrPkt[7] = (reg_cmd.seq_num & 0x7f80) >> 7;
AthrHdrPkt[8] = (reg_cmd.seq_num & 0x7f8000) >> 15;
AthrHdrPkt[9] = (reg_cmd.seq_num & 0x7f800000) >> 23;
/*fill reg data*/
if(!wr_flag)//write
memcpy((AthrHdrPkt + 10), val, cmd_len);
/*start xmit*/
if(dev == NULL) {
printf("ERROR device not found\n");
return -1;
}
header_xmit(dev, AthrHdrPkt ,60);
return 0;
}
void athr_hdr_func(void) {
NetSetTimeout (1 * CFG_HZ,athr_hdr_timeout );
NetSetHandler (athr_hdr_handler);
if(cmd)
athrs26_header_config_reg(lan_mac, cmd, cmd_read.reg_addr, cmd_read.cmd_len, cmd_read.reg_data);
else
athrs26_header_config_reg(lan_mac, cmd, cmd_write.reg_addr, cmd_write.cmd_len, cmd_write.reg_data);
}
static int
athrs26_header_write_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
{
int i = 2;
cmd_write.reg_addr = reg_addr;
cmd_write.cmd_len = cmd_len;
cmd_write.reg_data = reg_data;
cmd = 0;
seqcnt++;
do {
if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
break;
} while (i--);
return i;
}
static int
athrs26_header_read_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
{
int i = 2;
cmd_read.reg_addr = reg_addr;
cmd_read.cmd_len = cmd_len;
cmd_read.reg_data = reg_data;
cmd = 1;
seqcnt++;
do {
if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
break;
} while (i--);
if ((i==0) || (seqcnt != cmd_resp.seq) || (cmd_len != cmd_resp.len)) {
return -1;
}
memcpy (cmd_read.reg_data, cmd_resp.data, cmd_len);
return 0;
}
int header_receive_pkt(uchar *recv_pkt)
{
cmd_resp.len = recv_pkt[4] >> 4;
if (cmd_resp.len > 10)
goto out;
cmd_resp.seq = recv_pkt[6] >> 1;
cmd_resp.seq |= recv_pkt[7] << 7;
cmd_resp.seq |= recv_pkt[8] << 15;
cmd_resp.seq |= recv_pkt[9] << 23;
if (cmd_resp.seq < seqcnt)
goto out;
memcpy (cmd_resp.data, (recv_pkt + 10), cmd_resp.len);
out:
return 0;
}
void athrs26_reg_dev(struct eth_device *mac)
{
lan_mac = mac;
}
#endif
/*static uint32_t
athrs26_reg_read(uint16_t reg_addr)
{
#ifndef CFG_ATHRHDR_REG
uint16_t reg_word_addr = reg_addr / 2, phy_val;
uint32_t phy_addr;
uint8_t phy_reg;
phy_addr = 0x18;
phy_reg = 0x0;
phy_val = (reg_word_addr >> 8) & 0x1ff;
phy_reg_write (0, phy_addr, phy_reg, phy_val);
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
phy_reg = reg_word_addr & 0x1f;
phy_reg_read(0, phy_addr, phy_reg, &phy_val);
return phy_val;
#else
uint8_t reg_data[4];
memset (reg_data, 0, 4);
athrs26_header_read_reg(reg_addr, 4, reg_data);
return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24));
#endif
}
*/
static void
athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val)
{
#ifndef CFG_ATHRHDR_REG
uint16_t reg_word_addr = reg_addr / 2, phy_val;
uint32_t phy_addr;
uint8_t phy_reg;
/* configure register high address */
phy_addr = 0x18;
phy_reg = 0x0;
phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
phy_reg_write (0, phy_addr, phy_reg, phy_val);
/* read register with low address */
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address */
phy_reg_write (0, phy_addr, phy_reg, reg_val);
#else
uint8_t reg_data[4];
memset (reg_data, 0, 4);
reg_data[0] = (uint8_t)(0x00ff & reg_val);
reg_data[1] = (uint8_t)((0xff00 & reg_val) >> 8);
reg_data[2] = (uint8_t)((0xff0000 & reg_val) >> 16);
reg_data[3] = (uint8_t)((0xff000000 & reg_val) >> 24);
athrs26_header_write_reg (reg_addr, 4, reg_data);
#endif
}

134
package/uboot-lantiq/files/board/arcadyan/athrs26_phy.h
View File

@ -1,134 +0,0 @@
#ifndef _ATHRS26_PHY_H
#define _ATHRS26_PHY_H
/*****************/
/* PHY Registers */
/*****************/
#define ATHR_PHY_CONTROL 0
#define ATHR_PHY_STATUS 1
#define ATHR_PHY_ID1 2
#define ATHR_PHY_ID2 3
#define ATHR_AUTONEG_ADVERT 4
#define ATHR_LINK_PARTNER_ABILITY 5
#define ATHR_AUTONEG_EXPANSION 6
#define ATHR_NEXT_PAGE_TRANSMIT 7
#define ATHR_LINK_PARTNER_NEXT_PAGE 8
#define ATHR_1000BASET_CONTROL 9
#define ATHR_1000BASET_STATUS 10
#define ATHR_PHY_SPEC_CONTROL 16
#define ATHR_PHY_SPEC_STATUS 17
#define ATHR_DEBUG_PORT_ADDRESS 29
#define ATHR_DEBUG_PORT_DATA 30
/* ATHR_PHY_CONTROL fields */
#define ATHR_CTRL_SOFTWARE_RESET 0x8000
#define ATHR_CTRL_SPEED_LSB 0x2000
#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
#define ATHR_CTRL_SPEED_MSB 0x0040
#define ATHR_RESET_DONE(phy_control) \
(((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
/* Phy status fields */
#define ATHR_STATUS_AUTO_NEG_DONE 0x0020
#define ATHR_AUTONEG_DONE(ip_phy_status) \
(((ip_phy_status) & \
(ATHR_STATUS_AUTO_NEG_DONE)) == \
(ATHR_STATUS_AUTO_NEG_DONE))
/* Link Partner ability */
#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
#define ATHR_LINK_100BASETX 0x0080
#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
#define ATHR_LINK_10BASETX 0x0020
/* Advertisement register. */
#define ATHR_ADVERTISE_NEXT_PAGE 0x8000
#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
#define ATHR_ADVERTISE_PAUSE 0x0400
#define ATHR_ADVERTISE_100FULL 0x0100
#define ATHR_ADVERTISE_100HALF 0x0080
#define ATHR_ADVERTISE_10FULL 0x0040
#define ATHR_ADVERTISE_10HALF 0x0020
#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
/* 1000BASET_CONTROL */
#define ATHR_ADVERTISE_1000FULL 0x0200
/* Phy Specific status fields */
#define ATHER_STATUS_LINK_MASK 0xC000
#define ATHER_STATUS_LINK_SHIFT 14
#define ATHER_STATUS_FULL_DEPLEX 0x2000
#define ATHR_STATUS_LINK_PASS 0x0400
#define ATHR_STATUS_RESOVLED 0x0800
/*phy debug port register */
#define ATHER_DEBUG_SERDES_REG 5
/* Serdes debug fields */
#define ATHER_SERDES_BEACON 0x0100
#ifndef BOOL
#define BOOL int
#define TRUE 1
#define FALSE 0
#endif
#define sysMsDelay(_x) udelay((_x) * 1000)
#undef S26_VER_1_0
#ifdef CFG_ATHRHDR_EN
#include <net.h>
#define header_xmit(dev,pkt,len) dev->send(dev,pkt,len) //dev_queue_xmit(skb)
#define header_recv_ack(dev) dev->recv(dev) //dev_queue_xmit(skb)
typedef enum {
NORMAL_PACKET,
RESERVED0,
MIB_1ST,
RESERVED1,
RESERVED2,
READ_WRITE_REG,
READ_WRITE_REG_ACK,
RESERVED3
} ATHR_HDR_TYPE;
typedef struct {
uint16_t reserved0;
uint16_t priority;
uint16_t type ;
uint16_t broadcast;
uint16_t from_cpu;
uint16_t reserved1;
uint16_t port_num;
}at_header_t;
typedef struct {
uint64_t reg_addr;
uint64_t reserved0;
uint64_t cmd_len;
uint64_t reserved1;
uint64_t cmd;
uint64_t reserved2;
uint64_t seq_num;
}reg_cmd_t;
void athrs26_reg_init(void);
int header_receive_pkt(uchar *pkt);
void athrs26_reg_dev(struct eth_device *mac);
#endif
int athrs26_phy_is_up(int unit);
int athrs26_phy_is_fdx(int unit);
int athrs26_phy_speed(int unit);
BOOL athrs26_phy_setup(int unit);
#endif /* _ATHRS26_PHY_H */

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package/uboot-lantiq/files/board/arcadyan/board.c
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/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Thomas Langer, Ralph Hempel
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/addrspace.h>
#include <asm/danube.h>
#include <asm/reboot.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_HTTPD)
#include <httpd.h>
#endif
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#if defined(CONFIG_AR8216_SWITCH)
#include "athrs26_phy.h"
#endif
extern ulong ifx_get_ddr_hz(void);
extern ulong ifx_get_cpuclk(void);
/* IDs and registers of known external switches */
void _machine_restart(void)
{
*DANUBE_RCU_RST_REQ |=1<<30;
}
#ifdef CONFIG_SYS_RAMBOOT
phys_size_t initdram(int board_type)
{
return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
}
#elif defined(CONFIG_USE_DDR_RAM)
phys_size_t initdram(int board_type)
{
return (CONFIG_SYS_MAX_RAM);
}
#else
static ulong max_sdram_size(void) /* per Chip Select */
{
/* The only supported SDRAM data width is 16bit.
*/
#define CFG_DW 4
/* The only supported number of SDRAM banks is 4.
*/
#define CFG_NB 4
ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
int cols = cfgpb0 & 0xF;
int rows = (cfgpb0 & 0xF0) >> 4;
ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
return size;
}
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*/
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
phys_size_t initdram(int board_type)
{
int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
ulong size, max_size = 0;
ulong our_address;
/* load t9 into our_address */
asm volatile ("move %0, $25" : "=r" (our_address) :);
/* Can't probe for RAM size unless we are running from Flash.
* find out whether running from DRAM or Flash.
*/
if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
{
return max_sdram_size();
}
for (cols = 0x8; cols <= 0xC; cols++)
{
for (rows = 0xB; rows <= 0xD; rows++)
{
*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
(rows << 4) | cols;
size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
max_sdram_size());
if (size > max_size)
{
best_val = *DANUBE_SDRAM_MC_CFGPB0;
max_size = size;
}
}
}
*DANUBE_SDRAM_MC_CFGPB0 = best_val;
return max_size;
}
#endif
static void gpio_default(void)
{
#ifdef CONFIG_SWITCH_PORT0
*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
#elif defined(CONFIG_SWITCH_PORT1)
*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
#endif
#ifdef CONFIG_EBU_GPIO
{
int i = 0;
printf ("bring up ebu gpio\n");
*DANUBE_EBU_BUSCON1 = 0x1e7ff;
*DANUBE_EBU_ADDSEL1 = 0x14000001;
*((volatile u16*)0xb4000000) = 0x0;
for(i = 0; i < 1000; i++)
udelay(1000);
*((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO;
*DANUBE_EBU_BUSCON1 = 0x8001e7ff;
}
#endif
#ifdef CONFIG_BUTTON_PORT0
*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
{
printf("button is pressed\n");
setenv("bootdelay", "0");
setenv("bootcmd", "httpd");
}
#elif defined(CONFIG_BUTTON_PORT1)
*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
{
printf("button is pressed\n");
setenv("bootdelay", "0");
setenv("bootcmd", "httpd");
}
#endif
#ifdef CONFIG_ARV4525
*DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
#endif
}
int checkboard (void)
{
unsigned long chipid = *DANUBE_MPS_CHIPID;
int part_num;
puts ("Board: "CONFIG_ARCADYAN"\n");
puts ("SoC: ");
part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
switch (part_num)
{
case 0x129:
case 0x12D:
case 0x12b:
puts("Danube/Twinpass/Vinax-VE ");
break;
default:
printf ("unknown, chip part number 0x%03X ", part_num);
break;
}
printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
return 0;
}
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
int board_early_init_f(void)
{
#ifdef CONFIG_EBU_ADDSEL0
(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
#endif
#ifdef CONFIG_EBU_ADDSEL1
(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
#endif
#ifdef CONFIG_EBU_ADDSEL2
(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
#endif
#ifdef CONFIG_EBU_ADDSEL3
(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
#endif
#ifdef CONFIG_EBU_BUSCON0
(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
#endif
#ifdef CONFIG_EBU_BUSCON1
(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
#endif
#ifdef CONFIG_EBU_BUSCON2
(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
#endif
#ifdef CONFIG_EBU_BUSCON3
(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
#endif
return 0;
}
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifdef CONFIG_RTL8306_SWITCH
#define ID_RTL8306 0x5988
static int external_switch_rtl8306(void)
{
unsigned short chipid;
static char * const name = "lq_cpe_eth";
udelay(100000);
puts("\nsearching for rtl8306 switch ... ");
if (miiphy_read(name, 4, 30, &chipid) == 0) {
if (chipid == ID_RTL8306) {
puts("found");
/* set led mode */
miiphy_write(name, 0, 19, 0xffff);
/* magic */
miiphy_write(name, 4, 22, 0x877f);
puts("\n");
return 0;
}
puts("failed\n");
}
puts("\nno known switch found ... \n");
return 0;
}
#endif
#ifdef CONFIG_RTL8306G_SWITCH
#define ID_RTL8306 0x5988
static int external_switch_rtl8306G(void)
{
unsigned short chipid,val;
int i;
static char * const name = "lq_cpe_eth";
unsigned int chipid2, chipver, chiptype;
char str[128];
int cpu_mask = 1 << 5;
udelay(100000);
puts("\nsearching for rtl8306 switch ... ");
if (miiphy_read(name, 4, 30, &chipid) == 0) {
if (chipid == ID_RTL8306) {
puts("found\nReset Hard\n");
#ifdef CONFIG_ARV752DPW
//gpio 19
//reset reset ping to high
*DANUBE_GPIO_P1_DIR |= 8;
*DANUBE_GPIO_P1_OUT |= 8;
udelay(500*1000);
*DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
udelay(500*1000);
*DANUBE_GPIO_P1_OUT |= 8;
udelay(500*1000);
puts("Done\n");
#endif
/* set led mode */
miiphy_write(name, 0, 0, 0x3100);
miiphy_write(name, 0, 18, 0x7fff);
miiphy_write(name, 0, 19, 0xffff);
miiphy_write(name, 0, 22, 0x877f);
miiphy_write(name, 0, 24, 0x0ed1);
miiphy_write(name, 1, 0, 0x3100);
miiphy_write(name, 1, 22, 0x877f);
miiphy_write(name, 1, 24, 0x1ed2);
miiphy_write(name, 2, 0, 0x3100);
miiphy_write(name, 2, 22, 0x877f);
miiphy_write(name, 2, 23, 0x0020);
miiphy_write(name, 2, 24, 0x2ed4);
miiphy_write(name, 3, 0, 0x3100);
miiphy_write(name, 3, 22, 0x877f);
miiphy_write(name, 3, 24, 0x3ed8);
miiphy_write(name, 4, 0, 0x3100);
miiphy_write(name, 4, 22, 0x877f);
miiphy_write(name, 4, 24, 0x4edf);
miiphy_write(name, 5, 0, 0x3100);
miiphy_write(name, 6, 0, 0x2100);
//important. enable phy 5 link status, for rmii
miiphy_write(name, 6, 22, 0x873f);
miiphy_write(name, 6, 24, 0x8eff);
//disable ports
for (i=0;i<5;i++) {
miiphy_read(name, 0, 24, &val);
val&=~(1<<10);
val&=~(1<<11);
miiphy_write(name, 0, 24, val);
}
puts("Reset Soft\n");
miiphy_write(name,0 ,0 ,1<<15);
for (i=0;i<1000;i++)
{
miiphy_read(name,0 ,0 ,&val);
if (!(val&1<<15))
break;
udelay(1000);
}
if (i==1000)
puts("Failed\n");
else
puts("Success\n");
//enable ports egain
for (i=0;i<5;i++) // enable ports
{
miiphy_read(name, 0, 24, &val);
val|=(1<<10);
val|=(1<<11);
miiphy_write(name, 0, 24, val);
}
puts("\n");
return 0;
}
puts("failed\n");
}
puts("\nno known switch found ... \n");
return 0;
}
#endif
#ifdef CONFIG_AR8216_SWITCH
static int external_switch_ar8216(void)
{
puts("initializing ar8216 switch... ");
if (athrs26_phy_setup(0)==0) {
printf("initialized\n");
return 0;
}
puts("failed ... \n");
return 0;
}
#endif
int board_eth_init(bd_t *bis)
{
gpio_default();
#if defined(CONFIG_IFX_ETOP)
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
if (lq_eth_initialize(bis))
return -1;
*DANUBE_RCU_RST_REQ |=1;
udelay(200000);
*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
udelay(1000);
#ifdef CONFIG_RTL8306G_SWITCH
if (external_switch_rtl8306G()<0)
return -1;
#endif
#ifdef CONFIG_RTL8306_SWITCH
if (external_switch_rtl8306()<0)
return -1;
#endif
#ifdef CONFIG_AR8216_SWITCH
if (external_switch_ar8216()<0)
return -1;
#endif
#endif
return 0;
}
#if defined(CONFIG_CMD_HTTPD)
int do_http_upgrade(const unsigned char *data, const ulong size)
{
char buf[128];
if(getenv ("ram_addr") == NULL)
return -1;
if(getenv ("kernel_addr") == NULL)
return -1;
/* check the image */
if(run_command("imi ${ram_addr}", 0) < 0) {
return -1;
}
/* write the image to the flash */
puts("http ugrade ...\n");
sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
return run_command(buf, 0);
}
int do_http_progress(const int state)
{
/* toggle LED's here */
switch(state) {
case HTTP_PROGRESS_START:
puts("http start\n");
break;
case HTTP_PROGRESS_TIMEOUT:
puts(".");
break;
case HTTP_PROGRESS_UPLOAD_READY:
puts("http upload ready\n");
break;
case HTTP_PROGRESS_UGRADE_READY:
puts("http ugrade ready\n");
break;
case HTTP_PROGRESS_UGRADE_FAILED:
puts("http ugrade failed\n");
break;
}
return 0;
}
unsigned long do_http_tmp_address(void)
{
char *s = getenv ("ram_addr");
if (s) {
ulong tmp = simple_strtoul (s, NULL, 16);
return tmp;
}
return 0 /*0x80a00000*/;
}
#endif

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package/uboot-lantiq/files/board/arcadyan/config.mk
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@ -1,36 +0,0 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifdef CONFIG_BOOTSTRAP
TEXT_BASE = 0x80001000
CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
CONFIG_SYS_RAMBOOT = y
else
ifndef TEXT_BASE
$(info redefine TEXT_BASE = 0xB0000000 )
TEXT_BASE = 0xB0000000
endif
endif

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package/uboot-lantiq/files/board/arcadyan/ddr_settings.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x130 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1b00
#define MC_DC22_VALUE 0x1b1b
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x4e20
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
#define MC_DC46_VALUE 0x0

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package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1700
#define MC_DC22_VALUE 0x1717
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x4e20
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

47
package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h
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@ -1,47 +0,0 @@
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x134 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1400
#define MC_DC22_VALUE 0x1414
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5b /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x4e20
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
#define MC_DC46_VALUE 0x0

583
package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S
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@ -1,583 +0,0 @@
/*
* Memory sub-system initialization code for Danube board.
* Andre Messerschmidt
* Copyright (c) 2005 Infineon Technologies AG
*
* Based on Inca-IP code
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* History:
peng liu May 25, 2006, for PLL setting after reset, 05252006
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#if defined(CONFIG_USE_DDR_PSC_32)
#include "ddr_settings_psc_32.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_PSC_64)
#include "ddr_settings_psc_64.h"
#define DDR166
#else
#error "missing definition for RAM"
#endif
#define EBU_MODUL_BASE 0xBE105300
#define EBU_CLC(value) 0x0000(value)
#define EBU_CON(value) 0x0010(value)
#define EBU_ADDSEL0(value) 0x0020(value)
#define EBU_ADDSEL1(value) 0x0024(value)
#define EBU_ADDSEL2(value) 0x0028(value)
#define EBU_ADDSEL3(value) 0x002C(value)
#define EBU_BUSCON0(value) 0x0060(value)
#define EBU_BUSCON1(value) 0x0064(value)
#define EBU_BUSCON2(value) 0x0068(value)
#define EBU_BUSCON3(value) 0x006C(value)
#define MC_MODUL_BASE 0xBF800000
#define MC_ERRCAUSE(value) 0x0010(value)
#define MC_ERRADDR(value) 0x0020(value)
#define MC_CON(value) 0x0060(value)
#define MC_SRAM_ENABLE 0x00000004
#define MC_SDRAM_ENABLE 0x00000002
#define MC_DDRRAM_ENABLE 0x00000001
#define MC_SDR_MODUL_BASE 0xBF800200
#define MC_IOGP(value) 0x0000(value)
#define MC_CTRLENA(value) 0x0010(value)
#define MC_MRSCODE(value) 0x0020(value)
#define MC_CFGDW(value) 0x0030(value)
#define MC_CFGPB0(value) 0x0040(value)
#define MC_LATENCY(value) 0x0080(value)
#define MC_TREFRESH(value) 0x0090(value)
#define MC_SELFRFSH(value) 0x00A0(value)
#define MC_DDR_MODUL_BASE 0xBF801000
#define MC_DC00(value) 0x0000(value)
#define MC_DC01(value) 0x0010(value)
#define MC_DC02(value) 0x0020(value)
#define MC_DC03(value) 0x0030(value)
#define MC_DC04(value) 0x0040(value)
#define MC_DC05(value) 0x0050(value)
#define MC_DC06(value) 0x0060(value)
#define MC_DC07(value) 0x0070(value)
#define MC_DC08(value) 0x0080(value)
#define MC_DC09(value) 0x0090(value)
#define MC_DC10(value) 0x00A0(value)
#define MC_DC11(value) 0x00B0(value)
#define MC_DC12(value) 0x00C0(value)
#define MC_DC13(value) 0x00D0(value)
#define MC_DC14(value) 0x00E0(value)
#define MC_DC15(value) 0x00F0(value)
#define MC_DC16(value) 0x0100(value)
#define MC_DC17(value) 0x0110(value)
#define MC_DC18(value) 0x0120(value)
#define MC_DC19(value) 0x0130(value)
#define MC_DC20(value) 0x0140(value)
#define MC_DC21(value) 0x0150(value)
#define MC_DC22(value) 0x0160(value)
#define MC_DC23(value) 0x0170(value)
#define MC_DC24(value) 0x0180(value)
#define MC_DC25(value) 0x0190(value)
#define MC_DC26(value) 0x01A0(value)
#define MC_DC27(value) 0x01B0(value)
#define MC_DC28(value) 0x01C0(value)
#define MC_DC29(value) 0x01D0(value)
#define MC_DC30(value) 0x01E0(value)
#define MC_DC31(value) 0x01F0(value)
#define MC_DC32(value) 0x0200(value)
#define MC_DC33(value) 0x0210(value)
#define MC_DC34(value) 0x0220(value)
#define MC_DC35(value) 0x0230(value)
#define MC_DC36(value) 0x0240(value)
#define MC_DC37(value) 0x0250(value)
#define MC_DC38(value) 0x0260(value)
#define MC_DC39(value) 0x0270(value)
#define MC_DC40(value) 0x0280(value)
#define MC_DC41(value) 0x0290(value)
#define MC_DC42(value) 0x02A0(value)
#define MC_DC43(value) 0x02B0(value)
#define MC_DC44(value) 0x02C0(value)
#define MC_DC45(value) 0x02D0(value)
#define MC_DC46(value) 0x02E0(value)
#define RCU_OFFSET 0xBF203000
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
#define RCU_STS (RCU_OFFSET + 0x0014)
#define CGU_OFFSET 0xBF103000
#define PLL0_CFG (CGU_OFFSET + 0x0004)
#define PLL1_CFG (CGU_OFFSET + 0x0008)
#define PLL2_CFG (CGU_OFFSET + 0x000C)
#define CGU_SYS (CGU_OFFSET + 0x0010)
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
#define IF_CLK (CGU_OFFSET + 0x0018)
#define CGU_SMD (CGU_OFFSET + 0x0020)
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
//05252006
#define pll0_35MHz_CONFIG 0x9D861059
#define pll1_35MHz_CONFIG 0x1A260CD9
#define pll2_35MHz_CONFIG 0x8000f1e5
#define pll0_36MHz_CONFIG 0x1000125D
#define pll1_36MHz_CONFIG 0x1B1E0C99
#define pll2_36MHz_CONFIG 0x8002f2a1
//05252006
//06063001-joelin disable the PCI CFRAME mask -start
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
*/
#define PCI_CR_PR_OFFSET 0xBE105400
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
#define PCI_CONFIG_SPACE 0xB7000000
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
//06063001-joelin disable the PCI CFRAME mask -end
.set noreorder
/*
* void ebu_init(void)
*/
.globl ebu_init
.ent ebu_init
ebu_init:
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
li t1, EBU_MODUL_BASE
#if defined(CONFIG_EBU_ADDSEL0)
li t2, CONFIG_EBU_ADDSEL0
sw t2, EBU_ADDSEL0(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL1)
li t2, CONFIG_EBU_ADDSEL1
sw t2, EBU_ADDSEL1(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL2)
li t2, CONFIG_EBU_ADDSEL2
sw t2, EBU_ADDSEL2(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL3)
li t2, CONFIG_EBU_ADDSEL3
sw t2, EBU_ADDSEL3(t1)
#endif
#if defined(CONFIG_EBU_BUSCON0)
li t2, CONFIG_EBU_BUSCON0
sw t2, EBU_BUSCON0(t1)
#endif
#if defined(CONFIG_EBU_BUSCON1)
li t2, CONFIG_EBU_BUSCON1
sw t2, EBU_BUSCON1(t1)
#endif
#if defined(CONFIG_EBU_BUSCON2)
li t2, CONFIG_EBU_BUSCON2
sw t2, EBU_BUSCON2(t1)
#endif
#if defined(CONFIG_EBU_BUSCON3)
li t2, CONFIG_EBU_BUSCON3
sw t2, EBU_BUSCON3(t1)
#endif
#endif
j ra
nop
.end ebu_init
/*
* void cgu_init(long)
*
* a0 has the clock value
*/
.globl cgu_init
.ent cgu_init
cgu_init:
li t2, CGU_SYS
lw t2,0(t2)
beq t2,a0,freq_up2date
nop
li t2, RCU_STS
lw t2, 0(t2)
and t2,0x00020000
beq t2,0x00020000,boot_36MHZ
nop
//05252006
li t1, PLL0_CFG
li t2, pll0_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_35MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
b wait_reset
nop
boot_36MHZ:
li t1, PLL0_CFG
li t2, pll0_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_36MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
//05252006
wait_reset:
b wait_reset
nop
freq_up2date:
j ra
nop
.end cgu_init
#ifndef CONFIG_USE_DDR_RAM
/*
* void sdram_init(long)
*
* a0 has the clock value
*/
.globl sdram_init
.ent sdram_init
sdram_init:
/* SDRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable SDRAM module in memory controller */
li t3, MC_SDRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_SDR_MODUL_BASE
/* disable the controller */
li t2, 0
sw t2, MC_CTRLENA(t1)
li t2, 0x822
sw t2, MC_IOGP(t1)
li t2, 0x2
sw t2, MC_CFGDW(t1)
/* Set CAS Latency */
li t2, 0x00000020
sw t2, MC_MRSCODE(t1)
/* Set CS0 to SDRAM parameters */
li t2, 0x000014d8
sw t2, MC_CFGPB0(t1)
/* Set SDRAM latency parameters */
li t2, 0x00036325; /* BC PC100 */
sw t2, MC_LATENCY(t1)
/* Set SDRAM refresh rate */
li t2, 0x00000C30
sw t2, MC_TREFRESH(t1)
/* Clear Power-down registers */
sw zero, MC_SELFRFSH(t1)
/* Finally enable the controller */
li t2, 1
sw t2, MC_CTRLENA(t1)
j ra
nop
.end sdram_init
#endif /* !CONFIG_USE_DDR_RAM */
#ifdef CONFIG_USE_DDR_RAM
/*
* void ddrram_init(long)
*
* a0 has the clock value
*/
.globl ddrram_init
.ent ddrram_init
ddrram_init:
/* DDR-DRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable DDR module in memory controller */
li t3, MC_DDRRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_DDR_MODUL_BASE
/* Write configuration to DDR controller registers */
li t2, MC_DC0_VALUE
sw t2, MC_DC00(t1)
li t2, MC_DC1_VALUE
sw t2, MC_DC01(t1)
li t2, MC_DC2_VALUE
sw t2, MC_DC02(t1)
li t2, MC_DC3_VALUE
sw t2, MC_DC03(t1)
li t2, MC_DC4_VALUE
sw t2, MC_DC04(t1)
li t2, MC_DC5_VALUE
sw t2, MC_DC05(t1)
li t2, MC_DC6_VALUE
sw t2, MC_DC06(t1)
li t2, MC_DC7_VALUE
sw t2, MC_DC07(t1)
li t2, MC_DC8_VALUE
sw t2, MC_DC08(t1)
li t2, MC_DC9_VALUE
sw t2, MC_DC09(t1)
li t2, MC_DC10_VALUE
sw t2, MC_DC10(t1)
li t2, MC_DC11_VALUE
sw t2, MC_DC11(t1)
li t2, MC_DC12_VALUE
sw t2, MC_DC12(t1)
li t2, MC_DC13_VALUE
sw t2, MC_DC13(t1)
li t2, MC_DC14_VALUE
sw t2, MC_DC14(t1)
li t2, MC_DC15_VALUE
sw t2, MC_DC15(t1)
li t2, MC_DC16_VALUE
sw t2, MC_DC16(t1)
li t2, MC_DC17_VALUE
sw t2, MC_DC17(t1)
li t2, MC_DC18_VALUE
sw t2, MC_DC18(t1)
li t2, MC_DC19_VALUE
sw t2, MC_DC19(t1)
li t2, MC_DC20_VALUE
sw t2, MC_DC20(t1)
li t2, MC_DC21_VALUE
sw t2, MC_DC21(t1)
li t2, MC_DC22_VALUE
sw t2, MC_DC22(t1)
li t2, MC_DC23_VALUE
sw t2, MC_DC23(t1)
li t2, MC_DC24_VALUE
sw t2, MC_DC24(t1)
li t2, MC_DC25_VALUE
sw t2, MC_DC25(t1)
li t2, MC_DC26_VALUE
sw t2, MC_DC26(t1)
li t2, MC_DC27_VALUE
sw t2, MC_DC27(t1)
li t2, MC_DC28_VALUE
sw t2, MC_DC28(t1)
li t2, MC_DC29_VALUE
sw t2, MC_DC29(t1)
li t2, MC_DC30_VALUE
sw t2, MC_DC30(t1)
li t2, MC_DC31_VALUE
sw t2, MC_DC31(t1)
li t2, MC_DC32_VALUE
sw t2, MC_DC32(t1)
li t2, MC_DC33_VALUE
sw t2, MC_DC33(t1)
li t2, MC_DC34_VALUE
sw t2, MC_DC34(t1)
li t2, MC_DC35_VALUE
sw t2, MC_DC35(t1)
li t2, MC_DC36_VALUE
sw t2, MC_DC36(t1)
li t2, MC_DC37_VALUE
sw t2, MC_DC37(t1)
li t2, MC_DC38_VALUE
sw t2, MC_DC38(t1)
li t2, MC_DC39_VALUE
sw t2, MC_DC39(t1)
li t2, MC_DC40_VALUE
sw t2, MC_DC40(t1)
li t2, MC_DC41_VALUE
sw t2, MC_DC41(t1)
li t2, MC_DC42_VALUE
sw t2, MC_DC42(t1)
li t2, MC_DC43_VALUE
sw t2, MC_DC43(t1)
li t2, MC_DC44_VALUE
sw t2, MC_DC44(t1)
li t2, MC_DC45_VALUE
sw t2, MC_DC45(t1)
li t2, MC_DC46_VALUE
sw t2, MC_DC46(t1)
li t2, 0x00000100
sw t2, MC_DC03(t1)
j ra
nop
.end ddrram_init
#endif /* CONFIG_USE_DDR_RAM */
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
*/
move t0, ra
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
#if defined(DDR166)
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
li a0,0xe8
#elif defined(DDR133)
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
li a0,0xe9
#else /* defined(DDR111) */
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
li a0,0xea
#endif
bal cgu_init
nop
bal ebu_init
nop
//06063001-joelin disable the PCI CFRAME mask-start
#ifdef DISABLE_CFRAME
li t1, PCI_CR_PCI //mw bf103034 80000000
li t2, 0x80000000
sw t2,0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x103
sw t2,0(t1)
li t1, CS_CFM //mw b700006c 0
li t2, 0x00
sw t2, 0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x1000103
sw t2, 0(t1)
#endif
//06063001-joelin disable the PCI CFRAME mask-end
#ifdef CONFIG_USE_DDR_RAM
bal ddrram_init
nop
#else
bal sdram_init
nop
#endif
move ra, t0
j ra
nop
.end lowlevel_init

279
package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S
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@ -1,279 +0,0 @@
/*
* Memory sub-system initialization code for Danube board.
* Andre Messerschmidt
* Copyright (c) 2005 Infineon Technologies AG
*
* Based on Inca-IP code
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* History:
peng liu May 25, 2006, for PLL setting after reset, 05252006
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#if defined(CONFIG_USE_DDR_PSC_32)
#include "ddr_settings_psc_32.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_PSC_64)
#include "ddr_settings_psc_64.h"
#define DDR166
#else
#error "missing definition for RAM"
#endif
#define EBU_MODUL_BASE 0xBE105300
#define EBU_CLC(value) 0x0000(value)
#define EBU_CON(value) 0x0010(value)
#define EBU_ADDSEL0(value) 0x0020(value)
#define EBU_ADDSEL1(value) 0x0024(value)
#define EBU_ADDSEL2(value) 0x0028(value)
#define EBU_ADDSEL3(value) 0x002C(value)
#define EBU_BUSCON0(value) 0x0060(value)
#define EBU_BUSCON1(value) 0x0064(value)
#define EBU_BUSCON2(value) 0x0068(value)
#define EBU_BUSCON3(value) 0x006C(value)
#define MC_MODUL_BASE 0xBF800000
#define MC_ERRCAUSE(value) 0x0010(value)
#define MC_ERRADDR(value) 0x0020(value)
#define MC_CON(value) 0x0060(value)
#define MC_SRAM_ENABLE 0x00000004
#define MC_SDRAM_ENABLE 0x00000002
#define MC_DDRRAM_ENABLE 0x00000001
#define MC_SDR_MODUL_BASE 0xBF800200
#define MC_IOGP(value) 0x0000(value)
#define MC_CTRLENA(value) 0x0010(value)
#define MC_MRSCODE(value) 0x0020(value)
#define MC_CFGDW(value) 0x0030(value)
#define MC_CFGPB0(value) 0x0040(value)
#define MC_LATENCY(value) 0x0080(value)
#define MC_TREFRESH(value) 0x0090(value)
#define MC_SELFRFSH(value) 0x00A0(value)
#define MC_DDR_MODUL_BASE 0xBF801000
#define MC_DC00(value) 0x0000(value)
#define MC_DC01(value) 0x0010(value)
#define MC_DC02(value) 0x0020(value)
#define MC_DC03(value) 0x0030(value)
#define MC_DC04(value) 0x0040(value)
#define MC_DC05(value) 0x0050(value)
#define MC_DC06(value) 0x0060(value)
#define MC_DC07(value) 0x0070(value)
#define MC_DC08(value) 0x0080(value)
#define MC_DC09(value) 0x0090(value)
#define MC_DC10(value) 0x00A0(value)
#define MC_DC11(value) 0x00B0(value)
#define MC_DC12(value) 0x00C0(value)
#define MC_DC13(value) 0x00D0(value)
#define MC_DC14(value) 0x00E0(value)
#define MC_DC15(value) 0x00F0(value)
#define MC_DC16(value) 0x0100(value)
#define MC_DC17(value) 0x0110(value)
#define MC_DC18(value) 0x0120(value)
#define MC_DC19(value) 0x0130(value)
#define MC_DC20(value) 0x0140(value)
#define MC_DC21(value) 0x0150(value)
#define MC_DC22(value) 0x0160(value)
#define MC_DC23(value) 0x0170(value)
#define MC_DC24(value) 0x0180(value)
#define MC_DC25(value) 0x0190(value)
#define MC_DC26(value) 0x01A0(value)
#define MC_DC27(value) 0x01B0(value)
#define MC_DC28(value) 0x01C0(value)
#define MC_DC29(value) 0x01D0(value)
#define MC_DC30(value) 0x01E0(value)
#define MC_DC31(value) 0x01F0(value)
#define MC_DC32(value) 0x0200(value)
#define MC_DC33(value) 0x0210(value)
#define MC_DC34(value) 0x0220(value)
#define MC_DC35(value) 0x0230(value)
#define MC_DC36(value) 0x0240(value)
#define MC_DC37(value) 0x0250(value)
#define MC_DC38(value) 0x0260(value)
#define MC_DC39(value) 0x0270(value)
#define MC_DC40(value) 0x0280(value)
#define MC_DC41(value) 0x0290(value)
#define MC_DC42(value) 0x02A0(value)
#define MC_DC43(value) 0x02B0(value)
#define MC_DC44(value) 0x02C0(value)
#define MC_DC45(value) 0x02D0(value)
#define MC_DC46(value) 0x02E0(value)
#define RCU_OFFSET 0xBF203000
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
#define RCU_STS (RCU_OFFSET + 0x0014)
#define CGU_OFFSET 0xBF103000
#define PLL0_CFG (CGU_OFFSET + 0x0004)
#define PLL1_CFG (CGU_OFFSET + 0x0008)
#define PLL2_CFG (CGU_OFFSET + 0x000C)
#define CGU_SYS (CGU_OFFSET + 0x0010)
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
#define IF_CLK (CGU_OFFSET + 0x0018)
#define CGU_SMD (CGU_OFFSET + 0x0020)
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
//05252006
#define pll0_35MHz_CONFIG 0x9D861059
#define pll1_35MHz_CONFIG 0x1A260CD9
#define pll2_35MHz_CONFIG 0x8000f1e5
#define pll0_36MHz_CONFIG 0x1000125D
#define pll1_36MHz_CONFIG 0x1B1E0C99
#define pll2_36MHz_CONFIG 0x8002f2a1
//05252006
//06063001-joelin disable the PCI CFRAME mask -start
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
*/
#define PCI_CR_PR_OFFSET 0xBE105400
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
#define PCI_CONFIG_SPACE 0xB7000000
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
//06063001-joelin disable the PCI CFRAME mask -end
.set noreorder
/*
* void ebu_init(void)
*/
.globl ebu_init
.ent ebu_init
ebu_init:
j ra
nop
.end ebu_init
/*
* void cgu_init(long)
*
* a0 has the clock value
*/
.globl cgu_init
.ent cgu_init
cgu_init:
li t2, CGU_SYS
lw t2,0(t2)
beq t2,a0,freq_up2date
nop
li t2, RCU_STS
lw t2, 0(t2)
and t2,0x00020000
beq t2,0x00020000,boot_36MHZ
nop
//05252006
li t1, PLL0_CFG
li t2, pll0_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_35MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
b wait_reset
nop
boot_36MHZ:
li t1, PLL0_CFG
li t2, pll0_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_36MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
//05252006
wait_reset:
b wait_reset
nop
freq_up2date:
j ra
nop
.end cgu_init
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
*/
move t0, ra
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
bal ebu_init
nop
//06063001-joelin disable the PCI CFRAME mask-start
#ifdef DISABLE_CFRAME
li t1, PCI_CR_PCI //mw bf103034 80000000
li t2, 0x80000000
sw t2,0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x103
sw t2,0(t1)
li t1, CS_CFM //mw b700006c 0
li t2, 0x00
sw t2, 0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x1000103
sw t2, 0(t1)
#endif
//06063001-joelin disable the PCI CFRAME mask-end
move ra, t0
j ra
nop
.end lowlevel_init

48
package/uboot-lantiq/files/board/arcadyan/pmuenable.S
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@ -1,48 +0,0 @@
/*
* Power Management unit initialization code for AMAZON development board.
*
* Copyright (c) 2003 Ou Ke, Infineon.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#define PMU_PWDCR 0xBF10201C
#define PMU_SR 0xBF102020
.globl pmuenable
pmuenable:
li t0, PMU_PWDCR
li t1, 0x2 /* enable everything */
sw t1, 0(t0)
#if 0
1:
li t0, PMU_SR
lw t2, 0(t0)
bne t1, t2, 1b
nop
#endif
j ra
nop

74
package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds
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@ -1,74 +0,0 @@
/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = .;
_gp = ALIGN(16) +0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
. = ALIGN(4);
.sdata : { *(.sdata) }
. = .;
. = ALIGN(4);
.payload : { *(.payload) }
. = ALIGN(4);
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}

70
package/uboot-lantiq/files/board/arcadyan/u-boot.lds
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@ -1,70 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}

62
package/uboot-lantiq/files/board/infineon/easy50712/Makefile
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@ -1,62 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
COBJS-y += danube.o
SOBJS = lowlevel_init.o pmuenable.o
BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

40
package/uboot-lantiq/files/board/infineon/easy50712/config.mk
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@ -1,40 +0,0 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Danube board with MIPS 24Kc CPU core
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifdef CONFIG_BOOTSTRAP
TEXT_BASE = 0x80001000
CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
CONFIG_SYS_RAMBOOT = y
else
ifndef TEXT_BASE
$(info redefine TEXT_BASE = 0xB0000000 )
TEXT_BASE = 0xB0000000
endif
endif

436
package/uboot-lantiq/files/board/infineon/easy50712/danube.c
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@ -1,436 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Thomas Langer, Ralph Hempel
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/addrspace.h>
#include <asm/danube.h>
#include <asm/reboot.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_HTTPD)
#include <httpd.h>
#endif
extern ulong ifx_get_ddr_hz(void);
extern ulong ifx_get_cpuclk(void);
/* definitions for external PHYs / Switches */
/* Split values into phy address and register address */
#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
/* IDs and registers of known external switches */
#define ID_SAMURAI_0 0x1020
#define ID_SAMURAI_1 0x0007
#define SAMURAI_ID_REG0 0xA0
#define SAMURAI_ID_REG1 0xA1
#define ID_TANTOS 0x2599
void _machine_restart(void)
{
*DANUBE_RCU_RST_REQ |=1<<30;
}
#ifdef CONFIG_SYS_RAMBOOT
phys_size_t initdram(int board_type)
{
return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
}
#elif defined(CONFIG_USE_DDR_RAM)
phys_size_t initdram(int board_type)
{
return (CONFIG_SYS_MAX_RAM);
}
#else
static ulong max_sdram_size(void) /* per Chip Select */
{
/* The only supported SDRAM data width is 16bit.
*/
#define CFG_DW 4
/* The only supported number of SDRAM banks is 4.
*/
#define CFG_NB 4
ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
int cols = cfgpb0 & 0xF;
int rows = (cfgpb0 & 0xF0) >> 4;
ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
return size;
}
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*/
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
phys_size_t initdram(int board_type)
{
int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
ulong size, max_size = 0;
ulong our_address;
/* load t9 into our_address */
asm volatile ("move %0, $25" : "=r" (our_address) :);
/* Can't probe for RAM size unless we are running from Flash.
* find out whether running from DRAM or Flash.
*/
if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
{
return max_sdram_size();
}
for (cols = 0x8; cols <= 0xC; cols++)
{
for (rows = 0xB; rows <= 0xD; rows++)
{
*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
(rows << 4) | cols;
size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
max_sdram_size());
if (size > max_size)
{
best_val = *DANUBE_SDRAM_MC_CFGPB0;
max_size = size;
}
}
}
*DANUBE_SDRAM_MC_CFGPB0 = best_val;
return max_size;
}
#endif
int checkboard (void)
{
unsigned long chipid = *DANUBE_MPS_CHIPID;
int part_num;
puts ("Board: ");
part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
switch (part_num)
{
case 0x129:
case 0x12B:
case 0x12D:
puts("Danube/Twinpass/Vinax-VE ");
break;
default:
printf ("unknown, chip part number 0x%03X ", part_num);
break;
}
printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
return 0;
}
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
int board_early_init_f(void)
{
#ifdef CONFIG_EBU_ADDSEL0
(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
#endif
#ifdef CONFIG_EBU_ADDSEL1
(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
#endif
#ifdef CONFIG_EBU_ADDSEL2
(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
#endif
#ifdef CONFIG_EBU_ADDSEL3
(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
#endif
#ifdef CONFIG_EBU_BUSCON0
(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
#endif
#ifdef CONFIG_EBU_BUSCON1
(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
#endif
#ifdef CONFIG_EBU_BUSCON2
(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
#endif
#ifdef CONFIG_EBU_BUSCON3
(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
#endif
return 0;
}
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifdef CONFIG_EXTRA_SWITCH
static int external_switch_init(void)
{
unsigned short chipid0=0xdead, chipid1=0xbeef;
static char * const name = "lq_cpe_eth";
#ifdef CONFIG_SWITCH_PORT0
*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
#elif defined(CONFIG_SWITCH_PORT1)
*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
*DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
#endif
#ifdef CLK_OUT2_25MHZ
*DANUBE_GPIO_P0_DIR=0x0000ae78;
*DANUBE_GPIO_P0_ALTSEL0=0x00008078;
//joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
*DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
*DANUBE_CGU_IFCCR=0x00400010;
*DANUBE_GPIO_P0_OD=0x0000ae78;
#endif
/* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
udelay(100000);
debug("\nsearching for Samurai switch ... ");
if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) &&
(miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) {
if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) &&
((chipid1 & 0x000F) == ID_SAMURAI_1)) {
debug("found");
/* enable "Crossover Auto Detect" + defaults */
/* P0 */
miiphy_write(name, PHYADDR(0x01), 0x840F);
/* P1 */
miiphy_write(name, PHYADDR(0x03), 0x840F);
/* P2 */
miiphy_write(name, PHYADDR(0x05), 0x840F);
/* P3 */
miiphy_write(name, PHYADDR(0x07), 0x840F);
/* P4 */
miiphy_write(name, PHYADDR(0x08), 0x840F);
/* P5 */
miiphy_write(name, PHYADDR(0x09), 0x840F);
/* System Control 4: CPU on port 1 and other */
miiphy_write(name, PHYADDR(0x12), 0x3602);
#ifdef CLK_OUT2_25MHZ
/* Bandwidth Control Enable Register: enable */
miiphy_write(name, PHYADDR(0x33), 0x4000);
#endif
}
}
debug("\nsearching for TANTOS switch ... ");
if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) {
if (chipid0 == ID_TANTOS) {
debug("found");
/* P5 Basic Control: Force Link Up */
miiphy_write(name, PHYADDR(0xA1), 0x0004);
/* P6 Basic Control: Force Link Up */
miiphy_write(name, PHYADDR(0xC1), 0x0004);
/* RGMII/MII Port Control (P4/5/6) */
miiphy_write(name, PHYADDR(0xF5), 0x0773);
/* Software workaround. */
/* PHY reset from P0 to P4. */
/* set data for indirect write */
miiphy_write(name, PHYADDR(0x121), 0x8000);
/* P0 */
miiphy_write(name, PHYADDR(0x120), 0x0400);
udelay(1000);
/* P1 */
miiphy_write(name, PHYADDR(0x120), 0x0420);
udelay(1000);
/* P2 */
miiphy_write(name, PHYADDR(0x120), 0x0440);
udelay(1000);
/* P3 */
miiphy_write(name, PHYADDR(0x120), 0x0460);
udelay(1000);
/* P4 */
miiphy_write(name, PHYADDR(0x120), 0x0480);
udelay(1000);
}
}
debug("\n");
return 0;
}
#endif /* CONFIG_EXTRA_SWITCH */
int board_gpio_init(void)
{
#ifdef CONFIG_BUTTON_PORT0
*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
{
printf("button is pressed\n");
setenv("bootdelay", "0");
setenv("bootcmd", "httpd");
}
#elif defined(CONFIG_BUTTON_PORT1)
*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
*DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
{
printf("button is pressed\n");
setenv("bootdelay", "0");
setenv("bootcmd", "httpd");
}
#endif
}
int board_eth_init(bd_t *bis)
{
board_gpio_init();
#if defined(CONFIG_IFX_ETOP)
*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
if (lq_eth_initialize(bis)<0)
return -1;
*DANUBE_RCU_RST_REQ |=1;
udelay(200000);
*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
udelay(1000);
#ifdef CONFIG_EXTRA_SWITCH
if (external_switch_init()<0)
return -1;
#endif /* CONFIG_EXTRA_SWITCH */
#endif /* CONFIG_IFX_ETOP */
return 0;
}
#if defined(CONFIG_CMD_HTTPD)
int do_http_upgrade(const unsigned char *data, const ulong size)
{
char buf[128];
if(getenv ("ram_addr") == NULL)
return -1;
if(getenv ("kernel_addr") == NULL)
return -1;
/* check the image */
if(run_command("imi ${ram_addr}", 0) < 0) {
return -1;
}
/* write the image to the flash */
puts("http ugrade ...\n");
sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
return run_command(buf, 0);
}
int do_http_progress(const int state)
{
/* toggle LED's here */
switch(state) {
case HTTP_PROGRESS_START:
puts("http start\n");
break;
case HTTP_PROGRESS_TIMEOUT:
puts(".");
break;
case HTTP_PROGRESS_UPLOAD_READY:
puts("http upload ready\n");
break;
case HTTP_PROGRESS_UGRADE_READY:
puts("http ugrade ready\n");
break;
case HTTP_PROGRESS_UGRADE_FAILED:
puts("http ugrade failed\n");
break;
}
return 0;
}
unsigned long do_http_tmp_address(void)
{
char *s = getenv ("ram_addr");
if (s) {
ulong tmp = simple_strtoul (s, NULL, 16);
return tmp;
}
return 0 /*0x80a00000*/;
}
#endif

50
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA03
#define MC_DC21_VALUE 0x1d00
#define MC_DC22_VALUE 0x1d1d
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* was 0x7f */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

50
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_PROMOSDDR400.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xa02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x0
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1200
#define MC_DC22_VALUE 0x1212
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x4e20
#define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

51
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_Samsung_166.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1400
#define MC_DC22_VALUE 0x1414
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x4e /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d93
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

50
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e111.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1800
#define MC_DC22_VALUE 0x1818
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

50
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e166.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1800
#define MC_DC22_VALUE 0x1818
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

51
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1700
#define MC_DC22_VALUE 0x1717
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x4e20
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

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package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1200
#define MC_DC22_VALUE 0x1212
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

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package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r166.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0xd00
#define MC_DC22_VALUE 0xd0d
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

48
package/uboot-lantiq/files/board/infineon/easy50712/easy50712_bootstrap.c
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@ -1,48 +0,0 @@
/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2007
* Vlad Lungu vlad.lungu@windriver.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
phys_size_t bootstrap_initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return CONFIG_SYS_MAX_RAM;
}
int bootstrap_checkboard(void)
{
return 0;
}
int bootstrap_misc_init_r(void)
{
set_io_port_base(0);
return 0;
}

606
package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S
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@ -1,606 +0,0 @@
/*
* Memory sub-system initialization code for Danube board.
* Andre Messerschmidt
* Copyright (c) 2005 Infineon Technologies AG
*
* Based on Inca-IP code
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* History:
peng liu May 25, 2006, for PLL setting after reset, 05252006
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#if defined(CONFIG_USE_DDR_RAM)
#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
#include "ddr_settings_r111.h"
#define DDR111
#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
#include "ddr_settings_r166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
#include "ddr_settings_e111.h"
#define DDR111
#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
#include "ddr_settings_e166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
#include "ddr_settings_PROMOSDDR400.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
#include "ddr_settings_Samsung_166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
#include "ddr_settings_psc_166.h"
#define DDR166
#else
#warning "missing definition for ddr_settings.h, use default!"
#include "ddr_settings.h"
#endif
#endif /* CONFIG_USE_DDR_RAM */
#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
#error "missing include of ddr_settings.h"
#endif
#define EBU_MODUL_BASE 0xBE105300
#define EBU_CLC(value) 0x0000(value)
#define EBU_CON(value) 0x0010(value)
#define EBU_ADDSEL0(value) 0x0020(value)
#define EBU_ADDSEL1(value) 0x0024(value)
#define EBU_ADDSEL2(value) 0x0028(value)
#define EBU_ADDSEL3(value) 0x002C(value)
#define EBU_BUSCON0(value) 0x0060(value)
#define EBU_BUSCON1(value) 0x0064(value)
#define EBU_BUSCON2(value) 0x0068(value)
#define EBU_BUSCON3(value) 0x006C(value)
#define MC_MODUL_BASE 0xBF800000
#define MC_ERRCAUSE(value) 0x0010(value)
#define MC_ERRADDR(value) 0x0020(value)
#define MC_CON(value) 0x0060(value)
#define MC_SRAM_ENABLE 0x00000004
#define MC_SDRAM_ENABLE 0x00000002
#define MC_DDRRAM_ENABLE 0x00000001
#define MC_SDR_MODUL_BASE 0xBF800200
#define MC_IOGP(value) 0x0000(value)
#define MC_CTRLENA(value) 0x0010(value)
#define MC_MRSCODE(value) 0x0020(value)
#define MC_CFGDW(value) 0x0030(value)
#define MC_CFGPB0(value) 0x0040(value)
#define MC_LATENCY(value) 0x0080(value)
#define MC_TREFRESH(value) 0x0090(value)
#define MC_SELFRFSH(value) 0x00A0(value)
#define MC_DDR_MODUL_BASE 0xBF801000
#define MC_DC00(value) 0x0000(value)
#define MC_DC01(value) 0x0010(value)
#define MC_DC02(value) 0x0020(value)
#define MC_DC03(value) 0x0030(value)
#define MC_DC04(value) 0x0040(value)
#define MC_DC05(value) 0x0050(value)
#define MC_DC06(value) 0x0060(value)
#define MC_DC07(value) 0x0070(value)
#define MC_DC08(value) 0x0080(value)
#define MC_DC09(value) 0x0090(value)
#define MC_DC10(value) 0x00A0(value)
#define MC_DC11(value) 0x00B0(value)
#define MC_DC12(value) 0x00C0(value)
#define MC_DC13(value) 0x00D0(value)
#define MC_DC14(value) 0x00E0(value)
#define MC_DC15(value) 0x00F0(value)
#define MC_DC16(value) 0x0100(value)
#define MC_DC17(value) 0x0110(value)
#define MC_DC18(value) 0x0120(value)
#define MC_DC19(value) 0x0130(value)
#define MC_DC20(value) 0x0140(value)
#define MC_DC21(value) 0x0150(value)
#define MC_DC22(value) 0x0160(value)
#define MC_DC23(value) 0x0170(value)
#define MC_DC24(value) 0x0180(value)
#define MC_DC25(value) 0x0190(value)
#define MC_DC26(value) 0x01A0(value)
#define MC_DC27(value) 0x01B0(value)
#define MC_DC28(value) 0x01C0(value)
#define MC_DC29(value) 0x01D0(value)
#define MC_DC30(value) 0x01E0(value)
#define MC_DC31(value) 0x01F0(value)
#define MC_DC32(value) 0x0200(value)
#define MC_DC33(value) 0x0210(value)
#define MC_DC34(value) 0x0220(value)
#define MC_DC35(value) 0x0230(value)
#define MC_DC36(value) 0x0240(value)
#define MC_DC37(value) 0x0250(value)
#define MC_DC38(value) 0x0260(value)
#define MC_DC39(value) 0x0270(value)
#define MC_DC40(value) 0x0280(value)
#define MC_DC41(value) 0x0290(value)
#define MC_DC42(value) 0x02A0(value)
#define MC_DC43(value) 0x02B0(value)
#define MC_DC44(value) 0x02C0(value)
#define MC_DC45(value) 0x02D0(value)
#define MC_DC46(value) 0x02E0(value)
#define RCU_OFFSET 0xBF203000
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
#define RCU_STS (RCU_OFFSET + 0x0014)
#define CGU_OFFSET 0xBF103000
#define PLL0_CFG (CGU_OFFSET + 0x0004)
#define PLL1_CFG (CGU_OFFSET + 0x0008)
#define PLL2_CFG (CGU_OFFSET + 0x000C)
#define CGU_SYS (CGU_OFFSET + 0x0010)
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
#define IF_CLK (CGU_OFFSET + 0x0018)
#define CGU_SMD (CGU_OFFSET + 0x0020)
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
//05252006
#define pll0_35MHz_CONFIG 0x9D861059
#define pll1_35MHz_CONFIG 0x1A260CD9
#define pll2_35MHz_CONFIG 0x8000f1e5
#define pll0_36MHz_CONFIG 0x1000125D
#define pll1_36MHz_CONFIG 0x1B1E0C99
#define pll2_36MHz_CONFIG 0x8002f2a1
//05252006
//06063001-joelin disable the PCI CFRAME mask -start
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
*/
#define PCI_CR_PR_OFFSET 0xBE105400
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
#define PCI_CONFIG_SPACE 0xB7000000
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
//06063001-joelin disable the PCI CFRAME mask -end
.set noreorder
/*
* void ebu_init(void)
*/
.globl ebu_init
.ent ebu_init
ebu_init:
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
li t1, EBU_MODUL_BASE
#if defined(CONFIG_EBU_ADDSEL0)
li t2, CONFIG_EBU_ADDSEL0
sw t2, EBU_ADDSEL0(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL1)
li t2, CONFIG_EBU_ADDSEL1
sw t2, EBU_ADDSEL1(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL2)
li t2, CONFIG_EBU_ADDSEL2
sw t2, EBU_ADDSEL2(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL3)
li t2, CONFIG_EBU_ADDSEL3
sw t2, EBU_ADDSEL3(t1)
#endif
#if defined(CONFIG_EBU_BUSCON0)
li t2, CONFIG_EBU_BUSCON0
sw t2, EBU_BUSCON0(t1)
#endif
#if defined(CONFIG_EBU_BUSCON1)
li t2, CONFIG_EBU_BUSCON1
sw t2, EBU_BUSCON1(t1)
#endif
#if defined(CONFIG_EBU_BUSCON2)
li t2, CONFIG_EBU_BUSCON2
sw t2, EBU_BUSCON2(t1)
#endif
#if defined(CONFIG_EBU_BUSCON3)
li t2, CONFIG_EBU_BUSCON3
sw t2, EBU_BUSCON3(t1)
#endif
#endif
j ra
nop
.end ebu_init
/*
* void cgu_init(long)
*
* a0 has the clock value
*/
.globl cgu_init
.ent cgu_init
cgu_init:
li t2, CGU_SYS
lw t2,0(t2)
beq t2,a0,freq_up2date
nop
li t2, RCU_STS
lw t2, 0(t2)
and t2,0x00020000
beq t2,0x00020000,boot_36MHZ
nop
//05252006
li t1, PLL0_CFG
li t2, pll0_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_35MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
b wait_reset
nop
boot_36MHZ:
li t1, PLL0_CFG
li t2, pll0_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_36MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
//05252006
wait_reset:
b wait_reset
nop
freq_up2date:
j ra
nop
.end cgu_init
#ifndef CONFIG_USE_DDR_RAM
/*
* void sdram_init(long)
*
* a0 has the clock value
*/
.globl sdram_init
.ent sdram_init
sdram_init:
/* SDRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable SDRAM module in memory controller */
li t3, MC_SDRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_SDR_MODUL_BASE
/* disable the controller */
li t2, 0
sw t2, MC_CTRLENA(t1)
li t2, 0x822
sw t2, MC_IOGP(t1)
li t2, 0x2
sw t2, MC_CFGDW(t1)
/* Set CAS Latency */
li t2, 0x00000020
sw t2, MC_MRSCODE(t1)
/* Set CS0 to SDRAM parameters */
li t2, 0x000014d8
sw t2, MC_CFGPB0(t1)
/* Set SDRAM latency parameters */
li t2, 0x00036325; /* BC PC100 */
sw t2, MC_LATENCY(t1)
/* Set SDRAM refresh rate */
li t2, 0x00000C30
sw t2, MC_TREFRESH(t1)
/* Clear Power-down registers */
sw zero, MC_SELFRFSH(t1)
/* Finally enable the controller */
li t2, 1
sw t2, MC_CTRLENA(t1)
j ra
nop
.end sdram_init
#endif /* !CONFIG_USE_DDR_RAM */
#ifdef CONFIG_USE_DDR_RAM
/*
* void ddrram_init(long)
*
* a0 has the clock value
*/
.globl ddrram_init
.ent ddrram_init
ddrram_init:
/* DDR-DRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable DDR module in memory controller */
li t3, MC_DDRRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_DDR_MODUL_BASE
/* Write configuration to DDR controller registers */
li t2, MC_DC0_VALUE
sw t2, MC_DC00(t1)
li t2, MC_DC1_VALUE
sw t2, MC_DC01(t1)
li t2, MC_DC2_VALUE
sw t2, MC_DC02(t1)
li t2, MC_DC3_VALUE
sw t2, MC_DC03(t1)
li t2, MC_DC4_VALUE
sw t2, MC_DC04(t1)
li t2, MC_DC5_VALUE
sw t2, MC_DC05(t1)
li t2, MC_DC6_VALUE
sw t2, MC_DC06(t1)
li t2, MC_DC7_VALUE
sw t2, MC_DC07(t1)
li t2, MC_DC8_VALUE
sw t2, MC_DC08(t1)
li t2, MC_DC9_VALUE
sw t2, MC_DC09(t1)
li t2, MC_DC10_VALUE
sw t2, MC_DC10(t1)
li t2, MC_DC11_VALUE
sw t2, MC_DC11(t1)
li t2, MC_DC12_VALUE
sw t2, MC_DC12(t1)
li t2, MC_DC13_VALUE
sw t2, MC_DC13(t1)
li t2, MC_DC14_VALUE
sw t2, MC_DC14(t1)
li t2, MC_DC15_VALUE
sw t2, MC_DC15(t1)
li t2, MC_DC16_VALUE
sw t2, MC_DC16(t1)
li t2, MC_DC17_VALUE
sw t2, MC_DC17(t1)
li t2, MC_DC18_VALUE
sw t2, MC_DC18(t1)
li t2, MC_DC19_VALUE
sw t2, MC_DC19(t1)
li t2, MC_DC20_VALUE
sw t2, MC_DC20(t1)
li t2, MC_DC21_VALUE
sw t2, MC_DC21(t1)
li t2, MC_DC22_VALUE
sw t2, MC_DC22(t1)
li t2, MC_DC23_VALUE
sw t2, MC_DC23(t1)
li t2, MC_DC24_VALUE
sw t2, MC_DC24(t1)
li t2, MC_DC25_VALUE
sw t2, MC_DC25(t1)
li t2, MC_DC26_VALUE
sw t2, MC_DC26(t1)
li t2, MC_DC27_VALUE
sw t2, MC_DC27(t1)
li t2, MC_DC28_VALUE
sw t2, MC_DC28(t1)
li t2, MC_DC29_VALUE
sw t2, MC_DC29(t1)
li t2, MC_DC30_VALUE
sw t2, MC_DC30(t1)
li t2, MC_DC31_VALUE
sw t2, MC_DC31(t1)
li t2, MC_DC32_VALUE
sw t2, MC_DC32(t1)
li t2, MC_DC33_VALUE
sw t2, MC_DC33(t1)
li t2, MC_DC34_VALUE
sw t2, MC_DC34(t1)
li t2, MC_DC35_VALUE
sw t2, MC_DC35(t1)
li t2, MC_DC36_VALUE
sw t2, MC_DC36(t1)
li t2, MC_DC37_VALUE
sw t2, MC_DC37(t1)
li t2, MC_DC38_VALUE
sw t2, MC_DC38(t1)
li t2, MC_DC39_VALUE
sw t2, MC_DC39(t1)
li t2, MC_DC40_VALUE
sw t2, MC_DC40(t1)
li t2, MC_DC41_VALUE
sw t2, MC_DC41(t1)
li t2, MC_DC42_VALUE
sw t2, MC_DC42(t1)
li t2, MC_DC43_VALUE
sw t2, MC_DC43(t1)
li t2, MC_DC44_VALUE
sw t2, MC_DC44(t1)
li t2, MC_DC45_VALUE
sw t2, MC_DC45(t1)
li t2, MC_DC46_VALUE
sw t2, MC_DC46(t1)
li t2, 0x00000100
sw t2, MC_DC03(t1)
j ra
nop
.end ddrram_init
#endif /* CONFIG_USE_DDR_RAM */
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
*/
move t0, ra
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
#if defined(DDR166)
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
li a0,0xe8
#elif defined(DDR133)
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
li a0,0xe9
#else /* defined(DDR111) */
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
li a0,0xea
#endif
bal cgu_init
nop
bal ebu_init
nop
//06063001-joelin disable the PCI CFRAME mask-start
#ifdef DISABLE_CFRAME
li t1, PCI_CR_PCI //mw bf103034 80000000
li t2, 0x80000000
sw t2,0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x103
sw t2,0(t1)
li t1, CS_CFM //mw b700006c 0
li t2, 0x00
sw t2, 0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x1000103
sw t2, 0(t1)
#endif
//06063001-joelin disable the PCI CFRAME mask-end
#ifdef CONFIG_USE_DDR_RAM
bal ddrram_init
nop
#else
bal sdram_init
nop
#endif
move ra, t0
j ra
nop
.end lowlevel_init

613
package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_init.S
View File

@ -1,613 +0,0 @@
/*
* Memory sub-system initialization code for Danube board.
* Andre Messerschmidt
* Copyright (c) 2005 Infineon Technologies AG
*
* Based on Inca-IP code
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* History:
peng liu May 25, 2006, for PLL setting after reset, 05252006
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#if defined(CONFIG_USE_DDR_RAM)
#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
#include "ddr_settings_r111.h"
#define DDR111
#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
#include "ddr_settings_r166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
#include "ddr_settings_e111.h"
#define DDR111
#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
#include "ddr_settings_e166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
#include "ddr_settings_PROMOSDDR400.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
#include "ddr_settings_Samsung_166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
#include "ddr_settings_psc_166.h"
#define DDR166
#else
#warning "missing definition for ddr_settings.h, use default!"
#include "ddr_settings.h"
#endif
#endif /* CONFIG_USE_DDR_RAM */
#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
#error "missing include of ddr_settings.h"
#endif
#define EBU_MODUL_BASE 0xBE105300
#define EBU_CLC(value) 0x0000(value)
#define EBU_CON(value) 0x0010(value)
#define EBU_ADDSEL0(value) 0x0020(value)
#define EBU_ADDSEL1(value) 0x0024(value)
#define EBU_ADDSEL2(value) 0x0028(value)
#define EBU_ADDSEL3(value) 0x002C(value)
#define EBU_BUSCON0(value) 0x0060(value)
#define EBU_BUSCON1(value) 0x0064(value)
#define EBU_BUSCON2(value) 0x0068(value)
#define EBU_BUSCON3(value) 0x006C(value)
#define MC_MODUL_BASE 0xBF800000
#define MC_ERRCAUSE(value) 0x0010(value)
#define MC_ERRADDR(value) 0x0020(value)
#define MC_CON(value) 0x0060(value)
#define MC_SRAM_ENABLE 0x00000004
#define MC_SDRAM_ENABLE 0x00000002
#define MC_DDRRAM_ENABLE 0x00000001
#define MC_SDR_MODUL_BASE 0xBF800200
#define MC_IOGP(value) 0x0000(value)
#define MC_CTRLENA(value) 0x0010(value)
#define MC_MRSCODE(value) 0x0020(value)
#define MC_CFGDW(value) 0x0030(value)
#define MC_CFGPB0(value) 0x0040(value)
#define MC_LATENCY(value) 0x0080(value)
#define MC_TREFRESH(value) 0x0090(value)
#define MC_SELFRFSH(value) 0x00A0(value)
#define MC_DDR_MODUL_BASE 0xBF801000
#define MC_DC00(value) 0x0000(value)
#define MC_DC01(value) 0x0010(value)
#define MC_DC02(value) 0x0020(value)
#define MC_DC03(value) 0x0030(value)
#define MC_DC04(value) 0x0040(value)
#define MC_DC05(value) 0x0050(value)
#define MC_DC06(value) 0x0060(value)
#define MC_DC07(value) 0x0070(value)
#define MC_DC08(value) 0x0080(value)
#define MC_DC09(value) 0x0090(value)
#define MC_DC10(value) 0x00A0(value)
#define MC_DC11(value) 0x00B0(value)
#define MC_DC12(value) 0x00C0(value)
#define MC_DC13(value) 0x00D0(value)
#define MC_DC14(value) 0x00E0(value)
#define MC_DC15(value) 0x00F0(value)
#define MC_DC16(value) 0x0100(value)
#define MC_DC17(value) 0x0110(value)
#define MC_DC18(value) 0x0120(value)
#define MC_DC19(value) 0x0130(value)
#define MC_DC20(value) 0x0140(value)
#define MC_DC21(value) 0x0150(value)
#define MC_DC22(value) 0x0160(value)
#define MC_DC23(value) 0x0170(value)
#define MC_DC24(value) 0x0180(value)
#define MC_DC25(value) 0x0190(value)
#define MC_DC26(value) 0x01A0(value)
#define MC_DC27(value) 0x01B0(value)
#define MC_DC28(value) 0x01C0(value)
#define MC_DC29(value) 0x01D0(value)
#define MC_DC30(value) 0x01E0(value)
#define MC_DC31(value) 0x01F0(value)
#define MC_DC32(value) 0x0200(value)
#define MC_DC33(value) 0x0210(value)
#define MC_DC34(value) 0x0220(value)
#define MC_DC35(value) 0x0230(value)
#define MC_DC36(value) 0x0240(value)
#define MC_DC37(value) 0x0250(value)
#define MC_DC38(value) 0x0260(value)
#define MC_DC39(value) 0x0270(value)
#define MC_DC40(value) 0x0280(value)
#define MC_DC41(value) 0x0290(value)
#define MC_DC42(value) 0x02A0(value)
#define MC_DC43(value) 0x02B0(value)
#define MC_DC44(value) 0x02C0(value)
#define MC_DC45(value) 0x02D0(value)
#define MC_DC46(value) 0x02E0(value)
#define RCU_OFFSET 0xBF203000
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
#define RCU_STS (RCU_OFFSET + 0x0014)
#define CGU_OFFSET 0xBF103000
#define PLL0_CFG (CGU_OFFSET + 0x0004)
#define PLL1_CFG (CGU_OFFSET + 0x0008)
#define PLL2_CFG (CGU_OFFSET + 0x000C)
#define CGU_SYS (CGU_OFFSET + 0x0010)
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
#define IF_CLK (CGU_OFFSET + 0x0018)
#define CGU_SMD (CGU_OFFSET + 0x0020)
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
//05252006
#define pll0_35MHz_CONFIG 0x9D861059
#define pll1_35MHz_CONFIG 0x1A260CD9
#define pll2_35MHz_CONFIG 0x8000f1e5
#define pll0_36MHz_CONFIG 0x1000125D
#define pll1_36MHz_CONFIG 0x1B1E0C99
#define pll2_36MHz_CONFIG 0x8002f2a1
//05252006
//06063001-joelin disable the PCI CFRAME mask -start
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
*/
#define PCI_CR_PR_OFFSET 0xBE105400
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
#define PCI_CONFIG_SPACE 0xB7000000
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
//06063001-joelin disable the PCI CFRAME mask -end
.set noreorder
/*
* void ebu_init(void)
*/
.globl ebu_init
.ent ebu_init
ebu_init:
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
li t1, EBU_MODUL_BASE
#if defined(CONFIG_EBU_ADDSEL0)
li t2, CONFIG_EBU_ADDSEL0
sw t2, EBU_ADDSEL0(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL1)
li t2, CONFIG_EBU_ADDSEL1
sw t2, EBU_ADDSEL1(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL2)
li t2, CONFIG_EBU_ADDSEL2
sw t2, EBU_ADDSEL2(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL3)
li t2, CONFIG_EBU_ADDSEL3
sw t2, EBU_ADDSEL3(t1)
#endif
#if defined(CONFIG_EBU_BUSCON0)
li t2, CONFIG_EBU_BUSCON0
sw t2, EBU_BUSCON0(t1)
#endif
#if defined(CONFIG_EBU_BUSCON1)
li t2, CONFIG_EBU_BUSCON1
sw t2, EBU_BUSCON1(t1)
#endif
#if defined(CONFIG_EBU_BUSCON2)
li t2, CONFIG_EBU_BUSCON2
sw t2, EBU_BUSCON2(t1)
#endif
#if defined(CONFIG_EBU_BUSCON3)
li t2, CONFIG_EBU_BUSCON3
sw t2, EBU_BUSCON3(t1)
#endif
#endif
j ra
nop
.end ebu_init
/*
* void cgu_init(long)
*
* a0 has the clock value
*/
.globl cgu_init
.ent cgu_init
cgu_init:
li t2, CGU_SYS
lw t2,0(t2)
beq t2,a0,freq_up2date
nop
li t2, RCU_STS
lw t2, 0(t2)
and t2,0x00020000
beq t2,0x00020000,boot_36MHZ
nop
//05252006
li t1, PLL0_CFG
li t2, pll0_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_35MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
b wait_reset
nop
boot_36MHZ:
li t1, PLL0_CFG
li t2, pll0_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_36MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
//05252006
wait_reset:
b wait_reset
nop
freq_up2date:
j ra
nop
.end cgu_init
#ifndef CONFIG_USE_DDR_RAM
/*
* void sdram_init(long)
*
* a0 has the clock value
*/
.globl sdram_init
.ent sdram_init
sdram_init:
/* SDRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable SDRAM module in memory controller */
li t3, MC_SDRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_SDR_MODUL_BASE
/* disable the controller */
li t2, 0
sw t2, MC_CTRLENA(t1)
li t2, 0x822
sw t2, MC_IOGP(t1)
li t2, 0x2
sw t2, MC_CFGDW(t1)
/* Set CAS Latency */
li t2, 0x00000020
sw t2, MC_MRSCODE(t1)
/* Set CS0 to SDRAM parameters */
li t2, 0x000014d8
sw t2, MC_CFGPB0(t1)
/* Set SDRAM latency parameters */
li t2, 0x00036325; /* BC PC100 */
sw t2, MC_LATENCY(t1)
/* Set SDRAM refresh rate */
li t2, 0x00000C30
sw t2, MC_TREFRESH(t1)
/* Clear Power-down registers */
sw zero, MC_SELFRFSH(t1)
/* Finally enable the controller */
li t2, 1
sw t2, MC_CTRLENA(t1)
j ra
nop
.end sdram_init
#endif /* !CONFIG_USE_DDR_RAM */
#ifdef CONFIG_USE_DDR_RAM
/*
* void ddrram_init(long)
*
* a0 has the clock value
*/
.globl ddrram_init
.ent ddrram_init
ddrram_init:
/* DDR-DRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable DDR module in memory controller */
li t3, MC_DDRRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_DDR_MODUL_BASE
/* Write configuration to DDR controller registers */
li t2, MC_DC0_VALUE
sw t2, MC_DC00(t1)
li t2, MC_DC1_VALUE
sw t2, MC_DC01(t1)
li t2, MC_DC2_VALUE
sw t2, MC_DC02(t1)
li t2, MC_DC3_VALUE
sw t2, MC_DC03(t1)
li t2, MC_DC4_VALUE
sw t2, MC_DC04(t1)
li t2, MC_DC5_VALUE
sw t2, MC_DC05(t1)
li t2, MC_DC6_VALUE
sw t2, MC_DC06(t1)
li t2, MC_DC7_VALUE
sw t2, MC_DC07(t1)
li t2, MC_DC8_VALUE
sw t2, MC_DC08(t1)
li t2, MC_DC9_VALUE
sw t2, MC_DC09(t1)
li t2, MC_DC10_VALUE
sw t2, MC_DC10(t1)
li t2, MC_DC11_VALUE
sw t2, MC_DC11(t1)
li t2, MC_DC12_VALUE
sw t2, MC_DC12(t1)
li t2, MC_DC13_VALUE
sw t2, MC_DC13(t1)
li t2, MC_DC14_VALUE
sw t2, MC_DC14(t1)
li t2, MC_DC15_VALUE
sw t2, MC_DC15(t1)
li t2, MC_DC16_VALUE
sw t2, MC_DC16(t1)
li t2, MC_DC17_VALUE
sw t2, MC_DC17(t1)
li t2, MC_DC18_VALUE
sw t2, MC_DC18(t1)
li t2, MC_DC19_VALUE
sw t2, MC_DC19(t1)
li t2, MC_DC20_VALUE
sw t2, MC_DC20(t1)
li t2, MC_DC21_VALUE
sw t2, MC_DC21(t1)
li t2, MC_DC22_VALUE
sw t2, MC_DC22(t1)
li t2, MC_DC23_VALUE
sw t2, MC_DC23(t1)
li t2, MC_DC24_VALUE
sw t2, MC_DC24(t1)
li t2, MC_DC25_VALUE
sw t2, MC_DC25(t1)
li t2, MC_DC26_VALUE
sw t2, MC_DC26(t1)
li t2, MC_DC27_VALUE
sw t2, MC_DC27(t1)
li t2, MC_DC28_VALUE
sw t2, MC_DC28(t1)
li t2, MC_DC29_VALUE
sw t2, MC_DC29(t1)
li t2, MC_DC30_VALUE
sw t2, MC_DC30(t1)
li t2, MC_DC31_VALUE
sw t2, MC_DC31(t1)
li t2, MC_DC32_VALUE
sw t2, MC_DC32(t1)
li t2, MC_DC33_VALUE
sw t2, MC_DC33(t1)
li t2, MC_DC34_VALUE
sw t2, MC_DC34(t1)
li t2, MC_DC35_VALUE
sw t2, MC_DC35(t1)
li t2, MC_DC36_VALUE
sw t2, MC_DC36(t1)
li t2, MC_DC37_VALUE
sw t2, MC_DC37(t1)
li t2, MC_DC38_VALUE
sw t2, MC_DC38(t1)
li t2, MC_DC39_VALUE
sw t2, MC_DC39(t1)
li t2, MC_DC40_VALUE
sw t2, MC_DC40(t1)
li t2, MC_DC41_VALUE
sw t2, MC_DC41(t1)
li t2, MC_DC42_VALUE
sw t2, MC_DC42(t1)
li t2, MC_DC43_VALUE
sw t2, MC_DC43(t1)
li t2, MC_DC44_VALUE
sw t2, MC_DC44(t1)
li t2, MC_DC45_VALUE
sw t2, MC_DC45(t1)
li t2, MC_DC46_VALUE
sw t2, MC_DC46(t1)
li t2, 0x00000100
sw t2, MC_DC03(t1)
j ra
nop
.end ddrram_init
#endif /* CONFIG_USE_DDR_RAM */
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
*/
move t0, ra
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
#if defined(CONFIG_SYS_EBU_BOOT)
#if defined(DDR166)
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
li a0,0xe8
#elif defined(DDR133)
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
li a0,0xe9
#else /* defined(DDR111) */
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
li a0,0xea
#endif
bal cgu_init
nop
#endif /* CONFIG_SYS_EBU_BOOT */
bal ebu_init
nop
//06063001-joelin disable the PCI CFRAME mask-start
#ifdef DISABLE_CFRAME
li t1, PCI_CR_PCI //mw bf103034 80000000
li t2, 0x80000000
sw t2,0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x103
sw t2,0(t1)
li t1, CS_CFM //mw b700006c 0
li t2, 0x00
sw t2, 0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x1000103
sw t2, 0(t1)
#endif
//06063001-joelin disable the PCI CFRAME mask-end
#ifdef CONFIG_SYS_EBU_BOOT
#ifndef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_USE_DDR_RAM
bal ddrram_init
nop
#else
bal sdram_init
nop
#endif
#endif /* CONFIG_SYS_RAMBOOT */
#endif /* CONFIG_SYS_EBU_BOOT */
move ra, t0
j ra
nop
.end lowlevel_init

48
package/uboot-lantiq/files/board/infineon/easy50712/pmuenable.S
View File

@ -1,48 +0,0 @@
/*
* Power Management unit initialization code for AMAZON development board.
*
* Copyright (c) 2003 Ou Ke, Infineon.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#define PMU_PWDCR 0xBF10201C
#define PMU_SR 0xBF102020
.globl pmuenable
pmuenable:
li t0, PMU_PWDCR
li t1, 0x2 /* enable everything */
sw t1, 0(t0)
#if 0
1:
li t0, PMU_SR
lw t2, 0(t0)
bne t1, t2, 1b
nop
#endif
j ra
nop

74
package/uboot-lantiq/files/board/infineon/easy50712/u-boot-bootstrap.lds
View File

@ -1,74 +0,0 @@
/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = .;
_gp = ALIGN(16) +0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
. = ALIGN(4);
.sdata : { *(.sdata) }
. = .;
. = ALIGN(4);
.payload : { *(.payload) }
. = ALIGN(4);
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}

70
package/uboot-lantiq/files/board/infineon/easy50712/u-boot.lds
View File

@ -1,70 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}

62
package/uboot-lantiq/files/board/infineon/easy50812/Makefile
View File

@ -1,62 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
COBJS-y += ar9.o
SOBJS = lowlevel_init.o pmuenable.o
BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

619
package/uboot-lantiq/files/board/infineon/easy50812/ar9.c
View File

@ -1,619 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Thomas Langer, Ralph Hempel
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/addrspace.h>
#include <asm/ar9.h>
#include <asm/reboot.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_HTTPD)
#include <httpd.h>
#endif
extern ulong ifx_get_ddr_hz(void);
extern ulong ifx_get_cpuclk(void);
/* definitions for external PHYs / Switches */
/* Split values into phy address and register address */
#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
/* IDs and registers of known external switches */
#define ID_SAMURAI_0 0x1020
#define ID_SAMURAI_1 0x0007
#define SAMURAI_ID_REG0 0xA0
#define SAMURAI_ID_REG1 0xA1
#define ID_TANTOS 0x2599
#define RGMII_MODE 0
#define MII_MODE 1
#define REV_MII_MODE 2
#define RED_MII_MODE_IC 3 /*Input clock */
#define RGMII_MODE_100MB 4
#define TURBO_REV_MII_MODE 6 /*Turbo Rev Mii mode */
#define RED_MII_MODE_OC 7 /*Output clock */
#define RGMII_MODE_10MB 8
#define mdelay(n) udelay((n)*1000)
static void ar9_sw_chip_init(u8 port, u8 mode);
static void ar9_enable_sw_port(u8 port, u8 state);
static void ar9_configure_sw_port(u8 port, u8 mode);
static u16 ar9_smi_reg_read(u16 reg);
static u16 ar9_smi_reg_write(u16 reg, u16 data);
static char * const name = "lq_cpe_eth";
static int external_switch_init(void);
void _machine_restart(void)
{
*AR9_RCU_RST_REQ |= AR9_RST_ALL;
}
#ifdef CONFIG_SYS_RAMBOOT
phys_size_t initdram(int board_type)
{
return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
}
#elif defined(CONFIG_USE_DDR_RAM)
phys_size_t initdram(int board_type)
{
return (CONFIG_SYS_MAX_RAM);
}
#else
static ulong max_sdram_size(void) /* per Chip Select */
{
/* The only supported SDRAM data width is 16bit.
*/
#define CFG_DW 4
/* The only supported number of SDRAM banks is 4.
*/
#define CFG_NB 4
ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0;
int cols = cfgpb0 & 0xF;
int rows = (cfgpb0 & 0xF0) >> 4;
ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
return size;
}
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*/
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
phys_size_t initdram(int board_type)
{
int rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0;
ulong size, max_size = 0;
ulong our_address;
/* load t9 into our_address */
asm volatile ("move %0, $25" : "=r" (our_address) :);
/* Can't probe for RAM size unless we are running from Flash.
* find out whether running from DRAM or Flash.
*/
if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
{
return max_sdram_size();
}
for (cols = 0x8; cols <= 0xC; cols++)
{
for (rows = 0xB; rows <= 0xD; rows++)
{
*AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) |
(rows << 4) | cols;
size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
max_sdram_size());
if (size > max_size)
{
best_val = *AR9_SDRAM_MC_CFGPB0;
max_size = size;
}
}
}
*AR9_SDRAM_MC_CFGPB0 = best_val;
return max_size;
}
#endif
int checkboard (void)
{
unsigned long chipid = *AR9_MPS_CHIPID;
int part_num;
puts ("Board: ");
part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid);
switch (part_num)
{
case 0x16C:
puts("ARX188 ");
break;
case 0x16D:
puts("ARX168 ");
break;
case 0x16F:
puts("ARX182 ");
break;
case 0x170:
puts("GRX188 ");
break;
case 0x171:
puts("GRX168 ");
break;
default:
printf ("unknown, chip part number 0x%03X ", part_num);
break;
}
printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid));
printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
return 0;
}
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
int board_early_init_f(void)
{
#ifdef CONFIG_EBU_ADDSEL0
(*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
#endif
#ifdef CONFIG_EBU_ADDSEL1
(*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
#endif
#ifdef CONFIG_EBU_ADDSEL2
(*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
#endif
#ifdef CONFIG_EBU_ADDSEL3
(*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
#endif
#ifdef CONFIG_EBU_BUSCON0
(*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
#endif
#ifdef CONFIG_EBU_BUSCON1
(*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
#endif
#ifdef CONFIG_EBU_BUSCON2
(*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
#endif
#ifdef CONFIG_EBU_BUSCON3
(*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
#endif
return 0;
}
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_IFX_ETOP)
*AR9_PMU_PWDCR &= 0xFFFFEFDF;
*AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */
if (lq_eth_initialize(bis) < 0)
return -1;
*AR9_RCU_RST_REQ |= 1;
udelay(200000);
*AR9_RCU_RST_REQ &= (unsigned long)~1;
udelay(1000);
#ifdef CONFIG_EXTRA_SWITCH
if (external_switch_init()<0)
return -1;
#endif /* CONFIG_EXTRA_SWITCH */
#endif /* CONFIG_IFX_ETOP */
return 0;
}
static void ar9_configure_sw_port(u8 port, u8 mode)
{
if(port)
{
if (mode == 1) //MII mode
{
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000;
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000;
}
else if(mode == 2 || mode == 6) //Rev Mii mode
{
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000;
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000;
}
}
else //Port 0
{
if (mode == 1) //MII mode
{
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100;
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100;
}
else if(mode ==2 || mode ==6) //Rev Mii mode
{
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100;
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203;
}
}
}
/*
Call this function to place either MAC port 0 or 1 into working mode.
Parameters:
port - select ports 0 or 1.
state of interface : state
0: RGMII
1: MII
2: Rev MII
3: Reduce MII (input clock)
4: RGMII 100mb
5: Reserve
6: Turbo Rev MII
7: Reduce MII (output clock)
*/
void ar9_enable_sw_port(u8 port, u8 state)
{
REG32(AR9_SW_GCTL0) |= 0x80000000;
if (port == 0)
{
REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ;
//#if AR9_REFBOARD_TANTOS
REG32(0xbf20302c) &= 0xffff81ff;
REG32(0xbf20302c) |= 4<<9 ;
//#endif
REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8;
if((state &0x3) == 0)
{
REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3;
if(state == 4)
REG32(AR9_SW_RGMII_CTL) |= 0x4;
else
REG32(AR9_SW_RGMII_CTL) |= 0x8;
}
if(state == 6)
REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20));
if(state == 7)
REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21));
}
// *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe;
else
{
REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ;
REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18;
if((state &0x3) == 0)
{
REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff;
if(state == 4)
REG32(AR9_SW_RGMII_CTL) |= 0x1000;
else
REG32(AR9_SW_RGMII_CTL) |= 0x2000;
}
if(state == 6)
REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22));
if(state == 7)
REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23));
}
}
void pci_reset(void)
{
int i,j;
#define AR9_V1_PCI_RST_FIX 1
#if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST
*AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8;
*AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8;
*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8;
*AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8;
*AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8;
*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000;
*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000;
*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000;
*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000;
for(j=0;j<5;j++) {
*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000;
for(i=0;i<0x10000;i++);
*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000;
for(i=0;i<0x10000;i++);
}
*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR & ~0x4000;
*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR & ~0x8;
#endif
}
static u16 ar9_smi_reg_read(u16 reg)
{
int i;
while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/
for(i=0;i<0x3fff;i++);
udelay(50);
while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
return((u16) (REG32(AR9_SW_MDIO_DATA)));
}
static u16 ar9_smi_reg_write(u16 reg, u16 data)
{
int i;
while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/
for(i=0;i<0x3fff;i++);
udelay(50);
return 0;
}
static void ar9_sw_chip_init(u8 port, u8 mode)
{
int i;
u16 chipid;
debug("\nsearching for switches ... ");
asm("sync");
pci_reset();
/* 25mhz clock out */
*AR9_CGU_IFCCR &= ~(3<<10);
*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3);
*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3);
*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | (1<<3);
*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3);
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0);
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0);
*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | (1<<0);
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0);
*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ;
*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH));
*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P);
*AR9_GPIO_P2_OUT &= ~(1<<0);
asm("sync");
ar9_configure_sw_port(port, mode);
ar9_enable_sw_port(port, mode);
REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */
asm("sync");
/*GPIO 55(P3.7) used as output, set high*/
*AR9_GPIO_P3_OD |=(1<<7);
*AR9_GPIO_P3_DIR |= (1<<7);
*AR9_GPIO_P3_ALTSEL0 &=~(1<<7);
*AR9_GPIO_P3_ALTSEL1 &=~(1<<7);
asm("sync");
udelay(10);
*AR9_GPIO_P3_OUT &= ~(1<<7);
for(i=0;i<1000;i++)
udelay(110);
*AR9_GPIO_P3_OUT |=(1<<7);
udelay(100);
if(port==0)
REG32(AR9_SW_P0_CTL) |= 0x40001;
else
REG32(AR9_SW_P1_CTL) |= 0x40001;
REG32(AR9_SW_P2_CTL) |= 0x40001;
REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00);
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00);
*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | 0xc00;
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00;
asm("sync");
chipid = (unsigned short)(ar9_smi_reg_read(0x101));
printf("\nswitch chip id=%08x\n",chipid);
if (chipid != ID_TANTOS) {
debug("whatever detected\n");
ar9_smi_reg_write(0x1,0x840f);
ar9_smi_reg_write(0x3,0x840f);
ar9_smi_reg_write(0x5,0x840f);
ar9_smi_reg_write(0x7,0x840f);
ar9_smi_reg_write(0x8,0x840f);
ar9_smi_reg_write(0x12,0x3602);
#ifdef CLK_OUT2_25MHZ
ar9_smi_reg_write(0x33,0x4000);
#endif
} else { // Tantos switch ship
debug("Tantos switch detected\n");
ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/
ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/
ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/
/*port 5 duplex mode, flow control enable, 1000Mbit/s*/
/*port 6 duplex mode, flow control enable, 1000Mbit/s*/
}
asm("sync");
/*reset GPHY*/
mdelay(200);
*AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ;
udelay(50);
*AR9_GPIO_P2_OUT |= (1<<0);
}
static void ar9_dma_init(void)
{
/* select port */
*AR9_DMA_PS = 0;
/*
TXWGT 14:12 rw Port Weight for Transmit Direction (the default value “001”)
TXENDI 11:10 rw Endianness for Transmit Direction
Determine a byte swap between memory interface (left hand side) and
peripheral interface (right hand side).
00B B0_B1_B2_B3 No byte switching
01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
RXENDI 9:8 rw Endianness for Receive Direction
Determine a byte swap between peripheral (left hand side) and memory
interface (right hand side).
00B B0_B1_B2_B3 No byte switching
01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0
TXBL 5:4 rw Burst Length for Transmit Direction
Selects burst length for TX direction.
Others are reserved and will result in 2_WORDS burst length.
01B 2_WORDS 2 words
10B 4_WORDS 4 words
11B 8_WORDS 8 words
RXBL 3:2 rw Burst Length for Receive Direction
Selects burst length for RX direction.
Others are reserved and will result in 2_WORDS burst length.
01B 2_WORDS 2 words
10B 4_WORDS 4 words
11B 8_WORDS 8 words
*/
*AR9_DMA_PCTRL = 0x1f28;
}
#ifdef CONFIG_EXTRA_SWITCH
static int external_switch_init(void)
{
ar9_sw_chip_init(0, RGMII_MODE);
ar9_dma_init();
return 0;
}
#endif /* CONFIG_EXTRA_SWITCH */
#if defined(CONFIG_CMD_HTTPD)
int do_http_upgrade(const unsigned char *data, const ulong size)
{
char buf[128];
if(getenv ("ram_addr") == NULL)
return -1;
if(getenv ("kernel_addr") == NULL)
return -1;
/* check the image */
if(run_command("imi ${ram_addr}", 0) < 0) {
return -1;
}
/* write the image to the flash */
puts("http ugrade ...\n");
sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
return run_command(buf, 0);
}
int do_http_progress(const int state)
{
/* toggle LED's here */
switch(state) {
case HTTP_PROGRESS_START:
puts("http start\n");
break;
case HTTP_PROGRESS_TIMEOUT:
puts(".");
break;
case HTTP_PROGRESS_UPLOAD_READY:
puts("http upload ready\n");
break;
case HTTP_PROGRESS_UGRADE_READY:
puts("http ugrade ready\n");
break;
case HTTP_PROGRESS_UGRADE_FAILED:
puts("http ugrade failed\n");
break;
}
return 0;
}
unsigned long do_http_tmp_address(void)
{
char *s = getenv ("ram_addr");
if (s) {
ulong tmp = simple_strtoul (s, NULL, 16);
return tmp;
}
return 0 /*0x80a00000*/;
}
#endif

51
package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h
View File

@ -1,51 +0,0 @@
/* Settings for Denali DDR SDRAM controller */
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x306
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x139 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0x2200
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1800
#define MC_DC22_VALUE 0x1818
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x514
#define MC_DC29_VALUE 0x2d93
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x600
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

51
package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h
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@ -1,51 +0,0 @@
/* Settings for Denali DDR SDRAM controller */
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x306
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x13f /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0x2200
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1600
#define MC_DC22_VALUE 0x1616
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5d /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x514
#define MC_DC29_VALUE 0x2d93
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x600
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

51
package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
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@ -1,51 +0,0 @@
/* Settings for Denali DDR SDRAM controller */
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x306
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x80B
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xD02
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xF
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1200
#define MC_DC22_VALUE 0x1212
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x5FB
#define MC_DC29_VALUE 0x35DF
#define MC_DC30_VALUE 0x99E9
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x600
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

51
package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h
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@ -1,51 +0,0 @@
/* Settings for Denali DDR SDRAM controller */
/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x306
#define MC_DC7_VALUE 0x403
#define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x90c
#define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xf02
#define MC_DC12_VALUE 0x2c8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x12f /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xc800
#define MC_DC17_VALUE 0xf
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1500
#define MC_DC22_VALUE 0x1515
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x57 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x6b8
#define MC_DC29_VALUE 0x3c84
#define MC_DC30_VALUE 0xace5
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x600
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

51
package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h
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/* Settings for Denali DDR SDRAM controller */
/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x306
#define MC_DC7_VALUE 0x403
#define MC_DC8_VALUE 0x103
#define MC_DC9_VALUE 0xb0e
#define MC_DC10_VALUE 0x204
#define MC_DC11_VALUE 0x1102
#define MC_DC12_VALUE 0x2c8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x155 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xc800
#define MC_DC17_VALUE 0x13
#define MC_DC18_VALUE 0x401
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0xc00
#define MC_DC22_VALUE 0xc0c
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x74 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x798
#define MC_DC29_VALUE 0x445d
#define MC_DC30_VALUE 0xc351
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x600
//#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0

40
package/uboot-lantiq/files/board/infineon/easy50812/config.mk
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@ -1,40 +0,0 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Danube board with MIPS 24Kc CPU core
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifdef CONFIG_BOOTSTRAP
TEXT_BASE = 0x80001000
CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
CONFIG_SYS_RAMBOOT = y
else
ifndef TEXT_BASE
$(info redefine TEXT_BASE = 0xB0000000 )
TEXT_BASE = 0xB0000000
endif
endif

48
package/uboot-lantiq/files/board/infineon/easy50812/easy50812_bootstrap.c
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/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2007
* Vlad Lungu vlad.lungu@windriver.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
phys_size_t bootstrap_initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return CONFIG_SYS_MAX_RAM;
}
int bootstrap_checkboard(void)
{
return 0;
}
int bootstrap_misc_init_r(void)
{
set_io_port_base(0);
return 0;
}

597
package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S
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@ -1,597 +0,0 @@
/*
* Memory sub-system initialization code for Danube board.
* Andre Messerschmidt
* Copyright (c) 2005 Infineon Technologies AG
*
* Based on Inca-IP code
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* History:
peng liu May 25, 2006, for PLL setting after reset, 05252006
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#if defined(CONFIG_USE_DDR_RAM)
#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
# include "ar9_ddr111_settings.h"
#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M)
# include "ar9_ddr166_settings.h"
#elif defined(CONFIG_CPU_442M_RAM_147M)
# include "ar9_ddr166_settings.h"
#elif defined(CONFIG_CPU_393M_RAM_196M)
# ifdef CONFIG_ETRON_RAM
# include "etron_ddr196_settings.h"
# else
# include "ar9_ddr196_settings.h"
# endif
#elif defined(CONFIG_CPU_442M_RAM_221M)
# include "ar9_ddr221_settings.h"
#elif defined(CONFIG_CPU_500M_RAM_250M)
# include "ar9_ddr250_settings.h"
#else
# warning "missing definition for ddr_settings.h, use default!"
# include "ar9_ddr_settings.h"
#endif
#endif /* CONFIG_USE_DDR_RAM */
#define EBU_MODUL_BASE 0xBE105300
#define EBU_CLC(value) 0x0000(value)
#define EBU_CON(value) 0x0010(value)
#define EBU_ADDSEL0(value) 0x0020(value)
#define EBU_ADDSEL1(value) 0x0024(value)
#define EBU_ADDSEL2(value) 0x0028(value)
#define EBU_ADDSEL3(value) 0x002C(value)
#define EBU_BUSCON0(value) 0x0060(value)
#define EBU_BUSCON1(value) 0x0064(value)
#define EBU_BUSCON2(value) 0x0068(value)
#define EBU_BUSCON3(value) 0x006C(value)
#define MC_MODUL_BASE 0xBF800000
#define MC_ERRCAUSE(value) 0x0010(value)
#define MC_ERRADDR(value) 0x0020(value)
#define MC_CON(value) 0x0060(value)
#define MC_SRAM_ENABLE 0x00000004
#define MC_SDRAM_ENABLE 0x00000002
#define MC_DDRRAM_ENABLE 0x00000001
#define MC_SDR_MODUL_BASE 0xBF800200
#define MC_IOGP(value) 0x0000(value)
#define MC_CTRLENA(value) 0x0010(value)
#define MC_MRSCODE(value) 0x0020(value)
#define MC_CFGDW(value) 0x0030(value)
#define MC_CFGPB0(value) 0x0040(value)
#define MC_LATENCY(value) 0x0080(value)
#define MC_TREFRESH(value) 0x0090(value)
#define MC_SELFRFSH(value) 0x00A0(value)
#define MC_DDR_MODUL_BASE 0xBF801000
#define MC_DC00(value) 0x0000(value)
#define MC_DC01(value) 0x0010(value)
#define MC_DC02(value) 0x0020(value)
#define MC_DC03(value) 0x0030(value)
#define MC_DC04(value) 0x0040(value)
#define MC_DC05(value) 0x0050(value)
#define MC_DC06(value) 0x0060(value)
#define MC_DC07(value) 0x0070(value)
#define MC_DC08(value) 0x0080(value)
#define MC_DC09(value) 0x0090(value)
#define MC_DC10(value) 0x00A0(value)
#define MC_DC11(value) 0x00B0(value)
#define MC_DC12(value) 0x00C0(value)
#define MC_DC13(value) 0x00D0(value)
#define MC_DC14(value) 0x00E0(value)
#define MC_DC15(value) 0x00F0(value)
#define MC_DC16(value) 0x0100(value)
#define MC_DC17(value) 0x0110(value)
#define MC_DC18(value) 0x0120(value)
#define MC_DC19(value) 0x0130(value)
#define MC_DC20(value) 0x0140(value)
#define MC_DC21(value) 0x0150(value)
#define MC_DC22(value) 0x0160(value)
#define MC_DC23(value) 0x0170(value)
#define MC_DC24(value) 0x0180(value)
#define MC_DC25(value) 0x0190(value)
#define MC_DC26(value) 0x01A0(value)
#define MC_DC27(value) 0x01B0(value)
#define MC_DC28(value) 0x01C0(value)
#define MC_DC29(value) 0x01D0(value)
#define MC_DC30(value) 0x01E0(value)
#define MC_DC31(value) 0x01F0(value)
#define MC_DC32(value) 0x0200(value)
#define MC_DC33(value) 0x0210(value)
#define MC_DC34(value) 0x0220(value)
#define MC_DC35(value) 0x0230(value)
#define MC_DC36(value) 0x0240(value)
#define MC_DC37(value) 0x0250(value)
#define MC_DC38(value) 0x0260(value)
#define MC_DC39(value) 0x0270(value)
#define MC_DC40(value) 0x0280(value)
#define MC_DC41(value) 0x0290(value)
#define MC_DC42(value) 0x02A0(value)
#define MC_DC43(value) 0x02B0(value)
#define MC_DC44(value) 0x02C0(value)
#define MC_DC45(value) 0x02D0(value)
#define MC_DC46(value) 0x02E0(value)
#define RCU_OFFSET 0xBF203000
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
#define RCU_STS (RCU_OFFSET + 0x0014)
#define CGU_OFFSET 0xBF103000
#define PLL0_CFG (CGU_OFFSET + 0x0004)
#define PLL1_CFG (CGU_OFFSET + 0x0008)
#define PLL2_CFG (CGU_OFFSET + 0x000C)
#define CGU_SYS (CGU_OFFSET + 0x0010)
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
#define IF_CLK (CGU_OFFSET + 0x0018)
#define CGU_SMD (CGU_OFFSET + 0x0020)
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
//05252006
#define pll0_35MHz_CONFIG 0x9D861059
#define pll1_35MHz_CONFIG 0x1A260CD9
#define pll2_35MHz_CONFIG 0x8000f1e5
#define pll0_36MHz_CONFIG 0x1000125D
#define pll1_36MHz_CONFIG 0x1B1E0C99
#define pll2_36MHz_CONFIG 0x8002f2a1
//05252006
//06063001-joelin disable the PCI CFRAME mask -start
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
*/
#define PCI_CR_PR_OFFSET 0xBE105400
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
#define PCI_CONFIG_SPACE 0xB7000000
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
//06063001-joelin disable the PCI CFRAME mask -end
.set noreorder
/*
* void ebu_init(void)
*/
.globl ebu_init
.ent ebu_init
ebu_init:
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
li t1, EBU_MODUL_BASE
#if defined(CONFIG_EBU_ADDSEL0)
li t2, CONFIG_EBU_ADDSEL0
sw t2, EBU_ADDSEL0(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL1)
li t2, CONFIG_EBU_ADDSEL1
sw t2, EBU_ADDSEL1(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL2)
li t2, CONFIG_EBU_ADDSEL2
sw t2, EBU_ADDSEL2(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL3)
li t2, CONFIG_EBU_ADDSEL3
sw t2, EBU_ADDSEL3(t1)
#endif
#if defined(CONFIG_EBU_BUSCON0)
li t2, CONFIG_EBU_BUSCON0
sw t2, EBU_BUSCON0(t1)
#endif
#if defined(CONFIG_EBU_BUSCON1)
li t2, CONFIG_EBU_BUSCON1
sw t2, EBU_BUSCON1(t1)
#endif
#if defined(CONFIG_EBU_BUSCON2)
li t2, CONFIG_EBU_BUSCON2
sw t2, EBU_BUSCON2(t1)
#endif
#if defined(CONFIG_EBU_BUSCON3)
li t2, CONFIG_EBU_BUSCON3
sw t2, EBU_BUSCON3(t1)
#endif
#endif
j ra
nop
.end ebu_init
/*
* void cgu_init(long)
*
* a0 has the clock value
*/
.globl cgu_init
.ent cgu_init
cgu_init:
li t2, CGU_SYS
lw t2,0(t2)
beq t2,a0,freq_up2date
nop
li t2, RCU_STS
lw t2, 0(t2)
and t2,0x00020000
beq t2,0x00020000,boot_36MHZ
nop
//05252006
li t1, PLL0_CFG
li t2, pll0_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_35MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
b wait_reset
nop
boot_36MHZ:
li t1, PLL0_CFG
li t2, pll0_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_36MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
//05252006
wait_reset:
b wait_reset
nop
freq_up2date:
j ra
nop
.end cgu_init
#ifndef CONFIG_USE_DDR_RAM
/*
* void sdram_init(long)
*
* a0 has the clock value
*/
.globl sdram_init
.ent sdram_init
sdram_init:
/* SDRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable SDRAM module in memory controller */
li t3, MC_SDRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_SDR_MODUL_BASE
/* disable the controller */
li t2, 0
sw t2, MC_CTRLENA(t1)
li t2, 0x822
sw t2, MC_IOGP(t1)
li t2, 0x2
sw t2, MC_CFGDW(t1)
/* Set CAS Latency */
li t2, 0x00000020
sw t2, MC_MRSCODE(t1)
/* Set CS0 to SDRAM parameters */
li t2, 0x000014d8
sw t2, MC_CFGPB0(t1)
/* Set SDRAM latency parameters */
li t2, 0x00036325; /* BC PC100 */
sw t2, MC_LATENCY(t1)
/* Set SDRAM refresh rate */
li t2, 0x00000C30
sw t2, MC_TREFRESH(t1)
/* Clear Power-down registers */
sw zero, MC_SELFRFSH(t1)
/* Finally enable the controller */
li t2, 1
sw t2, MC_CTRLENA(t1)
j ra
nop
.end sdram_init
#endif /* !CONFIG_USE_DDR_RAM */
#ifdef CONFIG_USE_DDR_RAM
/*
* void ddrram_init(long)
*
* a0 has the clock value
*/
.globl ddrram_init
.ent ddrram_init
ddrram_init:
/* DDR-DRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable DDR module in memory controller */
li t3, MC_DDRRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_DDR_MODUL_BASE
/* Write configuration to DDR controller registers */
li t2, MC_DC0_VALUE
sw t2, MC_DC00(t1)
li t2, MC_DC1_VALUE
sw t2, MC_DC01(t1)
li t2, MC_DC2_VALUE
sw t2, MC_DC02(t1)
li t2, MC_DC3_VALUE
sw t2, MC_DC03(t1)
li t2, MC_DC4_VALUE
sw t2, MC_DC04(t1)
li t2, MC_DC5_VALUE
sw t2, MC_DC05(t1)
li t2, MC_DC6_VALUE
sw t2, MC_DC06(t1)
li t2, MC_DC7_VALUE
sw t2, MC_DC07(t1)
li t2, MC_DC8_VALUE
sw t2, MC_DC08(t1)
li t2, MC_DC9_VALUE
sw t2, MC_DC09(t1)
li t2, MC_DC10_VALUE
sw t2, MC_DC10(t1)
li t2, MC_DC11_VALUE
sw t2, MC_DC11(t1)
li t2, MC_DC12_VALUE
sw t2, MC_DC12(t1)
li t2, MC_DC13_VALUE
sw t2, MC_DC13(t1)
li t2, MC_DC14_VALUE
sw t2, MC_DC14(t1)
li t2, MC_DC15_VALUE
sw t2, MC_DC15(t1)
li t2, MC_DC16_VALUE
sw t2, MC_DC16(t1)
li t2, MC_DC17_VALUE
sw t2, MC_DC17(t1)
li t2, MC_DC18_VALUE
sw t2, MC_DC18(t1)
li t2, MC_DC19_VALUE
sw t2, MC_DC19(t1)
li t2, MC_DC20_VALUE
sw t2, MC_DC20(t1)
li t2, MC_DC21_VALUE
sw t2, MC_DC21(t1)
li t2, MC_DC22_VALUE
sw t2, MC_DC22(t1)
li t2, MC_DC23_VALUE
sw t2, MC_DC23(t1)
li t2, MC_DC24_VALUE
sw t2, MC_DC24(t1)
li t2, MC_DC25_VALUE
sw t2, MC_DC25(t1)
li t2, MC_DC26_VALUE
sw t2, MC_DC26(t1)
li t2, MC_DC27_VALUE
sw t2, MC_DC27(t1)
li t2, MC_DC28_VALUE
sw t2, MC_DC28(t1)
li t2, MC_DC29_VALUE
sw t2, MC_DC29(t1)
li t2, MC_DC30_VALUE
sw t2, MC_DC30(t1)
li t2, MC_DC31_VALUE
sw t2, MC_DC31(t1)
li t2, MC_DC32_VALUE
sw t2, MC_DC32(t1)
li t2, MC_DC33_VALUE
sw t2, MC_DC33(t1)
li t2, MC_DC34_VALUE
sw t2, MC_DC34(t1)
li t2, MC_DC35_VALUE
sw t2, MC_DC35(t1)
li t2, MC_DC36_VALUE
sw t2, MC_DC36(t1)
li t2, MC_DC37_VALUE
sw t2, MC_DC37(t1)
li t2, MC_DC38_VALUE
sw t2, MC_DC38(t1)
li t2, MC_DC39_VALUE
sw t2, MC_DC39(t1)
li t2, MC_DC40_VALUE
sw t2, MC_DC40(t1)
li t2, MC_DC41_VALUE
sw t2, MC_DC41(t1)
li t2, MC_DC42_VALUE
sw t2, MC_DC42(t1)
li t2, MC_DC43_VALUE
sw t2, MC_DC43(t1)
li t2, MC_DC44_VALUE
sw t2, MC_DC44(t1)
li t2, MC_DC45_VALUE
sw t2, MC_DC45(t1)
li t2, MC_DC46_VALUE
sw t2, MC_DC46(t1)
li t2, 0x00000100
sw t2, MC_DC03(t1)
j ra
nop
.end ddrram_init
#endif /* CONFIG_USE_DDR_RAM */
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
*/
move t0, ra
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
#if defined(DDR166)
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
li a0,0xe8
#elif defined(DDR133)
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
li a0,0xe9
#else /* defined(DDR111) */
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
li a0,0xea
#endif
bal cgu_init
nop
bal ebu_init
nop
//06063001-joelin disable the PCI CFRAME mask-start
#ifdef DISABLE_CFRAME
li t1, PCI_CR_PCI //mw bf103034 80000000
li t2, 0x80000000
sw t2,0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x103
sw t2,0(t1)
li t1, CS_CFM //mw b700006c 0
li t2, 0x00
sw t2, 0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x1000103
sw t2, 0(t1)
#endif
//06063001-joelin disable the PCI CFRAME mask-end
#ifdef CONFIG_USE_DDR_RAM
bal ddrram_init
nop
#else
bal sdram_init
nop
#endif
move ra, t0
j ra
nop
.end lowlevel_init

543
package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S
View File

@ -1,543 +0,0 @@
/*
* Memory sub-system initialization code for AR9 board.
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2005 Andre Messerschmidt Infineon
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* History:
peng liu May 25, 2006, for PLL setting after reset, 05252006
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#if defined(CONFIG_USE_DDR_RAM)
#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
# include "ar9_ddr111_settings.h"
#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M)
# include "ar9_ddr166_settings.h"
#elif defined(CONFIG_CPU_442M_RAM_147M)
# include "ar9_ddr166_settings.h"
#elif defined(CONFIG_CPU_393M_RAM_196M)
# ifdef CONFIG_ETRON_RAM
# include "etron_ddr196_settings.h"
# else
# include "ar9_ddr196_settings.h"
# endif
#elif defined(CONFIG_CPU_442M_RAM_221M)
# include "ar9_ddr221_settings.h"
#elif defined(CONFIG_CPU_500M_RAM_250M)
# include "ar9_ddr250_settings.h"
#else
# warning "missing definition for ddr_settings.h, use default!"
# include "ar9_ddr_settings.h"
#endif
#endif /* CONFIG_USE_DDR_RAM */
#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
#error "missing include of ddr_settings.h"
#endif
#define EBU_MODUL_BASE 0xBE105300
#define EBU_CLC(value) 0x0000(value)
#define EBU_CON(value) 0x0010(value)
#define EBU_ADDSEL0(value) 0x0020(value)
#define EBU_ADDSEL1(value) 0x0024(value)
#define EBU_ADDSEL2(value) 0x0028(value)
#define EBU_ADDSEL3(value) 0x002C(value)
#define EBU_BUSCON0(value) 0x0060(value)
#define EBU_BUSCON1(value) 0x0064(value)
#define EBU_BUSCON2(value) 0x0068(value)
#define EBU_BUSCON3(value) 0x006C(value)
#define MC_MODUL_BASE 0xBF800000
#define MC_ERRCAUSE(value) 0x0010(value)
#define MC_ERRADDR(value) 0x0020(value)
#define MC_CON(value) 0x0060(value)
#define MC_SRAM_ENABLE 0x00000004
#define MC_SDRAM_ENABLE 0x00000002
#define MC_DDRRAM_ENABLE 0x00000001
#define MC_SDR_MODUL_BASE 0xBF800200
#define MC_IOGP(value) 0x0000(value)
#define MC_CTRLENA(value) 0x0010(value)
#define MC_MRSCODE(value) 0x0020(value)
#define MC_CFGDW(value) 0x0030(value)
#define MC_CFGPB0(value) 0x0040(value)
#define MC_LATENCY(value) 0x0080(value)
#define MC_TREFRESH(value) 0x0090(value)
#define MC_SELFRFSH(value) 0x00A0(value)
#define MC_DDR_MODUL_BASE 0xBF801000
#define MC_DC00(value) 0x0000(value)
#define MC_DC01(value) 0x0010(value)
#define MC_DC02(value) 0x0020(value)
#define MC_DC03(value) 0x0030(value)
#define MC_DC04(value) 0x0040(value)
#define MC_DC05(value) 0x0050(value)
#define MC_DC06(value) 0x0060(value)
#define MC_DC07(value) 0x0070(value)
#define MC_DC08(value) 0x0080(value)
#define MC_DC09(value) 0x0090(value)
#define MC_DC10(value) 0x00A0(value)
#define MC_DC11(value) 0x00B0(value)
#define MC_DC12(value) 0x00C0(value)
#define MC_DC13(value) 0x00D0(value)
#define MC_DC14(value) 0x00E0(value)
#define MC_DC15(value) 0x00F0(value)
#define MC_DC16(value) 0x0100(value)
#define MC_DC17(value) 0x0110(value)
#define MC_DC18(value) 0x0120(value)
#define MC_DC19(value) 0x0130(value)
#define MC_DC20(value) 0x0140(value)
#define MC_DC21(value) 0x0150(value)
#define MC_DC22(value) 0x0160(value)
#define MC_DC23(value) 0x0170(value)
#define MC_DC24(value) 0x0180(value)
#define MC_DC25(value) 0x0190(value)
#define MC_DC26(value) 0x01A0(value)
#define MC_DC27(value) 0x01B0(value)
#define MC_DC28(value) 0x01C0(value)
#define MC_DC29(value) 0x01D0(value)
#define MC_DC30(value) 0x01E0(value)
#define MC_DC31(value) 0x01F0(value)
#define MC_DC32(value) 0x0200(value)
#define MC_DC33(value) 0x0210(value)
#define MC_DC34(value) 0x0220(value)
#define MC_DC35(value) 0x0230(value)
#define MC_DC36(value) 0x0240(value)
#define MC_DC37(value) 0x0250(value)
#define MC_DC38(value) 0x0260(value)
#define MC_DC39(value) 0x0270(value)
#define MC_DC40(value) 0x0280(value)
#define MC_DC41(value) 0x0290(value)
#define MC_DC42(value) 0x02A0(value)
#define MC_DC43(value) 0x02B0(value)
#define MC_DC44(value) 0x02C0(value)
#define MC_DC45(value) 0x02D0(value)
#define MC_DC46(value) 0x02E0(value)
#define RCU_OFFSET 0xBF203000
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
#define RCU_STS (RCU_OFFSET + 0x0014)
#define CGU_OFFSET 0xBF103000
#define PLL0_CFG (CGU_OFFSET + 0x0004)
#define PLL1_CFG (CGU_OFFSET + 0x0008)
#define PLL2_CFG (CGU_OFFSET + 0x000C)
#define CGU_SYS (CGU_OFFSET + 0x0010)
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
#define IF_CLK (CGU_OFFSET + 0x0018)
#define CGU_SMD (CGU_OFFSET + 0x0020)
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
#define pll1_36MHz_CONFIG 0x9800f25f
.set noreorder
/*
* void ebu_init(void)
*/
.globl ebu_init
.ent ebu_init
ebu_init:
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
li t1, EBU_MODUL_BASE
#if defined(CONFIG_EBU_ADDSEL0)
li t2, CONFIG_EBU_ADDSEL0
sw t2, EBU_ADDSEL0(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL1)
li t2, CONFIG_EBU_ADDSEL1
sw t2, EBU_ADDSEL1(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL2)
li t2, CONFIG_EBU_ADDSEL2
sw t2, EBU_ADDSEL2(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL3)
li t2, CONFIG_EBU_ADDSEL3
sw t2, EBU_ADDSEL3(t1)
#endif
#if defined(CONFIG_EBU_BUSCON0)
li t2, CONFIG_EBU_BUSCON0
sw t2, EBU_BUSCON0(t1)
#endif
#if defined(CONFIG_EBU_BUSCON1)
li t2, CONFIG_EBU_BUSCON1
sw t2, EBU_BUSCON1(t1)
#endif
#if defined(CONFIG_EBU_BUSCON2)
li t2, CONFIG_EBU_BUSCON2
sw t2, EBU_BUSCON2(t1)
#endif
#if defined(CONFIG_EBU_BUSCON3)
li t2, CONFIG_EBU_BUSCON3
sw t2, EBU_BUSCON3(t1)
#endif
#endif
j ra
nop
.end ebu_init
/*
* void cgu_init(long)
*
* a0 has the clock value
*/
.globl cgu_init
.ent cgu_init
cgu_init:
li t2, CGU_SYS
lw t2,0(t2)
beq t2,a0,freq_up2date
nop
li t1, CGU_SYS
sw a0,0(t1)
#if defined(CONFIG_CPU_333M_RAM_166M) && defined(CONFIG_USE_PLL1)
li t1, PLL1_CFG
li a1, pll1_36MHz_CONFIG
sw a1, 0(t1)
#endif
#if defined(CONFIG_CLASS_II_DDR_PAD)
li t1, CGU_SMD
li a1, 0x200000
sw a1, 0(t1) // Turn on DDR PAD Class II to INC drive.
#endif
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
b wait_reset
nop
wait_reset:
b wait_reset
nop
freq_up2date:
j ra
nop
.end cgu_init
#ifndef CONFIG_USE_DDR_RAM
/*
* void sdram_init(long)
*
* a0 has the clock value
*/
.globl sdram_init
.ent sdram_init
sdram_init:
/* SDRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable SDRAM module in memory controller */
li t3, MC_SDRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_SDR_MODUL_BASE
/* disable the controller */
li t2, 0
sw t2, MC_CTRLENA(t1)
li t2, 0x822
sw t2, MC_IOGP(t1)
li t2, 0x2
sw t2, MC_CFGDW(t1)
/* Set CAS Latency */
li t2, 0x00000020
sw t2, MC_MRSCODE(t1)
/* Set CS0 to SDRAM parameters */
li t2, 0x000014d8
sw t2, MC_CFGPB0(t1)
/* Set SDRAM latency parameters */
li t2, 0x00036325; /* BC PC100 */
sw t2, MC_LATENCY(t1)
/* Set SDRAM refresh rate */
li t2, 0x00000C30
sw t2, MC_TREFRESH(t1)
/* Clear Power-down registers */
sw zero, MC_SELFRFSH(t1)
/* Finally enable the controller */
li t2, 1
sw t2, MC_CTRLENA(t1)
j ra
nop
.end sdram_init
#endif /* !CONFIG_USE_DDR_RAM */
#ifdef CONFIG_USE_DDR_RAM
/*
* void ddrram_init(long)
*
* a0 has the clock value
*/
.globl ddrram_init
.ent ddrram_init
ddrram_init:
/* DDR-DRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable DDR module in memory controller */
li t3, MC_DDRRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_DDR_MODUL_BASE
/* Write configuration to DDR controller registers */
li t2, MC_DC0_VALUE
sw t2, MC_DC00(t1)
li t2, MC_DC1_VALUE
sw t2, MC_DC01(t1)
li t2, MC_DC2_VALUE
sw t2, MC_DC02(t1)
li t2, MC_DC3_VALUE
sw t2, MC_DC03(t1)
li t2, MC_DC4_VALUE
sw t2, MC_DC04(t1)
li t2, MC_DC5_VALUE
sw t2, MC_DC05(t1)
li t2, MC_DC6_VALUE
sw t2, MC_DC06(t1)
li t2, MC_DC7_VALUE
sw t2, MC_DC07(t1)
li t2, MC_DC8_VALUE
sw t2, MC_DC08(t1)
li t2, MC_DC9_VALUE
sw t2, MC_DC09(t1)
li t2, MC_DC10_VALUE
sw t2, MC_DC10(t1)
li t2, MC_DC11_VALUE
sw t2, MC_DC11(t1)
li t2, MC_DC12_VALUE
sw t2, MC_DC12(t1)
li t2, MC_DC13_VALUE
sw t2, MC_DC13(t1)
li t2, MC_DC14_VALUE
sw t2, MC_DC14(t1)
li t2, MC_DC15_VALUE
sw t2, MC_DC15(t1)
li t2, MC_DC16_VALUE
sw t2, MC_DC16(t1)
li t2, MC_DC17_VALUE
sw t2, MC_DC17(t1)
li t2, MC_DC18_VALUE
sw t2, MC_DC18(t1)
li t2, MC_DC19_VALUE
sw t2, MC_DC19(t1)
li t2, MC_DC20_VALUE
sw t2, MC_DC20(t1)
li t2, MC_DC21_VALUE
sw t2, MC_DC21(t1)
li t2, MC_DC22_VALUE
sw t2, MC_DC22(t1)
li t2, MC_DC23_VALUE
sw t2, MC_DC23(t1)
li t2, MC_DC24_VALUE
sw t2, MC_DC24(t1)
li t2, MC_DC25_VALUE
sw t2, MC_DC25(t1)
li t2, MC_DC26_VALUE
sw t2, MC_DC26(t1)
li t2, MC_DC27_VALUE
sw t2, MC_DC27(t1)
li t2, MC_DC28_VALUE
sw t2, MC_DC28(t1)
li t2, MC_DC29_VALUE
sw t2, MC_DC29(t1)
li t2, MC_DC30_VALUE
sw t2, MC_DC30(t1)
li t2, MC_DC31_VALUE
sw t2, MC_DC31(t1)
li t2, MC_DC32_VALUE
sw t2, MC_DC32(t1)
li t2, MC_DC33_VALUE
sw t2, MC_DC33(t1)
li t2, MC_DC34_VALUE
sw t2, MC_DC34(t1)
li t2, MC_DC35_VALUE
sw t2, MC_DC35(t1)
li t2, MC_DC36_VALUE
sw t2, MC_DC36(t1)
li t2, MC_DC37_VALUE
sw t2, MC_DC37(t1)
li t2, MC_DC38_VALUE
sw t2, MC_DC38(t1)
li t2, MC_DC39_VALUE
sw t2, MC_DC39(t1)
li t2, MC_DC40_VALUE
sw t2, MC_DC40(t1)
li t2, MC_DC41_VALUE
sw t2, MC_DC41(t1)
li t2, MC_DC42_VALUE
sw t2, MC_DC42(t1)
li t2, MC_DC43_VALUE
sw t2, MC_DC43(t1)
li t2, MC_DC44_VALUE
sw t2, MC_DC44(t1)
li t2, MC_DC45_VALUE
sw t2, MC_DC45(t1)
li t2, MC_DC46_VALUE
sw t2, MC_DC46(t1)
li t2, 0x00000100
sw t2, MC_DC03(t1)
j ra
nop
.end ddrram_init
#endif /* CONFIG_USE_DDR_RAM */
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
*/
move t0, ra
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
#if defined(CONFIG_SYS_EBU_BOOT)
/*
using PPL1 value
*/
li a0,0x90
bal cgu_init
nop
#endif /* CONFIG_SYS_EBU_BOOT */
bal ebu_init
nop
#ifdef CONFIG_SYS_EBU_BOOT
#ifndef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_USE_DDR_RAM
bal ddrram_init
nop
#else
bal sdram_init
nop
#endif
#endif /* CONFIG_SYS_RAMBOOT */
#endif /* CONFIG_SYS_EBU_BOOT */
move ra, t0
j ra
nop
.end lowlevel_init

48
package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S
View File

@ -1,48 +0,0 @@
/*
* Power Management unit initialization code for AMAZON development board.
*
* Copyright (c) 2003 Ou Ke, Infineon.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#define PMU_PWDCR 0xBF10201C
#define PMU_SR 0xBF102020
.globl pmuenable
pmuenable:
li t0, PMU_PWDCR
li t1, 0x2 /* enable everything */
sw t1, 0(t0)
#if 0
1:
li t0, PMU_SR
lw t2, 0(t0)
bne t1, t2, 1b
nop
#endif
j ra
nop

74
package/uboot-lantiq/files/board/infineon/easy50812/u-boot-bootstrap.lds
View File

@ -1,74 +0,0 @@
/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = .;
_gp = ALIGN(16) +0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
. = ALIGN(4);
.sdata : { *(.sdata) }
. = .;
. = ALIGN(4);
.payload : { *(.payload) }
. = ALIGN(4);
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}

70
package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds
View File

@ -1,70 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}

67
package/uboot-lantiq/files/cpu/mips/ar9-clock.c
View File

@ -1,67 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/ar9.h>
ulong ifx_get_ddr_hz(void)
{
switch((*AR9_CGU_SYS) & 0x05) {
case 0x01:
case 0x05:
return CLOCK_111M;
case 0x00:
case 0x04:
return CLOCK_166M;
}
return 0;
}
ulong ifx_get_cpuclk(void)
{
switch((*AR9_CGU_SYS) & 0x05) {
case 0x00:
case 0x01:
return CLOCK_333M;
case 0x04:
return CLOCK_166M;
case 0x05:
return CLOCK_111M;
}
return 0;
}
ulong get_bus_freq(ulong dummy)
{
unsigned int ddr_clock=ifx_get_ddr_hz();
if((*AR9_CGU_SYS) & 0x40){
return ddr_clock/2;
} else {
return ddr_clock;
}
}

46
package/uboot-lantiq/files/cpu/mips/ar9/Makefile
View File

@ -1,46 +0,0 @@
#########################################################################
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = clock.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

67
package/uboot-lantiq/files/cpu/mips/ar9/clock.c
View File

@ -1,67 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/ar9.h>
ulong ifx_get_ddr_hz(void)
{
switch((*AR9_CGU_SYS) & 0x05) {
case 0x01:
case 0x05:
return CLOCK_111M;
case 0x00:
case 0x04:
return CLOCK_166M;
}
return 0;
}
ulong ifx_get_cpuclk(void)
{
switch((*AR9_CGU_SYS) & 0x05) {
case 0x00:
case 0x01:
return CLOCK_333M;
case 0x04:
return CLOCK_166M;
case 0x05:
return CLOCK_111M;
}
return 0;
}
ulong get_bus_freq(ulong dummy)
{
unsigned int ddr_clock=ifx_get_ddr_hz();
if((*AR9_CGU_SYS) & 0x40){
return ddr_clock/2;
} else {
return ddr_clock;
}
}

60
package/uboot-lantiq/files/cpu/mips/ar9/ifx_cache.S
View File

@ -1,60 +0,0 @@
#define IFX_CACHE_EXTRA_INVALID_TAG \
mtc0 zero, CP0_TAGLO, 1; \
mtc0 zero, CP0_TAGLO, 2; \
mtc0 zero, CP0_TAGLO, 3; \
mtc0 zero, CP0_TAGLO, 4;
#define IFX_CACHE_EXTRA_OPERATION \
/* set WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ECCF_WST; \
or a0, a1; \
mtc0 a0, CP0_ECC; \
\
li a0, K0BASE; \
move a2, t2; /* icacheSize */ \
move a3, t4; /* icacheLineSize */ \
move a1, a2; \
icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \
\
/* clear WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ~ECCF_WST; \
and a0, a1; \
mtc0 a0, CP0_ECC; \
\
/* 1: initialise dcache tags. */ \
\
/* cache line size */ \
li a2, CFG_CACHELINE_SIZE; \
/* kseg0 mem address */ \
li a1, 0; \
li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \
1: \
/* store tag (invalid, not locked) */ \
cache 0x8, 0(a1); \
cache 0x9, 0(a1); \
\
add a3, -1; \
bne a3, zero, 1b; \
add a1, a2; \
\
/* set WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ECCF_WST; \
or a0, a1; \
mtc0 a0, CP0_ECC; \
\
li a0, K0BASE; \
move a2, t3; /* dcacheSize */ \
move a3, t5; /* dcacheLineSize */ \
move a1, a2; \
icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \
\
/* clear WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ~ECCF_WST; \
and a0, a1; \
mtc0 a0, CP0_ECC;

65
package/uboot-lantiq/files/cpu/mips/danube-clock.c
View File

@ -1,65 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/danube.h>
ulong ifx_get_ddr_hz(void)
{
static const ulong ddr_freq[] = {166666667,133333333,111111111,83333333};
return ddr_freq[((*DANUBE_CGU_SYS) & 0x3)];
}
ulong ifx_get_cpuclk(void)
{
#ifdef CONFIG_USE_EMULATOR
return EMULATOR_CPU_SPEED;
#else //NOT CONFIG_USE_EMULATOR
unsigned int ddr_clock=ifx_get_ddr_hz();
switch((*DANUBE_CGU_SYS) & 0xc){
case 0:
default:
return 323333333;
case 4:
return ddr_clock;
case 8:
return ddr_clock << 1;
}
#endif
}
ulong get_bus_freq(ulong dummy)
{
#ifdef CONFIG_USE_EMULATOR
unsigned int clkCPU;
clkCPU = ifx_get_cpuclk();
return clkCPU >> 2;
#else //NOT CONFIG_USE_EMULATOR
unsigned int ddr_clock=ifx_get_ddr_hz();
if ((*DANUBE_CGU_SYS) & 0x40){
return ddr_clock >> 1;
}
return ddr_clock;
#endif
}

46
package/uboot-lantiq/files/cpu/mips/danube/Makefile
View File

@ -1,46 +0,0 @@
#########################################################################
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = clock.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

65
package/uboot-lantiq/files/cpu/mips/danube/clock.c
View File

@ -1,65 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/danube.h>
ulong ifx_get_ddr_hz(void)
{
static const ulong ddr_freq[] = {166666667,133333333,111111111,83333333};
return ddr_freq[((*DANUBE_CGU_SYS) & 0x3)];
}
ulong ifx_get_cpuclk(void)
{
#ifdef CONFIG_USE_EMULATOR
return EMULATOR_CPU_SPEED;
#else //NOT CONFIG_USE_EMULATOR
unsigned int ddr_clock=ifx_get_ddr_hz();
switch((*DANUBE_CGU_SYS) & 0xc){
case 0:
default:
return 323333333;
case 4:
return ddr_clock;
case 8:
return ddr_clock << 1;
}
#endif
}
ulong get_bus_freq(ulong dummy)
{
#ifdef CONFIG_USE_EMULATOR
unsigned int clkCPU;
clkCPU = ifx_get_cpuclk();
return clkCPU >> 2;
#else //NOT CONFIG_USE_EMULATOR
unsigned int ddr_clock=ifx_get_ddr_hz();
if ((*DANUBE_CGU_SYS) & 0x40){
return ddr_clock >> 1;
}
return ddr_clock;
#endif
}

60
package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S
View File

@ -1,60 +0,0 @@
#define IFX_CACHE_EXTRA_INVALID_TAG \
mtc0 zero, CP0_TAGLO, 1; \
mtc0 zero, CP0_TAGLO, 2; \
mtc0 zero, CP0_TAGLO, 3; \
mtc0 zero, CP0_TAGLO, 4;
#define IFX_CACHE_EXTRA_OPERATION \
/* set WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ECCF_WST; \
or a0, a1; \
mtc0 a0, CP0_ECC; \
\
li a0, K0BASE; \
move a2, t2; /* icacheSize */ \
move a3, t4; /* icacheLineSize */ \
move a1, a2; \
icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \
\
/* clear WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ~ECCF_WST; \
and a0, a1; \
mtc0 a0, CP0_ECC; \
\
/* 1: initialise dcache tags. */ \
\
/* cache line size */ \
li a2, CFG_CACHELINE_SIZE; \
/* kseg0 mem address */ \
li a1, 0; \
li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \
1: \
/* store tag (invalid, not locked) */ \
cache 0x8, 0(a1); \
cache 0x9, 0(a1); \
\
add a3, -1; \
bne a3, zero, 1b; \
add a1, a2; \
\
/* set WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ECCF_WST; \
or a0, a1; \
mtc0 a0, CP0_ECC; \
\
li a0, K0BASE; \
move a2, t3; /* dcacheSize */ \
move a3, t5; /* dcacheLineSize */ \
move a1, a2; \
icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \
\
/* clear WST bit */ \
mfc0 a0, CP0_ECC; \
li a1, ~ECCF_WST; \
and a0, a1; \
mtc0 a0, CP0_ECC;

218
package/uboot-lantiq/files/cpu/mips/ifx_asc.c
View File

@ -1,218 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2009
* Infineon Technologies AG, http://www.infineon.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include "ifx_asc.h"
#define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask))
#define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask))
#define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) )
#undef DEBUG_ASC_RAW
#ifdef DEBUG_ASC_RAW
#define DEBUG_ASC_RAW_RX_BUF 0xA0800000
#define DEBUG_ASC_RAW_TX_BUF 0xA0900000
#endif
DECLARE_GLOBAL_DATA_PTR;
static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE);
/*
* FDV fASC
* BaudRate = ----- * --------------------
* 512 16 * (ReloadValue+1)
*/
/*
* FDV fASC
* ReloadValue = ( ----- * --------------- ) - 1
* 512 16 * BaudRate
*/
static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload)
{
u32 clock = fasc / 16;
u32 fdv; /* best fdv */
u32 reload = 0; /* best reload */
u32 diff; /* smallest diff */
u32 idiff; /* current diff */
u32 ireload; /* current reload */
u32 i; /* current fdv */
u32 result; /* current resulting baudrate */
if (clock > 0x7FFFFF)
clock /= 512;
else
baudrate *= 512;
fdv = 512; /* start with 1:1 fraction */
diff = baudrate; /* highest possible */
/* i is the test fdv value -- start with the largest possible */
for (i = 512; i > 0; i--)
{
ireload = (clock * i) / baudrate;
if (ireload < 1)
break; /* already invalid */
result = (clock * i) / ireload;
idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result);
if (idiff == 0)
{
fdv = i;
reload = ireload;
break; /* can't do better */
}
else if (idiff < diff)
{
fdv = i; /* best so far */
reload = ireload;
diff = idiff; /* update lowest diff*/
}
}
*pfdv = (fdv == 512) ? 0 : fdv;
*preload = reload - 1;
}
void serial_setbrg (void)
{
u32 ReloadValue, fdv;
serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue);
/* Disable Baud Rate Generator; BG should only be written when R=0 */
CLEAR_BIT(asc_con, ASCCON_R);
/* Enable Fractional Divider */
SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */
/* Set fractional divider value */
asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK);
/* Set reload value in BG */
asc_writel(asc_bg, ReloadValue);
/* Enable Baud Rate Generator */
SET_BIT(asc_con, ASCCON_R); /* R = 1 */
}
int serial_init (void)
{
/* and we have to set CLC register*/
CLEAR_BIT(asc_clc, ASCCLC_DISS);
SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
/* initialy we are in async mode */
asc_writel(asc_con, ASCCON_M_8ASYNC);
/* select input port */
asc_writel(asc_pisel, CONSOLE_TTY & 0x1);
/* TXFIFO's filling level */
SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK,
ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL);
/* enable TXFIFO */
SET_BIT(asc_txfcon, ASCTXFCON_TXFEN);
/* RXFIFO's filling level */
SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK,
ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN);
/* set baud rate */
serial_setbrg();
/* enable error signals & Receiver enable */
SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
return 0;
}
void serial_putc (const char c)
{
u32 txFl = 0;
#ifdef DEBUG_ASC_RAW
static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
*debug++=c;
#endif
if (c == '\n')
serial_putc ('\r');
/* check do we have a free space in the TX FIFO */
/* get current filling level */
do {
txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
}
while ( txFl == ASC_TXFIFO_FULL );
asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */
/* check for errors */
if ( asc_readl(asc_state) & ASCSTATE_TOE ) {
SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE);
return;
}
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
char c;
while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 );
c = (char)(asc_readl(asc_rbuf) & 0xff);
#ifdef DEBUG_ASC_RAW
static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
*debug++=c;
#endif
return c;
}
int serial_tstc (void)
{
int res = 1;
if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) {
res = 0;
}
return res;
}

199
package/uboot-lantiq/files/cpu/mips/ifx_asc.h
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@ -1,199 +0,0 @@
/*****************************************************************************
* DANUBE BootROM
* Copyright (c) 2005, Infineon Technologies AG, All rights reserved
* IFAP DC COM SD
*****************************************************************************/
#ifndef __ASC_H
#define __ASC_H
/* channel operating modes */
#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define ASC_TXFIFO_FL 1
#define ASC_RXFIFO_FL 1
#define ASC_TXFIFO_FULL 16
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0000000f
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_8IRDA 0x1
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_M_7IRDA 0x3
#define ASCCON_WLSMASK 0x0000000c
#define ASCCON_WLSOFFSET 2
#define ASCCON_WLS_8BIT 0x0
#define ASCCON_WLS_7BIT 0x1
#define ASCCON_PEN 0x00000010
#define ASCCON_ODD 0x00000020
#define ASCCON_SP 0x00000040
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_ERRCLK 0x00000400
#define ASCCON_EMMASK 0x00001800
#define ASCCON_EMOFFSET 11
#define ASCCON_EM_ECHO_OFF 0x0
#define ASCCON_EM_ECHO_AB 0x1
#define ASCCON_EM_ECHO_ON 0x2
#define ASCCON_LB 0x00002000
#define ASCCON_ACO 0x00004000
#define ASCCON_R 0x00008000
#define ASCCON_PAL 0x00010000
#define ASCCON_FEN 0x00020000
#define ASCCON_RUEN 0x00040000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCCON_BEN 0x00200000
#define ASCCON_TXINV 0x01000000
#define ASCCON_RXINV 0x02000000
#define ASCCON_TXMSB 0x04000000
#define ASCCON_RXMSB 0x08000000
/* STATE register's bits and bitfields */
#define ASCSTATE_REN 0x00000001
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_RUE 0x00040000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_TOE 0x00100000
#define ASCSTATE_BE 0x00200000
#define ASCSTATE_TXBVMASK 0x07000000
#define ASCSTATE_TXBVOFFSET 24
#define ASCSTATE_TXEOM 0x08000000
#define ASCSTATE_RXBVMASK 0x70000000
#define ASCSTATE_RXBVOFFSET 28
#define ASCSTATE_RXEOM 0x80000000
/* WHBSTATE register's bits and bitfields */
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRRUE 0x00000010
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCWHBSTATE_CLRTOE 0x00000040
#define ASCWHBSTATE_CLRBE 0x00000080
#define ASCWHBSTATE_SETPE 0x00000100
#define ASCWHBSTATE_SETFE 0x00000200
#define ASCWHBSTATE_SETRUE 0x00000400
#define ASCWHBSTATE_SETROE 0x00000800
#define ASCWHBSTATE_SETTOE 0x00001000
#define ASCWHBSTATE_SETBE 0x00002000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_CLRABEN 0x0001
#define ASCWHBABCON_SETABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_CLRSCCDET 0x0040
#define ASCWHBABSTAT_SETSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFIFO1 0x00000400
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFIFO1 0x00000400
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
typedef struct IfxAsc_s
{
unsigned long asc_clc; /*0x0000*/
unsigned long asc_pisel; /*0x0004*/
unsigned long asc_id; /*0x0008*/
unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
unsigned long asc_con; /*0x0010*/
unsigned long asc_state; /*0x0014*/
unsigned long asc_whbstate; /*0x0018*/
unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
unsigned long asc_tbuf; /*0x0020*/
unsigned long asc_rbuf; /*0x0024*/
unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
unsigned long asc_abcon; /*0x0030*/
unsigned long asc_abstat; /* not used */ /*0x0034*/
unsigned long asc_whbabcon; /*0x0038*/
unsigned long asc_whbabstat; /* not used */ /*0x003C*/
unsigned long asc_rxfcon; /*0x0040*/
unsigned long asc_txfcon; /*0x0044*/
unsigned long asc_fstat; /*0x0048*/
unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
unsigned long asc_bg; /*0x0050*/
unsigned long asc_bg_timer; /*0x0054*/
unsigned long asc_fdv; /*0x0058*/
unsigned long asc_pmw; /*0x005C*/
unsigned long asc_modcon; /*0x0060*/
unsigned long asc_modstat; /*0x0064*/
unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
unsigned long asc_sfcc; /*0x0070*/
unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
unsigned long asc_eomcon; /*0x0080*/
unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
unsigned long asc_dmacon; /*0x00EC*/
unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
unsigned long asc_irnen; /*0x00F4*/
unsigned long asc_irnicr; /*0x00F8*/
unsigned long asc_irncr; /*0x00FC*/
} IfxAsc_t;
/* Register access macros */
#define asc_readl(reg) \
readl(&pAsc->reg)
#define asc_writel(reg,value) \
writel((value), &pAsc->reg)
#endif /* __ASC_H */

401
package/uboot-lantiq/files/drivers/net/ifx_etop.c
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@ -1,401 +0,0 @@
/*
* Lantiq CPE device ethernet driver.
* Supposed to work on Twinpass/Danube.
*
* Based on INCA-IP driver:
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Thomas Langer, Ralph Hempel
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <config.h>
#include "ifx_etop.h"
#if defined(CONFIG_AR9)
#define TX_CHAN_NO 1
#define RX_CHAN_NO 0
#else
#define TX_CHAN_NO 7
#define RX_CHAN_NO 6
#endif
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 8
#define TOUT_LOOP 100
typedef struct
{
union
{
struct
{
volatile u32 OWN :1;
volatile u32 C :1;
volatile u32 Sop :1;
volatile u32 Eop :1;
volatile u32 reserved :3;
volatile u32 Byteoffset :2;
volatile u32 reserve :7;
volatile u32 DataLen :16;
}field;
volatile u32 word;
}status;
volatile u32 DataPtr;
} dma_rx_descriptor_t;
typedef struct
{
union
{
struct
{
volatile u32 OWN :1;
volatile u32 C :1;
volatile u32 Sop :1;
volatile u32 Eop :1;
volatile u32 Byteoffset :5;
volatile u32 reserved :7;
volatile u32 DataLen :16;
}field;
volatile u32 word;
}status;
volatile u32 DataPtr;
} dma_tx_descriptor_t;
static volatile dma_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
static volatile dma_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
static int tx_num, rx_num;
static volatile IfxDMA_t *pDma = (IfxDMA_t *)CKSEG1ADDR(DANUBE_DMA_BASE);
static int lq_eth_init(struct eth_device *dev, bd_t * bis);
static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length);
static int lq_eth_recv(struct eth_device *dev);
static void lq_eth_halt(struct eth_device *dev);
static void lq_eth_init_chip(void);
static void lq_eth_init_dma(void);
static int lq_eth_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
u32 timeout = 50000;
u32 phy, reg;
if ((phyAddr > 0x1F) || (regAddr > 0x1F) || (retVal == NULL))
return -1;
phy = (phyAddr & 0x1F) << 21;
reg = (regAddr & 0x1F) << 16;
*ETOP_MDIO_ACC = 0xC0000000 | phy | reg;
while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
udelay(10);
if (timeout==0) {
*retVal = 0;
return -1;
}
*retVal = *ETOP_MDIO_ACC & 0xFFFF;
return 0;
}
static int lq_eth_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
u32 timeout = 50000;
u32 phy, reg;
if ((phyAddr > 0x1F) || (regAddr > 0x1F))
return -1;
phy = (phyAddr & 0x1F) << 21;
reg = (regAddr & 0x1F) << 16;
*ETOP_MDIO_ACC = 0x80000000 | phy | reg | data;
while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
udelay(10);
if (timeout==0)
return -1;
return 0;
}
int lq_eth_initialize(bd_t * bis)
{
struct eth_device *dev;
debug("Entered lq_eth_initialize()\n");
if (!(dev = malloc (sizeof *dev))) {
printf("Failed to allocate memory\n");
return -1;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "lq_cpe_eth");
dev->init = lq_eth_init;
dev->halt = lq_eth_halt;
dev->send = lq_eth_send;
dev->recv = lq_eth_recv;
eth_register(dev);
#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
/* register mii command access routines */
miiphy_register(dev->name,
lq_eth_miiphy_read, lq_eth_miiphy_write);
#endif
lq_eth_init_dma();
lq_eth_init_chip();
return 0;
}
static int lq_eth_init(struct eth_device *dev, bd_t * bis)
{
int i;
uchar *enetaddr = dev->enetaddr;
debug("lq_eth_init %x:%x:%x:%x:%x:%x\n",
enetaddr[0], enetaddr[1], enetaddr[2], enetaddr[3], enetaddr[4], enetaddr[5]);
*ENET_MAC_DA0 = (enetaddr[0]<<24) + (enetaddr[1]<<16) + (enetaddr[2]<< 8) + enetaddr[3];
*ENET_MAC_DA1 = (enetaddr[4]<<24) + (enetaddr[5]<<16);
*ENETS_CFG |= 1<<28; /* enable filter for unicast packets */
tx_num=0;
rx_num=0;
for(i=0;i < NUM_RX_DESC; i++) {
dma_rx_descriptor_t * rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[i]);
rx_desc->status.word=0;
rx_desc->status.field.OWN=1;
rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */
rx_desc->DataPtr=(u32)CKSEG1ADDR(NetRxPackets[i]);
NetRxPackets[i][0] = 0xAA;
}
/* Reset DMA */
dma_writel(dma_cs, RX_CHAN_NO);
dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
dma_writel(dma_cpoll, 0x80000040);
/*set descriptor base*/
dma_writel(dma_cdba, (u32)rx_des_ring);
dma_writel(dma_cdlen, NUM_RX_DESC);
dma_writel(dma_cie, 0);
dma_writel(dma_cctrl, 0x30000);
for(i=0;i < NUM_TX_DESC; i++) {
dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[i]);
memset(tx_desc, 0, sizeof(tx_des_ring[0]));
}
dma_writel(dma_cs, TX_CHAN_NO);
dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
dma_writel(dma_cpoll, 0x80000040);
dma_writel(dma_cdba, (u32)tx_des_ring);
dma_writel(dma_cdlen, NUM_TX_DESC);
dma_writel(dma_cie, 0);
dma_writel(dma_cctrl, 0x30100);
/* turn on DMA rx & tx channel
*/
dma_writel(dma_cs, RX_CHAN_NO);
dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1); /*reset and turn on the channel*/
return 0;
}
static void lq_eth_halt(struct eth_device *dev)
{
int i;
debug("lq_eth_halt()\n");
for(i=0;i<8;i++) {
dma_writel(dma_cs, i);
dma_writel(dma_cctrl, dma_readl(dma_cctrl) & ~1);/*stop the dma channel*/
}
}
#ifdef DEBUG
static void lq_dump(const u8 *data, const u32 length)
{
u32 i;
debug("\n");
for(i=0;i<length;i++) {
debug("%02x ", data[i]);
}
debug("\n");
}
#endif
static int lq_eth_send(struct eth_device *dev, volatile void *packet, int length)
{
int i;
int res = -1;
volatile dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[tx_num]);
if (length <= 0) {
printf ("%s: bad packet size: %d\n", dev->name, length);
goto Done;
}
for(i=0; tx_desc->status.field.OWN==1; i++) {
if (i>=TOUT_LOOP) {
printf("NO Tx Descriptor...");
goto Done;
}
}
tx_desc->status.field.Sop=1;
tx_desc->status.field.Eop=1;
tx_desc->status.field.C=0;
tx_desc->DataPtr = (u32)CKSEG1ADDR(packet);
if (length<60)
tx_desc->status.field.DataLen = 60;
else
tx_desc->status.field.DataLen = (u32)length;
flush_cache((u32)packet, tx_desc->status.field.DataLen);
asm("SYNC");
tx_desc->status.field.OWN=1;
res=length;
tx_num++;
if (tx_num==NUM_TX_DESC) tx_num=0;
#ifdef DEBUG
lq_dump(tx_desc->DataPtr, tx_desc->status.field.DataLen);
#endif
dma_writel(dma_cs, TX_CHAN_NO);
if (!(dma_readl(dma_cctrl) & 1)) {
dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1);
}
Done:
return res;
}
static int lq_eth_recv(struct eth_device *dev)
{
int length = 0;
volatile dma_rx_descriptor_t * rx_desc;
rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[rx_num]);
if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) {
return 0;
}
debug("rx");
#ifdef DEBUG
lq_dump(rx_desc->DataPtr, rx_desc->status.field.DataLen);
#endif
length = rx_desc->status.field.DataLen;
if (length > 4) {
invalidate_dcache_range((u32)CKSEG0ADDR(rx_desc->DataPtr), (u32) CKSEG0ADDR(rx_desc->DataPtr) + length);
NetReceive(NetRxPackets[rx_num], length);
} else {
printf("ERROR: Invalid rx packet length.\n");
}
rx_desc->status.field.Sop=0;
rx_desc->status.field.Eop=0;
rx_desc->status.field.C=0;
rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
rx_desc->status.field.OWN=1;
rx_num++;
if (rx_num == NUM_RX_DESC)
rx_num=0;
return length;
}
static void lq_eth_init_chip(void)
{
*ETOP_MDIO_CFG &= ~0x6;
*ENET_MAC_CFG = 0x187;
// turn on port0, set to rmii and turn off port1.
#ifdef CONFIG_RMII
*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x0000000A;
#else
*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x00000008;
#endif
*ETOP_IG_PLEN_CTRL = 0x004005EE; // set packetlen.
*ENET_MAC_CFG |= 1<<11; /*enable the crc*/
return;
}
static void lq_eth_init_dma(void)
{
/* Reset DMA */
dma_writel(dma_ctrl, dma_readl(dma_ctrl) | 1);
dma_writel(dma_irnen, 0);/*disable all the interrupts first*/
/* Clear Interrupt Status Register */
dma_writel(dma_irncr, 0xfffff);
/*disable all the dma interrupts*/
dma_writel(dma_irnen, 0);
/*disable channel 0 and channel 1 interrupts*/
dma_writel(dma_cs, RX_CHAN_NO);
dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
dma_writel(dma_cpoll, 0x80000040);
/*set descriptor base*/
dma_writel(dma_cdba, (u32)rx_des_ring);
dma_writel(dma_cdlen, NUM_RX_DESC);
dma_writel(dma_cie, 0);
dma_writel(dma_cctrl, 0x30000);
dma_writel(dma_cs, TX_CHAN_NO);
dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
dma_writel(dma_cpoll, 0x80000040);
dma_writel(dma_cdba, (u32)tx_des_ring);
dma_writel(dma_cdlen, NUM_TX_DESC);
dma_writel(dma_cie, 0);
dma_writel(dma_cctrl, 0x30100);
/*enable the poll function and set the poll counter*/
//dma_writel(DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
/*set port properties, enable endian conversion for switch*/
dma_writel(dma_ps, 0);
dma_writel(dma_pctrl, dma_readl(dma_pctrl) | (0xf<<8));/*enable 32 bit endian conversion*/
return;
}

91
package/uboot-lantiq/files/drivers/net/ifx_etop.h
View File

@ -1,91 +0,0 @@
/*
* Lantiq switch ethernet driver for Danube family.
*
* Based on INCA-IP driver:
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __DRIVERS_IFX_SW_H__
#define __DRIVERS_IFX_SW_H__
#define DANUBE_PPE32_BASE 0xBE180000
#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
#define DANUBE_DMA_BASE 0xBE104100
typedef struct IfxDMA_s
{
unsigned long dma_clc; /*0x0000*/
unsigned long dma_rsvd1[1]; /* for mapping */ /*0x0004*/
unsigned long dma_id; /*0x0008*/
unsigned long dma_rsvd2[1]; /* for mapping */ /*0x000C*/
unsigned long dma_ctrl; /*0x0010*/
unsigned long dma_cpoll; /*0x0014*/
unsigned long dma_cs; /*0x0018*/
unsigned long dma_cctrl; /*0x001C*/
unsigned long dma_cdba; /*0x0020*/
unsigned long dma_cdlen; /*0x0024*/
unsigned long dma_cis; /*0x0028*/
unsigned long dma_cie; /*0x002C*/
unsigned long dma_rsvd3[4]; /* for mapping */ /*0x0030*/
unsigned long dma_ps; /*0x0040*/
unsigned long dma_pctrl; /*0x0044*/
unsigned long dma_rsvd4[43]; /* for mapping */ /*0x0048*/
unsigned long dma_irnen; /*0x00F4*/
unsigned long dma_irncr; /*0x00F8*/
unsigned long dma_irnicr; /*0x00FC*/
} IfxDMA_t;
/* Register access macros */
#define dma_readl(reg) \
readl(&pDma->reg)
#define dma_writel(reg,value) \
writel((value), &pDma->reg)
int lq_eth_initialize(bd_t * bis);
#endif /* __DRIVERS_IFX_SW_H__ */

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/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2009
* Infineon Technologies AG, http://www.infineon.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include "ifx_asc.h"
#define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask))
#define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask))
#define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) )
#undef DEBUG_ASC_RAW
#ifdef DEBUG_ASC_RAW
#define DEBUG_ASC_RAW_RX_BUF 0xA0800000
#define DEBUG_ASC_RAW_TX_BUF 0xA0900000
#endif
DECLARE_GLOBAL_DATA_PTR;
static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE);
/*
* FDV fASC
* BaudRate = ----- * --------------------
* 512 16 * (ReloadValue+1)
*/
/*
* FDV fASC
* ReloadValue = ( ----- * --------------- ) - 1
* 512 16 * BaudRate
*/
static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload)
{
u32 clock = fasc / 16;
u32 fdv; /* best fdv */
u32 reload = 0; /* best reload */
u32 diff; /* smallest diff */
u32 idiff; /* current diff */
u32 ireload; /* current reload */
u32 i; /* current fdv */
u32 result; /* current resulting baudrate */
if (clock > 0x7FFFFF)
clock /= 512;
else
baudrate *= 512;
fdv = 512; /* start with 1:1 fraction */
diff = baudrate; /* highest possible */
/* i is the test fdv value -- start with the largest possible */
for (i = 512; i > 0; i--)
{
ireload = (clock * i) / baudrate;
if (ireload < 1)
break; /* already invalid */
result = (clock * i) / ireload;
idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result);
if (idiff == 0)
{
fdv = i;
reload = ireload;
break; /* can't do better */
}
else if (idiff < diff)
{
fdv = i; /* best so far */
reload = ireload;
diff = idiff; /* update lowest diff*/
}
}
*pfdv = (fdv == 512) ? 0 : fdv;
*preload = reload - 1;
}
void serial_setbrg (void)
{
u32 ReloadValue, fdv;
serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue);
/* Disable Baud Rate Generator; BG should only be written when R=0 */
CLEAR_BIT(asc_con, ASCCON_R);
/* Enable Fractional Divider */
SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */
/* Set fractional divider value */
asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK);
/* Set reload value in BG */
asc_writel(asc_bg, ReloadValue);
/* Enable Baud Rate Generator */
SET_BIT(asc_con, ASCCON_R); /* R = 1 */
}
int serial_init (void)
{
/* and we have to set CLC register*/
CLEAR_BIT(asc_clc, ASCCLC_DISS);
SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
/* initialy we are in async mode */
asc_writel(asc_con, ASCCON_M_8ASYNC);
/* select input port */
asc_writel(asc_pisel, CONSOLE_TTY & 0x1);
/* TXFIFO's filling level */
SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK,
ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL);
/* enable TXFIFO */
SET_BIT(asc_txfcon, ASCTXFCON_TXFEN);
/* RXFIFO's filling level */
SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK,
ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN);
/* set baud rate */
serial_setbrg();
/* enable error signals & Receiver enable */
SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
return 0;
}
void serial_putc (const char c)
{
u32 txFl = 0;
#ifdef DEBUG_ASC_RAW
static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
*debug++=c;
#endif
if (c == '\n')
serial_putc ('\r');
/* check do we have a free space in the TX FIFO */
/* get current filling level */
do {
txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
}
while ( txFl == ASC_TXFIFO_FULL );
asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */
/* check for errors */
if ( asc_readl(asc_state) & ASCSTATE_TOE ) {
SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE);
return;
}
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
char c;
while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 );
c = (char)(asc_readl(asc_rbuf) & 0xff);
#ifdef DEBUG_ASC_RAW
static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
*debug++=c;
#endif
return c;
}
int serial_tstc (void)
{
int res = 1;
if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) {
res = 0;
}
return res;
}

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/*****************************************************************************
* DANUBE BootROM
* Copyright (c) 2005, Infineon Technologies AG, All rights reserved
* IFAP DC COM SD
*****************************************************************************/
#ifndef __ASC_H
#define __ASC_H
/* channel operating modes */
#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define ASC_TXFIFO_FL 1
#define ASC_RXFIFO_FL 1
#define ASC_TXFIFO_FULL 16
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0000000f
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_8IRDA 0x1
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_M_7IRDA 0x3
#define ASCCON_WLSMASK 0x0000000c
#define ASCCON_WLSOFFSET 2
#define ASCCON_WLS_8BIT 0x0
#define ASCCON_WLS_7BIT 0x1
#define ASCCON_PEN 0x00000010
#define ASCCON_ODD 0x00000020
#define ASCCON_SP 0x00000040
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_ERRCLK 0x00000400
#define ASCCON_EMMASK 0x00001800
#define ASCCON_EMOFFSET 11
#define ASCCON_EM_ECHO_OFF 0x0
#define ASCCON_EM_ECHO_AB 0x1
#define ASCCON_EM_ECHO_ON 0x2
#define ASCCON_LB 0x00002000
#define ASCCON_ACO 0x00004000
#define ASCCON_R 0x00008000
#define ASCCON_PAL 0x00010000
#define ASCCON_FEN 0x00020000
#define ASCCON_RUEN 0x00040000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCCON_BEN 0x00200000
#define ASCCON_TXINV 0x01000000
#define ASCCON_RXINV 0x02000000
#define ASCCON_TXMSB 0x04000000
#define ASCCON_RXMSB 0x08000000
/* STATE register's bits and bitfields */
#define ASCSTATE_REN 0x00000001
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_RUE 0x00040000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_TOE 0x00100000
#define ASCSTATE_BE 0x00200000
#define ASCSTATE_TXBVMASK 0x07000000
#define ASCSTATE_TXBVOFFSET 24
#define ASCSTATE_TXEOM 0x08000000
#define ASCSTATE_RXBVMASK 0x70000000
#define ASCSTATE_RXBVOFFSET 28
#define ASCSTATE_RXEOM 0x80000000
/* WHBSTATE register's bits and bitfields */
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRRUE 0x00000010
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCWHBSTATE_CLRTOE 0x00000040
#define ASCWHBSTATE_CLRBE 0x00000080
#define ASCWHBSTATE_SETPE 0x00000100
#define ASCWHBSTATE_SETFE 0x00000200
#define ASCWHBSTATE_SETRUE 0x00000400
#define ASCWHBSTATE_SETROE 0x00000800
#define ASCWHBSTATE_SETTOE 0x00001000
#define ASCWHBSTATE_SETBE 0x00002000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_CLRABEN 0x0001
#define ASCWHBABCON_SETABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_CLRSCCDET 0x0040
#define ASCWHBABSTAT_SETSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFIFO1 0x00000400
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFIFO1 0x00000400
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
typedef struct IfxAsc_s
{
unsigned long asc_clc; /*0x0000*/
unsigned long asc_pisel; /*0x0004*/
unsigned long asc_id; /*0x0008*/
unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
unsigned long asc_con; /*0x0010*/
unsigned long asc_state; /*0x0014*/
unsigned long asc_whbstate; /*0x0018*/
unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
unsigned long asc_tbuf; /*0x0020*/
unsigned long asc_rbuf; /*0x0024*/
unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
unsigned long asc_abcon; /*0x0030*/
unsigned long asc_abstat; /* not used */ /*0x0034*/
unsigned long asc_whbabcon; /*0x0038*/
unsigned long asc_whbabstat; /* not used */ /*0x003C*/
unsigned long asc_rxfcon; /*0x0040*/
unsigned long asc_txfcon; /*0x0044*/
unsigned long asc_fstat; /*0x0048*/
unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
unsigned long asc_bg; /*0x0050*/
unsigned long asc_bg_timer; /*0x0054*/
unsigned long asc_fdv; /*0x0058*/
unsigned long asc_pmw; /*0x005C*/
unsigned long asc_modcon; /*0x0060*/
unsigned long asc_modstat; /*0x0064*/
unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
unsigned long asc_sfcc; /*0x0070*/
unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
unsigned long asc_eomcon; /*0x0080*/
unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
unsigned long asc_dmacon; /*0x00EC*/
unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
unsigned long asc_irnen; /*0x00F4*/
unsigned long asc_irnicr; /*0x00F8*/
unsigned long asc_irncr; /*0x00FC*/
} IfxAsc_t;
/* Register access macros */
#define asc_readl(reg) \
readl(&pAsc->reg)
#define asc_writel(reg,value) \
writel((value), &pAsc->reg)
#endif /* __ASC_H */

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/*
* (C) Copyright 2010
* Ralph Hempel
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/***********************************************************************/
/* Module : PMU register address and bits */
/***********************************************************************/
#define AR9_PMU (0xBF102000)
/* PMU Power down Control Register */
#define AR9_PMU_PWDCR ((volatile u32*)(AR9_PMU + 0x001C))
/* PMU Status Register */
#define AR9_PMU_SR ((volatile u32*)(AR9_PMU + 0x0020))
/** DMA block */
#define AR9_PMU_DMA (1<<5)
#define AR9_PMU_SDIO (1<<16)
#define AR9_PMU_USB0 (1<<6)
#define AR9_PMU_USB0_P (1<<0)
#define AR9_PMU_SWITCH (1<<28)
/***********************************************************************/
/* Module : RCU register address and bits */
/***********************************************************************/
#define AR9_RCU_BASE_ADDR (0xBF203000)
#define AR9_RCU_RST_REQ ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0010))
#define AR9_RCU_RST_STAT ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0014))
#define AR9_RST_ALL (1 << 30)
/*** Reset Request Register Bits ***/
#define AR9_RCU_RST_REQ_SRST (1 << 30)
#define AR9_RCU_RST_REQ_ARC_JTAG (1 << 20)
#define AR9_RCU_RST_REQ_PCI (1 << 13)
#define AR9_RCU_RST_REQ_AFE (1 << 11)
#define AR9_RCU_RST_REQ_SDIO (1 << 19)
#define AR9_RCU_RST_REQ_DMA (1 << 9)
#define AR9_RCU_RST_REQ_PPE (1 << 8)
#define AR9_RCU_RST_REQ_DFE (1 << 7)
/***********************************************************************/
/* Module : GPIO register address and bits */
/***********************************************************************/
#define AR9_GPIO (0xBE100B00)
/***Port 0 Data Output Register (0010H)***/
#define AR9_GPIO_P0_OUT ((volatile u32 *)(AR9_GPIO+ 0x0010))
/***Port 1 Data Output Register (0040H)***/
#define AR9_GPIO_P1_OUT ((volatile u32 *)(AR9_GPIO+ 0x0040))
/***Port 2 Data Output Register (0070H)***/
#define AR9_GPIO_P2_OUT ((volatile u32 *)(AR9_GPIO+ 0x0070))
/***Port 3 Data Output Register (00A0H)***/
#define AR9_GPIO_P3_OUT ((volatile u32 *)(AR9_GPIO+ 0x00A0))
/***Port 0 Data Input Register (0014H)***/
#define AR9_GPIO_P0_IN ((volatile u32 *)(AR9_GPIO+ 0x0014))
/***Port 1 Data Input Register (0044H)***/
#define AR9_GPIO_P1_IN ((volatile u32 *)(AR9_GPIO+ 0x0044))
/***Port 2 Data Input Register (0074H)***/
#define AR9_GPIO_P2_IN ((volatile u32 *)(AR9_GPIO+ 0x0074))
/***Port 3 Data Input Register (00A4H)***/
#define AR9_GPIO_P3_IN ((volatile u32 *)(AR9_GPIO+ 0x00A4))
/***Port 0 Direction Register (0018H)***/
#define AR9_GPIO_P0_DIR ((volatile u32 *)(AR9_GPIO+ 0x0018))
/***Port 1 Direction Register (0048H)***/
#define AR9_GPIO_P1_DIR ((volatile u32 *)(AR9_GPIO+ 0x0048))
/***Port 2 Direction Register (0078H)***/
#define AR9_GPIO_P2_DIR ((volatile u32 *)(AR9_GPIO+ 0x0078))
/***Port 3 Direction Register (0048H)***/
#define AR9_GPIO_P3_DIR ((volatile u32 *)(AR9_GPIO+ 0x00A8))
/***Port 0 Alternate Function Select Register 0 (001C H) ***/
#define AR9_GPIO_P0_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x001C))
/***Port 1 Alternate Function Select Register 0 (004C H) ***/
#define AR9_GPIO_P1_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x004C))
/***Port 2 Alternate Function Select Register 0 (007C H) ***/
#define AR9_GPIO_P2_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x007C))
/***Port 3 Alternate Function Select Register 0 (00AC H) ***/
#define AR9_GPIO_P3_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x00AC))
/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
#define AR9_GPIO_P0_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0020))
/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
#define AR9_GPIO_P1_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0050))
/***Port 2 Alternate Function Select Register 0 (0080 H) ***/
#define AR9_GPIO_P2_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0080))
/***Port 3 Alternate Function Select Register 0 (0064 H) ***/
#define AR9_GPIO_P3_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0064))
/***Port 0 Open Drain Control Register (0024H)***/
#define AR9_GPIO_P0_OD ((volatile u32 *)(AR9_GPIO+ 0x0024))
/***Port 1 Open Drain Control Register (0054H)***/
#define AR9_GPIO_P1_OD ((volatile u32 *)(AR9_GPIO+ 0x0054))
/***Port 2 Open Drain Control Register (0084H)***/
#define AR9_GPIO_P2_OD ((volatile u32 *)(AR9_GPIO+ 0x0084))
/***Port 3 Open Drain Control Register (0034H)***/
#define AR9_GPIO_P3_OD ((volatile u32 *)(AR9_GPIO+ 0x0034))
/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
#define AR9_GPIO_P0_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0028))
/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
#define AR9_GPIO_P1_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0058))
/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/
#define AR9_GPIO_P2_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0088))
/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/
//#define AR9_GPIO_P3_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0094))
/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
#define AR9_GPIO_P0_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x002C))
/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
#define AR9_GPIO_P1_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x005C))
/***Port 2 Pull Up/Pull Down Select Register (008C H)***/
#define AR9_GPIO_P2_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x008C))
/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/
#define AR9_GPIO_P3_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x0038))
/***Port 0 Pull Up Device Enable Register (0030 H)***/
#define AR9_GPIO_P0_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0030))
/***Port 1 Pull Up Device Enable Register (0060 H)***/
#define AR9_GPIO_P1_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0060))
/***Port 2 Pull Up Device Enable Register (0090 H)***/
#define AR9_GPIO_P2_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0090))
/***Port 3 Pull Up Device Enable Register (003c H)***/
#define AR9_GPIO_P3_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x003C))
/***********************************************************************/
/* Module : CGU register address and bits */
/***********************************************************************/
#define AR9_CGU (0xBF103000)
/***CGU Clock PLL0 ***/
#define AR9_CGU_PLL0_CFG ((volatile u32*)(AR9_CGU+ 0x0004))
/***CGU Clock PLL1 ***/
#define AR9_CGU_PLL1_CFG ((volatile u32*)(AR9_CGU+ 0x0008))
/***CGU Clock SYS Mux Register***/
#define AR9_CGU_SYS ((volatile u32*)(AR9_CGU+ 0x0010))
/***CGU Interface Clock Control Register***/
#define AR9_CGU_IFCCR ((volatile u32*)(AR9_CGU+ 0x0018))
/***CGU PCI Clock Control Register**/
#define AR9_CGU_PCICR ((volatile u32*)(AR9_CGU+ 0x0034))
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
#define CLOCK_111M 111111111
#define CLOCK_133M 133333333
#define CLOCK_166M 166666667
#define CLOCK_196M 196666667
#define CLOCK_333M 333333333
#define CLOCK_366M 366666667
#define CLOCK_500M 500000000
/***********************************************************************/
/* Module : MPS register address and bits */
/***********************************************************************/
#define AR9_MPS (KSEG1+0x1F107000)
#define AR9_MPS_CHIPID ((volatile u32*)(AR9_MPS + 0x0344))
#define AR9_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
#define AR9_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
#define AR9_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
/***********************************************************************/
/* Module : EBU register address and bits */
/***********************************************************************/
#define AR9_EBU (0xBE105300)
#define AR9_EBU_CLC ((volatile u32*)(AR9_EBU+ 0x0000))
#define AR9_EBU_CLC_DISS (1 << 1)
#define AR9_EBU_CLC_DISR (1 << 0)
#define AR9_EBU_ID ((volatile u32*)(AR9_EBU+ 0x0008))
/***EBU Global Control Register***/
#define AR9_EBU_CON ((volatile u32*)(AR9_EBU+ 0x0010))
#define AR9_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
#define AR9_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
#define AR9_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
#define AR9_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
#define AR9_EBU_CON_ARBSYNC (1 << 5)
//#define AR9_EBU_CON_1 (1 << 3)
/***EBU Address Select Register 0***/
#define AR9_EBU_ADDSEL0 ((volatile u32*)(AR9_EBU + 0x0020))
/***EBU Address Select Register 1***/
#define AR9_EBU_ADDSEL1 ((volatile u32*)(AR9_EBU + 0x0024))
/***EBU Address Select Register 2***/
#define AR9_EBU_ADDSEL2 ((volatile u32*)(AR9_EBU + 0x0028))
/***EBU Address Select Register 3***/
#define AR9_EBU_ADDSEL3 ((volatile u32*)(AR9_EBU + 0x002C))
#define AR9_EBU_ADDSEL_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
#define AR9_EBU_ADDSEL_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
#define AR9_EBU_ADDSEL_MIRRORE (1 << 1)
#define AR9_EBU_ADDSEL_REGEN (1 << 0)
/***EBU Bus Configuration Register 0***/
#define AR9_EBU_BUSCON0 ((volatile u32*)(AR9_EBU+ 0x0060))
#define AR9_EBU_BUSCON0_WRDIS (1 << 31)
#define AR9_EBU_BUSCON0_ADSWP (value) (1 << 30)
#define AR9_EBU_BUSCON0_PG_EN (value) (1 << 29)
#define AR9_EBU_BUSCON0_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24)
#define AR9_EBU_BUSCON0_SETUP (1 << 22)
#define AR9_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
#define AR9_EBU_BUSCON0_WAITINV (1 << 19)
#define AR9_EBU_BUSCON0_VN_EN (1 << 18)
#define AR9_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
#define AR9_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14)
#define AR9_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12)
#define AR9_EBU_BUSCON0_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8)
#define AR9_EBU_BUSCON0_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6)
#define AR9_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
#define AR9_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
#define AR9_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
/***EBU Bus Configuration Register 1***/
#define AR9_EBU_BUSCON1 ((volatile u32*)(AR9_EBU+ 0x0064))
#define AR9_EBU_BUSCON1_WRDIS (1 << 31)
#define AR9_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
#define AR9_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
#define AR9_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
#define AR9_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
#define AR9_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
#define AR9_EBU_BUSCON1_WAITINV (1 << 19)
#define AR9_EBU_BUSCON1_SETUP (1 << 18)
#define AR9_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
#define AR9_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
#define AR9_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
#define AR9_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
#define AR9_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
#define AR9_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
/***EBU Bus Configuration Register 2***/
#define AR9_EBU_BUSCON2 ((volatile u32*)(AR9_EBU+ 0x0068))
#define AR9_EBU_BUSCON2_WRDIS (1 << 31)
#define AR9_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
#define AR9_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
#define AR9_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
#define AR9_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
#define AR9_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
#define AR9_EBU_BUSCON2_WAITINV (1 << 19)
#define AR9_EBU_BUSCON2_SETUP (1 << 18)
#define AR9_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
#define AR9_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
#define AR9_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
#define AR9_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
#define AR9_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
#define AR9_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
/***EBU Bus Configuration Register 2***/
#define AR9_EBU_BUSCON3 ((volatile u32*)(AR9_EBU+ 0x006C))
#define AR9_EBU_BUSCON3_WRDIS (1 << 31)
#define AR9_EBU_BUSCON3_ADSWP (value) (1 << 30)
#define AR9_EBU_BUSCON3_PG_EN (value) (1 << 29)
#define AR9_EBU_BUSCON3_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24)
#define AR9_EBU_BUSCON3_SETUP (1 << 22)
#define AR9_EBU_BUSCON3_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
#define AR9_EBU_BUSCON3_WAITINV (1 << 19)
#define AR9_EBU_BUSCON3_VN_EN (1 << 18)
#define AR9_EBU_BUSCON3_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
#define AR9_EBU_BUSCON3_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14)
#define AR9_EBU_BUSCON3_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12)
#define AR9_EBU_BUSCON3_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8)
#define AR9_EBU_BUSCON3_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6)
#define AR9_EBU_BUSCON3_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
#define AR9_EBU_BUSCON3_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
#define AR9_EBU_BUSCON3_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
/***********************************************************************/
/* Module : SDRAM register address and bits */
/***********************************************************************/
#define AR9_SDRAM (0xBF800000)
/***********************************************************************/
/* Module : ASC0 register address and bits */
/***********************************************************************/
#define AR9_ASC0 (KSEG1 | 0x1E100400)
#define AR9_ASC0_TBUF ((volatile u32*)(AR9_ASC0 + 0x0020))
#define AR9_ASC0_RBUF ((volatile u32*)(AR9_ASC0 + 0x0024))
#define AR9_ASC0_FSTAT ((volatile u32*)(AR9_ASC0 + 0x0048))
/***********************************************************************/
/* Module : ASC1 register address and bits */
/***********************************************************************/
#define AR9_ASC1 (KSEG1 | 0x1E100C00)
#define AR9_ASC1_TBUF ((volatile u32*)(AR9_ASC1 + 0x0020))
#define AR9_ASC1_RBUF ((volatile u32*)(AR9_ASC1 + 0x0024))
#define AR9_ASC1_FSTAT ((volatile u32*)(AR9_ASC1 + 0x0048))
/***********************************************************************/
/* Module : DMA register address and bits */
/***********************************************************************/
#define AR9_DMA_OFFSET (0xBE104100)
/***********************************************************************/
#define AR9_DMA_CLC ((volatile u32*)(AR9_DMA_OFFSET + 0x0000))
#define AR9_DMA_ID ((volatile u32*)(AR9_DMA_OFFSET + 0x0008))
#define AR9_DMA_CTRL (volatile u32*)(AR9_DMA_BASE + 0x10)
/** DMA Port Select Register */
#define AR9_DMA_PS ((volatile u32*)(AR9_DMA_OFFSET + 0x0040))
/** DMA Port Control Register */
#define AR9_DMA_PCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x0044))
#define AR9_DMA_IRNEN ((volatile u32*)(AR9_DMA_OFFSET + 0x00F4))
#define AR9_DMA_IRNCR ((volatile u32*)(AR9_DMA_OFFSET + 0x00F8))
#define AR9_DMA_IRNICR ((volatile u32*)(AR9_DMA_OFFSET + 0x00FC))
#define AR9_DMA_CS ((volatile u32*)(AR9_DMA_OFFSET + 0x0018))
#define AR9_DMA_CCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x001C))
#define AR9_DMA_CDBA ((volatile u32*)(AR9_DMA_OFFSET + 0x0020))
#define AR9_DMA_CIE ((volatile u32*)(AR9_DMA_OFFSET + 0x002C))
#define AR9_DMA_CIS ((volatile u32*)(AR9_DMA_OFFSET + 0x0028))
#define AR9_DMA_CDLEN ((volatile u32*)(AR9_DMA_OFFSET + 0x0024))
#define AR9_DMA_CPOLL ((volatile u32*)(AR9_DMA_OFFSET + 0x0014))
/***********************************************************************/
/* Module : GPORT switch register */
/***********************************************************************/
#define AR9_SW (0xBE108000)
#define AR9_SW_PS (AR9_SW + 0x000)
#define AR9_SW_P0_CTL (AR9_SW + 0x004)
#define AR9_SW_P1_CTL (AR9_SW + 0x008)
#define AR9_SW_P2_CTL (AR9_SW + 0x00C)
#define AR9_SW_P0_VLAN (AR9_SW + 0x010)
#define AR9_SW_P1_VLAN (AR9_SW + 0x014)
#define AR9_SW_P2_VLAN (AR9_SW + 0x018)
#define AR9_SW_P0_INCTL (AR9_SW + 0x020)
#define AR9_SW_P1_INCTL (AR9_SW + 0x024)
#define AR9_SW_P2_INCTL (AR9_SW + 0x028)
#define AR9_SW_DF_PORTMAP (AR9_SW + 0x02C)
#define AR9_SW_P0_ECS_Q32 (AR9_SW + 0x030)
#define AR9_SW_P0_ECS_Q10 (AR9_SW + 0x034)
#define AR9_SW_P0_ECW_Q32 (AR9_SW + 0x038)
#define AR9_SW_P0_ECW_Q10 (AR9_SW + 0x03C)
#define AR9_SW_P1_ECS_Q32 (AR9_SW + 0x040)
#define AR9_SW_P1_ECS_Q10 (AR9_SW + 0x044)
#define AR9_SW_P1_ECW_Q32 (AR9_SW + 0x048)
#define AR9_SW_P1_ECW_Q10 (AR9_SW + 0x04C)
#define AR9_SW_P2_ECS_Q32 (AR9_SW + 0x050)
#define AR9_SW_P2_ECS_Q10 (AR9_SW + 0x054)
#define AR9_SW_P2_ECW_Q32 (AR9_SW + 0x058)
#define AR9_SW_P2_ECW_Q10 (AR9_SW + 0x05C)
#define AR9_SW_INT_ENA (AR9_SW + 0x060)
#define AR9_SW_INT_ST (AR9_SW + 0x064)
#define AR9_SW_GCTL0 (AR9_SW + 0x068)
#define AR9_SW_GCTL1 (AR9_SW + 0x06C)
#define AR9_SW_ARP (AR9_SW + 0x070)
#define AR9_SW_STRM_CTL (AR9_SW + 0x074)
#define AR9_SW_RGMII_CTL (AR9_SW + 0x078)
#define AR9_SW_1P_PRT (AR9_SW + 0x07C)
#define AR9_SW_GBKT_SZBS (AR9_SW + 0x080)
#define AR9_SW_GBKT_SZEBS (AR9_SW + 0x084)
#define AR9_SW_BF_TH (AR9_SW + 0x088)
#define AR9_SW_PMAC_HD_CTL (AR9_SW + 0x08C)
#define AR9_SW_PMAC_SA1 (AR9_SW + 0x090)
#define AR9_SW_PMAC_SA2 (AR9_SW + 0x094)
#define AR9_SW_PMAC_DA1 (AR9_SW + 0x098)
#define AR9_SW_PMAC_DA2 (AR9_SW + 0x09C)
#define AR9_SW_PMAC_VLAN (AR9_SW + 0x0A0)
#define AR9_SW_PMAC_TX_IPG (AR9_SW + 0x0A4)
#define AR9_SW_PMAC_RX_IPG (AR9_SW + 0x0A8)
#define AR9_SW_ADR_TB_CTL0 (AR9_SW + 0x0AC)
#define AR9_SW_ADR_TB_CTL1 (AR9_SW + 0x0B0)
#define AR9_SW_ADR_TB_CTL2 (AR9_SW + 0x0B4)
#define AR9_SW_ADR_TB_ST0 (AR9_SW + 0x0B8)
#define AR9_SW_ADR_TB_ST1 (AR9_SW + 0x0BC)
#define AR9_SW_ADR_TB_ST2 (AR9_SW + 0x0C0)
#define AR9_SW_RMON_CTL (AR9_SW + 0x0C4)
#define AR9_SW_RMON_ST (AR9_SW + 0x0C8)
#define AR9_SW_MDIO_CTL (AR9_SW + 0x0CC)
#define AR9_SW_MDIO_DATA (AR9_SW + 0x0D0)
#define AR9_SW_TP_FLT_ACT (AR9_SW + 0x0D4)
#define AR9_SW_PRTCL_FLT_ACT (AR9_SW + 0x0D8)
#define AR9_SW_VLAN_FLT0 (AR9_SW + 0x100)
#define AR9_SW_VLAN_FLT1 (AR9_SW + 0x104)
#define AR9_SW_VLAN_FLT2 (AR9_SW + 0x108)
#define AR9_SW_VLAN_FLT3 (AR9_SW + 0x10C)
#define AR9_SW_VLAN_FLT4 (AR9_SW + 0x110)
#define AR9_SW_VLAN_FLT5 (AR9_SW + 0x114)
#define AR9_SW_VLAN_FLT6 (AR9_SW + 0x118)
#define AR9_SW_VLAN_FLT7 (AR9_SW + 0x11C)
#define AR9_SW_VLAN_FLT8 (AR9_SW + 0x120)
#define AR9_SW_VLAN_FLT9 (AR9_SW + 0x124)
#define AR9_SW_VLAN_FLT10 (AR9_SW + 0x128)
#define AR9_SW_VLAN_FLT11 (AR9_SW + 0x12C)
#define AR9_SW_VLAN_FLT12 (AR9_SW + 0x130)
#define AR9_SW_VLAN_FLT13 (AR9_SW + 0x134)
#define AR9_SW_VLAN_FLT14 (AR9_SW + 0x138)
#define AR9_SW_VLAN_FLT15 (AR9_SW + 0x13C)
#define AR9_SW_TP_FLT10 (AR9_SW + 0x140)
#define AR9_SW_TP_FLT32 (AR9_SW + 0x144)
#define AR9_SW_TP_FLT54 (AR9_SW + 0x148)
#define AR9_SW_TP_FLT76 (AR9_SW + 0x14C)
#define AR9_SW_DFSRV_MAP0 (AR9_SW + 0x150)
#define AR9_SW_DFSRV_MAP1 (AR9_SW + 0x154)
#define AR9_SW_DFSRV_MAP2 (AR9_SW + 0x158)
#define AR9_SW_DFSRV_MAP3 (AR9_SW + 0x15C)
#define AR9_SW_TCP_PF0 (AR9_SW + 0x160)
#define AR9_SW_TCP_PF1 (AR9_SW + 0x164)
#define AR9_SW_TCP_PF2 (AR9_SW + 0x168)
#define AR9_SW_TCP_PF3 (AR9_SW + 0x16C)
#define AR9_SW_TCP_PF4 (AR9_SW + 0x170)
#define AR9_SW_TCP_PF5 (AR9_SW + 0x174)
#define AR9_SW_TCP_PF6 (AR9_SW + 0x178)
#define AR9_SW_TCP_PF7 (AR9_SW + 0x17C)
#define AR9_SW_RA_03_00 (AR9_SW + 0x180)
#define AR9_SW_RA_07_04 (AR9_SW + 0x184)
#define AR9_SW_RA_0B_08 (AR9_SW + 0x188)
#define AR9_SW_RA_0F_0C (AR9_SW + 0x18C)
#define AR9_SW_RA_13_10 (AR9_SW + 0x190)
#define AR9_SW_RA_17_14 (AR9_SW + 0x194)
#define AR9_SW_RA_1B_18 (AR9_SW + 0x198)
#define AR9_SW_RA_1F_1C (AR9_SW + 0x19C)
#define AR9_SW_RA_23_20 (AR9_SW + 0x1A0)
#define AR9_SW_RA_27_24 (AR9_SW + 0x1A4)
#define AR9_SW_RA_2B_28 (AR9_SW + 0x1A8)
#define AR9_SW_RA_2F_2C (AR9_SW + 0x1AC)
#define AR9_SW_F0 (AR9_SW + 0x1B0)
#define AR9_SW_F1 (AR9_SW + 0x1B4)
#define REG32(addr) *((volatile u32 *)(addr))

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package/uboot-lantiq/files/include/asm-mips/danube.h
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package/uboot-lantiq/files/include/configs/arcadyan-common.h
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/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file contains the configuration parameters for the Danube reference board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
#define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */
#define CONFIG_USE_DDR_RAM
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
#ifdef CONFIG_SYS_RAMBOOT
//#warning CONFIG_SYS_RAMBOOT
#define CONFIG_SKIP_LOWLEVEL_INIT
#else /* CONFIG_SYS_RAMBOOT */
#define CONFIG_SYS_EBU_BOOT
#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
#endif /* CONFIG_SYS_RAMBOOT */
#if 1
#ifndef CPU_CLOCK_RATE
#define CPU_CLOCK_RATE (ifx_get_cpuclk())
#endif
#endif
#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
/*
* Include common defines/options for all Infineon boards
*/
#include "ifx-common.h"
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ram_addr=0x80500000\0" \
"kernel_addr=0xb0020000\0" \
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath} \0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off\0" \
"addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \
"console=ttyS1,115200 ethaddr=${ethaddr} " \
"${mtdparts}\0" \
"flash_flash=run flashargs addip addmisc;" \
"bootm ${kernel_addr}\0" \
"flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \
"net_flash=run load_kernel flashargs addip addmisc;" \
"bootm ${ram_addr}\0" \
"net_nfs=run load_kernel nfsargs addip addmisc;" \
"bootm ${ram_addr}\0" \
"load_kernel=tftp ${ram_addr} " \
"${tftppath}openwrt-ifxmips-uImage\0" \
"update_uboot=tftp 0x80500000 ${tftppath}u-boot-" CONFIG_ARCADYAN ".bin;era 0xb0000000 +${filesize};" \
"cp.b 0x80500000 0xb0000000 ${filesize}\0" \
"update_openwrt=tftp ${ram_addr} " \
"${tftppath}" CONFIG_ARCADYAN "-squashfs.image;" \
"era ${kernel_addr} +${filesize};" \
"cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
/*
* Cache Configuration (cpu/chip specific, Danube)
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
#define CONFIG_NET_MULTI
#define CONFIG_IFX_ETOP
//#define CLK_OUT2_25MHZ
#define CONFIG_MII
#undef CONFIG_CMD_MII
#define CONFIG_IFX_ASC
#ifdef CONFIG_USE_ASC0
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
#else
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
#endif
#ifdef CONFIG_SYS_RAMBOOT
/* Configuration of EBU: */
/* starting address from 0xb0000000 */
/* make the flash available from RAM boot */
# define CONFIG_EBU_ADDSEL0 0x10000031
# define CONFIG_EBU_BUSCON0 0x0001D7FF
# define CONFIG_EBU_ADDSEL1 0x14000001
# define CONFIG_EBU_BUSCON1 0x4041D7FD
#endif
#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_SERVERIP 192.168.1.101
#define CONFIG_GATEWAYIP 192.168.1.254
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_ROOTPATH "/export"
#ifdef CONFIG_BOOTSTRAP
#define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE
#define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOOTSTRAP_LZMA
//#define CONFIG_BOOTSTRAP_SERIAL
#endif
#endif /* __CONFIG_H */

17
package/uboot-lantiq/files/include/configs/arv3527P.h
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@ -1,17 +0,0 @@
#ifndef __CONFIG_H_3527
#define __CONFIG_H_3527
#define CONFIG_ARV3527 1
#define CONFIG_ARCADYAN "ARV3527P"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV3527 => "
/*#define CONFIG_BUTTON_PORT1
#define CONFIG_BUTTON_PIN 13
#define CONFIG_BUTTON_LEVEL 0
*/
#include "arcadyan-common.h"
#endif

16
package/uboot-lantiq/files/include/configs/arv4518PW.h
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@ -1,16 +0,0 @@
#ifndef __CONFIG_H_4518
#define __CONFIG_H_4518
#define CONFIG_ARV4518 1
#define CONFIG_ARCADYAN "ARV4518PW"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV4518 => "
//#define CONFIG_RMII 1
#define CONFIG_RTL8306_SWITCH 1
#include "arcadyan-common.h"
#endif

21
package/uboot-lantiq/files/include/configs/arv4519PW.h
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@ -1,21 +0,0 @@
#ifndef __CONFIG_H_4519
#define __CONFIG_H_4519
#define CONFIG_ARV4519 1
#define CONFIG_ARCADYAN "ARV4519PW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV4519 => "
#define CONFIG_AR8216_SWITCH 1
#define CONFIG_EBU_GPIO 0
#define CONFIG_SWITCH_PORT0
#define CONFIG_SWITCH_PIN 13
#define CONFIG_BUTTON_PORT1
#define CONFIG_BUTTON_PIN 12
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

20
package/uboot-lantiq/files/include/configs/arv4520PW.h
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@ -1,20 +0,0 @@
#ifndef __CONFIG_H_4520
#define __CONFIG_H_4520
#define CONFIG_ARV4520 1
#define CONFIG_ARCADYAN "ARV4520PW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV4520 => "
#define CONFIG_RMII 1
#define CONFIG_ADM6996_SWITCH 1
#define CONFIG_EBU_GPIO 0x400
#define CONFIG_BUTTON_PORT0
#define CONFIG_BUTTON_PIN 11
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

18
package/uboot-lantiq/files/include/configs/arv4525PW.h
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@ -1,18 +0,0 @@
#ifndef __CONFIG_H_4525
#define __CONFIG_H_4525
#define CONFIG_ARV4525 1
#define CONFIG_ARCADYAN "ARV4525PW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV4525 => "
#define CONFIG_BUTTON_PORT1
#define CONFIG_BUTTON_PIN 13
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

20
package/uboot-lantiq/files/include/configs/arv452CPW.h
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@ -1,20 +0,0 @@
#ifndef __CONFIG_H_452C
#define __CONFIG_H_452C
#define CONFIG_ARV452C 1
#define CONFIG_ARCADYAN "ARV452CPW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV452c => "
#define CONFIG_RMII 1
#define CONFIG_RTL8306_SWITCH 1
#define CONFIG_EBU_GPIO 0xf00
#define CONFIG_BUTTON_PORT0
#define CONFIG_BUTTON_PIN 11
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

16
package/uboot-lantiq/files/include/configs/arv7518PW.h
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@ -1,16 +0,0 @@
#ifndef __CONFIG_H_7518
#define __CONFIG_H_7518
#define CONFIG_ARV7518 1
#define CONFIG_ARCADYAN "ARV7518PW"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV7518 => "
//#define CONFIG_RMII 1
#define CONFIG_AR8216_SWITCH 1
#include "arcadyan-common.h"
#endif

18
package/uboot-lantiq/files/include/configs/arv7525PW.h
View File

@ -1,18 +0,0 @@
#ifndef __CONFIG_H_7525PW
#define __CONFIG_H_7525PW
#define CONFIG_ARV7525 1
#define CONFIG_ARCADYAN "ARV7525PW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV7525 => "
#define CONFIG_BUTTON_PORT1
#define CONFIG_BUTTON_PIN 13
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

19
package/uboot-lantiq/files/include/configs/arv752DPW.h
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@ -1,19 +0,0 @@
#ifndef __CONFIG_H_752DPW
#define __CONFIG_H_752DPW
#define CONFIG_ARV752DPW 1
#define CONFIG_ARCADYAN "ARV752DPW"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV752DPW => "
#define CONFIG_RMII
#define CONFIG_RTL8306G_SWITCH 1
//#define CONFIG_EBU_GPIO 0x2
//#define CONFIG_BUTTON_PORT0
//#define CONFIG_BUTTON_PIN 12
#include "arcadyan-common.h"
#endif

21
package/uboot-lantiq/files/include/configs/arv752DPW22.h
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@ -1,21 +0,0 @@
#ifndef __CONFIG_H_752DPW22
#define __CONFIG_H_752DPW22
#define CONFIG_ARV752DPW22 1
#define CONFIG_ARCADYAN "ARV752DPW22"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV752DPW22 => "
#define CONFIG_AR8216_SWITCH 1
#define CONFIG_EBU_GPIO 0x2
#define CONFIG_SWITCH_PORT1
#define CONFIG_SWITCH_PIN 3
#define CONFIG_BUTTON_PORT0
#define CONFIG_BUTTON_PIN 13
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

117
package/uboot-lantiq/files/include/configs/easy50712.h
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@ -1,117 +0,0 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file contains the configuration parameters for the Danube reference board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* #define DEBUG */
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
#define CONFIG_EASY50712 1 /* on the Danube Reference Board */
#define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
#ifdef CONFIG_SYS_RAMBOOT
//#warning CONFIG_SYS_RAMBOOT
#define CONFIG_SKIP_LOWLEVEL_INIT
#else /* CONFIG_SYS_RAMBOOT */
#define CONFIG_SYS_EBU_BOOT
#ifdef CONFIG_USE_DDR_RAM
/* FIXME: should not need these workarounds */
#define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */
#endif
#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
#endif /* CONFIG_SYS_RAMBOOT */
#if 1
#ifndef CPU_CLOCK_RATE
#define CPU_CLOCK_RATE (ifx_get_cpuclk())
#endif
#endif
#define CONFIG_SYS_PROMPT "DANUBE => " /* Monitor Command Prompt */
#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
/*
* Include common defines/options for all Infineon boards
*/
#include "ifx-common.h"
/*
* Cache Configuration (cpu/chip specific, Danube)
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
#define CONFIG_NET_MULTI
#if 0
#define CONFIG_M4530_ETH
#define CONFIG_M4530_FPGA
#endif
#define CONFIG_IFX_ETOP
#define CLK_OUT2_25MHZ
#define CONFIG_EXTRA_SWITCH
#define CONFIG_RMII /* use interface in RMII mode */
#define CONFIG_MII
#define CONFIG_CMD_MII
#define CONFIG_IFX_ASC
#ifdef CONFIG_USE_ASC0
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
#else
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
#endif
#ifdef CONFIG_SYS_RAMBOOT
/* Configuration of EBU: */
/* starting address from 0xb0000000 */
/* make the flash available from RAM boot */
# define CONFIG_EBU_ADDSEL0 0x10000031
# define CONFIG_EBU_BUSCON0 0x0001D7FF
#endif
#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
#endif /* __CONFIG_H */

104
package/uboot-lantiq/files/include/configs/easy50812.h
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@ -1,104 +0,0 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file contains the configuration parameters for the Danube reference board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* #define DEBUG */
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
#define CONFIG_MIPS34KC 1 /* MIPS 34Kc CPU core */
#define CONFIG_AR9 1 /* an AR9 device */
#define CONFIG_EASY50812 1 /* on the AR9 reference board */
#define CONFIG_SYS_MAX_RAM 32*1024*1024 /* 32 MB */
#define CONFIG_FLASH_CFI_DRIVER 1 /* using CFI flash driver */
#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
/* use PPL1 and fixed values for CPU / DDR and bus speed */
#define CONFIG_USE_PLL1
#define CONFIG_CPU_333M_RAM_166M
#define CONFIG_CLASS_II_DDR_PAD
#ifdef CONFIG_SYS_RAMBOOT
#define CONFIG_SKIP_LOWLEVEL_INIT /* no cache */
#else
#define CONFIG_SYS_EBU_BOOT
#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
#endif
#ifndef CPU_CLOCK_RATE
#define CPU_CLOCK_RATE (ifx_get_cpuclk())
#endif
#define CONFIG_SYS_PROMPT "AR9 => " /* Monitor Command Prompt */
#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
/*
* Include common defines/options for all Lantiq boards
*/
#include "ifx-common.h"
/*
* Cache Configuration (cpu/chip specific, ar9)
*/
#define CONFIG_SYS_DCACHE_SIZE (16384)
#define CONFIG_SYS_ICACHE_SIZE (16384)
#define CONFIG_SYS_CACHELINE_SIZE (32)
#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
#define CONFIG_NET_MULTI
#if 0
#define CONFIG_M4530_ETH
#define CONFIG_M4530_FPGA
#endif
#define CONFIG_IFX_ETOP /* lantiq ethernet cpe interface */
#define CLK_OUT2_25MHZ
#define CONFIG_EXTRA_SWITCH /* search for external switches like tantos */
#define CONFIG_RMII /* use interface in RMII mode */
#define CONFIG_MII
#define CONFIG_CMD_MII /* enable MII command */
#define CONFIG_IFX_ASC /* use lantiq ASC driver */
#ifdef CONFIG_USE_ASC0
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
#else
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
#endif
#ifdef CONFIG_SYS_RAMBOOT
/* Configuration of EBU: */
/* starting address from 0xb0000000 */
/* make the flash available from RAM boot */
# define CONFIG_EBU_ADDSEL0 0x10000031
# define CONFIG_EBU_BUSCON0 0x0001D7FF
#endif
#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
#endif /* __CONFIG_H */

192
package/uboot-lantiq/files/include/configs/ifx-common.h
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@ -1,192 +0,0 @@
/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Common configuration options for all AMCC boards
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IFX_COMMON_H
#define __IFX_COMMON_H
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
#define CONFIG_BAUDRATE 115200
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#undef CONFIG_PREBOOT
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ram_addr=0x80500000\0" \
"kernel_addr=0xb0020000\0" \
"mtdparts=mtdparts=ifx-nor:256k(uboot)ro,64k(uboot_env)ro,64k(kernel),-(rootfs)\0" \
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath} \0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off\0" \
"addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \
"console=ttyS1,115200 ethaddr=${ethaddr} " \
"${mtdparts}\0" \
"flash_flash=run flashargs addip addmisc;" \
"bootm ${kernel_addr}\0" \
"flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \
"net_flash=run load_kernel flashargs addip addmisc;" \
"bootm ${ram_addr}\0" \
"net_nfs=run load_kernel nfsargs addip addmisc;" \
"bootm ${ram_addr}\0" \
"load_kernel=tftp ${ram_addr} " \
"${tftppath}openwrt-ifxmips-uImage\0" \
"update_uboot=tftp 0x80500000 ${tftppath}u-boot.bin;era 0xb0000000 +${filesize};" \
"cp.b 0x80500000 0xb0000000 ${filesize}\0" \
"update_openwrt=tftp ${ram_addr} " \
"${tftppath}openwrt-ifxmips-squashfs.image;" \
"era ${kernel_addr} +${filesize};" \
"cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
#define CONFIG_BOOTCOMMAND "run flash_flash"
/*
* TFTP is using fragmented packets
*/
#define CONFIG_IP_DEFRAG
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_IMI
#undef CONFIG_CMD_PING
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
#undef CONFIG_SYS_HUSH_PARSER
/*
* Miscellaneous configurable options
*/
#define CONFIG_LZMA
#undef CONFIG_SYS_LONGHELP /* undef to save memory */
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_MALLOC_LEN 1024*1024
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE/2)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x80800000
#define CONFIG_CMDLINE_EDITING /* add command line history */
#undef CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT (140) /* max number of sectors on one chip */
#define PHYS_FLASH_1 0xB0000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0xB0800000 /* Flash Bank #2 */
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_IS_IN_FLASH 1
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_ADDR 0xB0010000
#define CONFIG_ENV_SIZE 0x10000
#ifdef CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_SWAP_ADDR
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define FLASH_FIXUP_ADDR_8(addr) ((void*)((ulong)(addr)^2))
#define FLASH_FIXUP_ADDR_16(addr) ((void*)((ulong)(addr)^2))
#endif
#define CONFIG_NR_DRAM_BANKS 1
#ifdef CONFIG_SYS_EBU_BOOT
#ifndef INFINEON_EBU_BOOTCFG
#error Please define INFINEON_EBU_BOOTCFG
#endif
#endif
#ifdef CONFIG_BOOTSTRAP
#define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE
#define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOOTSTRAP_LZMA
//#define CONFIG_BOOTSTRAP_SERIAL
#endif
#endif /* __IFX_COMMON_H */

165
package/uboot-lantiq/gct
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@ -1,165 +0,0 @@
#!/usr/bin/perl
#use strict;
#use Cwd;
#use Env;
my $aline;
my $lineid;
my $length;
my $address;
my @bytes;
my $addstr;
my $chsum=0;
my $count=0;
my $firstime=1;
my $i;
my $currentaddr;
my $tmp;
my $holder="";
my $loadaddr;
if(@ARGV < 2){
die("\n Syntax: ./program_SDRAM input1(memory setup) input2(*\.srec) output\n");
}
open(INFILE1, "<$ARGV[0]") || die("\ninput1 open fail\n");
open(INFILE2, "<$ARGV[1]") || die("\ninput2 open fail\n");
open(OUTFILE, ">$ARGV[2]") || die("\nOutput file open fail\n");
$i=0;
while ($line = <INFILE1>){
if($line=~/\w/){
if($line!~/[;#\*]/){
if($i eq 0){
printf OUTFILE ("33333333");
}
chomp($line);
$line=~s/\t//;
@array=split(/ +/,$line);
$j=0;
while(@array[$j]!~/\w/){
$j=$j+1;
}
$addr=@array[$j];
$regval=@array[$j+1];
$addr=~s/0x//;
$regval=~s/0x//;
printf OUTFILE ("%08x%08x",hex($addr),hex($regval));
$i=$i+1;
if($i eq 8){
$i=0;
printf OUTFILE ("\n");
}
}
}
}
while($i lt 8 && $i gt 0){
printf OUTFILE "00"x8;
$i=$i+1;
}
if($i eq 8){
printf OUTFILE ("\n");
}
while($aline=<INFILE2>){
$aline=uc($aline);
chomp($aline);
next if(($aline=~/^S0/) || ($aline=~/^S7/));
($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline;
$length = hex($length);
$address = hex($address);
$length -=5;
$i=0;
while($length>0){
if($firstime==1){
$addstr = sprintf("%x", $address);
$addstr = "0"x(8-length($addstr)).$addstr;
print OUTFILE $addstr;
addchsum($addstr);
$firstime=0;
$currentaddr=$address;
$loadaddr = $addstr;
}
else{
if($count==64){
$addstr = sprintf("%x", $currentaddr);
$addstr = "0"x(8-length($addstr)).$addstr;
print OUTFILE $addstr;
addchsum($addstr);
$count=0;
}
#printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr;
}
if($currentaddr < $address) {
print OUTFILE "00";
addchsum("00");
$count++;
$currentaddr++;
}
else {
while($count<64){
$bytes[$i]=~tr/ABCDEF/abcdef/;
print OUTFILE "$bytes[$i]";
addchsum($bytes[$i]);
$i++;
$count++;
$currentaddr++;
$length--;
last if($length==0);
}
}
if($count==64){
print OUTFILE "\n";
#print OUTFILE "\r";
}
}
}
if($count != 64){
$tmp = "00";
for($i=0;$i<(64-$count);$i++){
print OUTFILE "00";
addchsum($tmp);
}
print OUTFILE "\n";
#print OUTFILE "\r";
}
print OUTFILE "11"x4;
use integer;
$chsum=$chsum & 0xffffffff;
$chsum = sprintf("%X", $chsum);
$chsum = "0"x(8-length($chsum)).$chsum;
$chsum =~tr/ABCDEF/abcdef/;
print OUTFILE $chsum;
print OUTFILE "00"x60;
print OUTFILE "\n";
#print OUTFILE "\r";
print OUTFILE "99"x4;
print OUTFILE $loadaddr;
print OUTFILE "00"x60;
print OUTFILE "\n";
#print OUTFILE "\r";
close OUTFILE;
#END of Program
sub addchsum{
my $cc=$_[0];
$holder=$holder.$cc;
if(length($holder)==8){
$holder = hex($holder);
$chsum+=$holder;
$holder="";
}
}
#END

60
package/uboot-lantiq/patches/000-build-infos.patch
View File

@ -1,60 +0,0 @@
Add output like in linux kernel for current compiled file
Used normaly in combination with make option -s
Like in following example:
$ make -s V=1
[CC] tools/img2srec.c
[CC] tools/bmp_logo.c
[CC] examples/hello_world.c
--- a/config.mk
+++ b/config.mk
@@ -234,17 +234,47 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATF
#########################################################################
+ifndef KBUILD_VERBOSE
+ KBUILD_VERBOSE:=0
+endif
+ifeq ("$(origin V)", "command line")
+ KBUILD_VERBOSE:=$(V)
+endif
+ifeq (,$(findstring s,$(MAKEFLAGS)))
+ KBUILD_VERBOSE:=0
+endif
+
+ifneq ($(KBUILD_VERBOSE),0)
+ define MESSAGE
+ @printf " %s %s/%s\n" $(1) $(2) $(3)
+ endef
+else
+ define MESSAGE
+ endef
+endif
+
# Allow boards to use custom optimize flags on a per dir/file basis
BCURDIR := $(notdir $(CURDIR))
+
$(obj)%.s: %.S
+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $<
$(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $<
$(obj)%.o: %.S
+ $(call MESSAGE, [AS], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c
$(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.o: %.c
+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.i: %.c
+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.s: %.c
+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S
$(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S
#########################################################################

25
package/uboot-lantiq/patches/010-fix-mips-flags.patch
View File

@ -1,25 +0,0 @@
--- a/cpu/mips/config.mk
+++ b/cpu/mips/config.mk
@@ -23,17 +23,19 @@
v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
MIPSFLAGS:=$(shell \
if [ "$v" -lt "14" ]; then \
- echo "-mcpu=4kc"; \
+ echo "-mcpu=mips32"; \
else \
- echo "-march=4kc -mtune=4kc"; \
+ echo "-mips32 -march=mips32 -mtune=mips32"; \
fi)
+ifndef ENDIANNESS
ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
ENDIANNESS = -EL
else
ENDIANNESS = -EB
endif
+endif
-MIPSFLAGS += $(ENDIANNESS)
+MIPSFLAGS += $(ENDIANNESS) -fno-schedule-insns -fno-schedule-insns2
PLATFORM_CPPFLAGS += $(MIPSFLAGS)

124
package/uboot-lantiq/patches/020-mips-enhancements.patch
View File

@ -1,124 +0,0 @@
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -69,6 +69,9 @@ _start:
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+#elif defined(CONFIG_SYS_EBU_BOOT)
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word 0x00000000 /* phase of the flash */
#else
RVECENT(romReserved,2)
#endif
@@ -202,7 +205,25 @@ _start:
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
-#ifdef CONFIG_PURPLE
+#ifndef CONFIG_PURPLE
+ XVECENT(romExcHandle,0x400); /* bfc00400: Int, CauseIV=1 */
+ RVECENT(romReserved,129);
+ RVECENT(romReserved,130);
+ RVECENT(romReserved,131);
+ RVECENT(romReserved,132);
+ RVECENT(romReserved,133);
+ RVECENT(romReserved,134);
+ RVECENT(romReserved,135);
+ RVECENT(romReserved,136);
+ RVECENT(romReserved,137);
+ RVECENT(romReserved,138);
+ RVECENT(romReserved,139);
+ RVECENT(romReserved,140);
+ RVECENT(romReserved,141);
+ RVECENT(romReserved,142);
+ RVECENT(romReserved,143);
+ XVECENT(romExcHandle,0x480); /* bfc00480: EJTAG debug exception */
+#else /* CONFIG_PURPLE */
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
@@ -228,6 +249,12 @@ _start:
#endif /* CONFIG_PURPLE */
.align 4
reset:
+#ifdef CONFIG_SYS_MIPS_MULTI_CPU
+ mfc0 k0, CP0_EBASE
+ and k0, EBASEF_CPUNUM
+ bne k0, zero, ifx_mips_handler_cpux
+ nop
+#endif
/* Clear watch registers.
*/
@@ -239,6 +266,16 @@ reset:
setup_c0_status_reset
+#if defined(CONFIG_MIPS24KEC) || defined(CONFIG_MIPS34KC)
+ /* CONFIG7 register */
+ /* Erratum "RPS May Cause Incorrect Instruction Execution"
+ * for 24KEC and 34KC */
+ mfc0 k0, CP0_CONFIG, 7
+ li k1, MIPS_CONF7_RPS
+ or k0, k1
+ mtc0 k0, CP0_CONFIG, 7
+#endif
+
/* Init Timer */
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
@@ -270,9 +307,12 @@ reset:
jalr t9
nop
+#ifndef CONFIG_SYS_MIPS_CACHE_OPER_MODE
+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
/* ... and enable them.
*/
- li t0, CONF_CM_CACHABLE_NONCOHERENT
+ li t0, CONFIG_SYS_MIPS_CACHE_OPER_MODE
mtc0 t0, CP0_CONFIG
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
@@ -419,3 +459,15 @@ romReserved:
romExcHandle:
b romExcHandle
+
+ /* Additional handlers.
+ */
+#ifdef CONFIG_SYS_MIPS_MULTI_CPU
+/*
+ * Stop Slave CPUs
+ */
+ifx_mips_handler_cpux:
+ wait;
+ b ifx_mips_handler_cpux;
+ nop;
+#endif
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -57,6 +57,7 @@
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
+#define CP0_EBASE $15,1
#define CP0_CONFIG $16
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
@@ -395,6 +396,14 @@
#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
+ * Bits in the coprocessor 0 EBase register
+ */
+#define EBASEB_CPUNUM 0
+#define EBASEF_CPUNUM (0x3ff << EBASEB_CPUNUM)
+#define EBASEB_EXPBASE 12
+#define EBASEF_EXPBASE (0x3ffff << EBASEB_EXPBASE)
+
+/*
* Bits in the coprocessor 0 config register.
*/
/* Generic bits. */

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