bcm53xx: backport DT changes from 5.17 & 5.18

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki 2022-03-30 16:05:55 +02:00
parent 8822a8d850
commit a721fb9f83
9 changed files with 471 additions and 1 deletions

View File

@ -1,5 +1,6 @@
From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Tue, 23 Nov 2021 09:55:06 +0100
Date: Tue, 23 Nov 2021 10:03:33 +0100
Subject: [PATCH] ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
@ -10,6 +11,7 @@ register.
References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)

View File

@ -0,0 +1,42 @@
From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001
From: Florian Fainelli <f.fainelli@gmail.com>
Date: Thu, 2 Dec 2021 15:16:27 -0800
Subject: [PATCH] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node
Rename the msi controller unit name to 'msi' to avoid collisions with
the 'msi-controller' boolean property.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -587,7 +587,7 @@
status = "disabled";
msi-parent = <&msi0>;
- msi0: msi-controller {
+ msi0: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
@@ -624,7 +624,7 @@
status = "disabled";
msi-parent = <&msi1>;
- msi1: msi-controller {
+ msi1: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
@@ -661,7 +661,7 @@
status = "disabled";
msi-parent = <&msi2>;
- msi2: msi-controller {
+ msi2: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;

View File

@ -0,0 +1,25 @@
From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001
From: Florian Fainelli <f.fainelli@gmail.com>
Date: Tue, 7 Dec 2021 10:19:09 -0800
Subject: [PATCH] ARM: dts: NSP: Rename SATA unit name
Rename the SATA controller unit name from ahci to sata in preparation
for adding the Broadcom SATA3 controller YAML binding which will bring
validation.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -534,7 +534,7 @@
};
};
- sata: ahci@41000 {
+ sata: sata@41000 {
compatible = "brcm,bcm-nsp-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0x41000 0x1000>, <0x40020 0x1c>;

View File

@ -0,0 +1,45 @@
From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
Date: Fri, 17 Dec 2021 00:03:19 +0800
Subject: [PATCH] ARM: dts: BCM5301X: correct RX delay and enable flow control
on Asus RT-AC88U
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The current 'rx-internal-delay-ps' property value on the Realtek switch
node, 2000, will be divided by 300, resulting in 6.66, which will be
rounded to the closest step value, 7. Change it to 2100 to be accurate.
See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of
0.3 ns") for reference.
Flow control needs to be enabled on both sides of the internal and
external switch. It is already enabled on the CPU port of the Realtek
switch so we also enable it on the external switch port of the Broadcom
switch as well.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
@@ -138,7 +138,7 @@
ethernet = <&sw0_p5>;
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
- rx-internal-delay-ps = <2000>;
+ rx-internal-delay-ps = <2100>;
fixed-link {
speed = <1000>;
@@ -213,6 +213,7 @@
fixed-link {
speed = <1000>;
full-duplex;
+ pause;
};
};

View File

@ -0,0 +1,109 @@
From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 23 Dec 2021 00:17:17 +0100
Subject: [PATCH] Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus
RT-AC88U"
This reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused
a build regression:
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 --------------------
1 file changed, 77 deletions(-)
--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
@@ -93,83 +93,6 @@
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
};
-
- switch {
- compatible = "realtek,rtl8365mb";
- /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
- mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
- mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
- realtek,disable-leds;
- dsa,member = <1 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan5";
- phy-handle = <&ethphy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "lan6";
- phy-handle = <&ethphy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan7";
- phy-handle = <&ethphy2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan8";
- phy-handle = <&ethphy3>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&sw0_p5>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <2000>;
- rx-internal-delay-ps = <2100>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- };
-
- mdio {
- compatible = "realtek,smi-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- };
-
- ethphy3: ethernet-phy@3 {
- reg = <3>;
- };
- };
- };
};
&srab {

View File

@ -0,0 +1,103 @@
From 441d531ec9b766f49e01c107a3043235daa4493f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
Date: Sun, 2 Jan 2022 23:33:04 +0300
Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Define the Realtek RTL8365MB switch without interrupt support on the device
tree of Asus RT-AC88U.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 76 ++++++++++++++++++++
1 file changed, 76 insertions(+)
--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
@@ -93,6 +93,82 @@
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
};
+
+ switch {
+ compatible = "realtek,rtl8365mb";
+ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
+ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
+ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+ realtek,disable-leds;
+ dsa,member = <1 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan5";
+ phy-handle = <&ethphy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan6";
+ phy-handle = <&ethphy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan7";
+ phy-handle = <&ethphy2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan8";
+ phy-handle = <&ethphy3>;
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&sw0_p5>;
+ phy-mode = "rgmii";
+ tx-internal-delay-ps = <2000>;
+ rx-internal-delay-ps = <2100>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+
+ mdio {
+ compatible = "realtek,smi-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+ };
};
&srab {

View File

@ -0,0 +1,40 @@
From 66848aff05f669e95795b5f3a163f4762781333e Mon Sep 17 00:00:00 2001
From: Matthew Hagan <mnhagan88@gmail.com>
Date: Wed, 23 Feb 2022 23:50:39 +0000
Subject: [PATCH] ARM: dts: NSP: MX6X: get mac-address from eeprom
The MAC address on the MX64/MX65 series is located on the AT24 EEPROM.
This is the same as other Meraki devices such as the MR32 [1].
[1] https://lore.kernel.org/linux-arm-kernel/fa8271d02ef74a687f365cebe5c55ec846963ab7.1631986106.git.chunkeey@gmail.com/
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
@@ -39,6 +39,8 @@
&amac2 {
status = "okay";
+ nvmem-cells = <&mac_address>;
+ nvmem-cell-names = "mac-address";
};
&ehci0 {
@@ -53,6 +55,12 @@
reg = <0x50>;
pagesize = <32>;
read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac_address: mac-address@66 {
+ reg = <0x66 0x6>;
+ };
};
};

View File

@ -0,0 +1,62 @@
From 482c85c7fc95c572d368b2214b9e9d2c4a2e5789 Mon Sep 17 00:00:00 2001
From: Matthew Hagan <mnhagan88@gmail.com>
Date: Wed, 23 Feb 2022 23:50:40 +0000
Subject: [PATCH] ARM: dts: NSP: MX6X: correct LED function types
Currently, the amber LED will remain always on. This is due to a
misinterpretation of the LED sub-node properties, where-by "default-state"
was used to indicate the initial state when powering on the device. When in
use, however, this resulted in the amber LED always being on. Instead change
this to only indicate a fault state.
Assign LED_FUNCTION_POWER to the green PWM LED.
These changes bring the MX64/65 in line with the MR32's devicetree.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 3 +--
arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi | 3 +--
arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +-
3 files changed, 3 insertions(+), 5 deletions(-)
--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
@@ -57,10 +57,9 @@
led-4 {
/* amber:power */
- function = LED_FUNCTION_POWER;
+ function = LED_FUNCTION_FAULT;
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
- default-state = "on";
};
led-5 {
--- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
@@ -106,10 +106,9 @@
led-a {
/* amber:power */
- function = LED_FUNCTION_POWER;
+ function = LED_FUNCTION_FAULT;
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
- default-state = "on";
};
led-b {
--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
@@ -22,7 +22,7 @@
};
led-2 {
- function = LED_FUNCTION_INDICATOR;
+ function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
pwms = <&pwm 2 50000>;
max-brightness = <255>;

View File

@ -0,0 +1,42 @@
From c8442f0fb09ca3d842b9b23d1d0650f649fd10f8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Mon, 28 Feb 2022 10:52:07 +0100
Subject: [PATCH] ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul
XWR-3150
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Luxul XWR-3150 stores MAC as NVRAM variable. Add NVMEM cell for it and
reference it in the Ethernet interface node.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
@@ -25,6 +25,9 @@
nvram@1eff0000 {
compatible = "brcm,nvram";
reg = <0x1eff0000 0x10000>;
+
+ et0macaddr: et0macaddr {
+ };
};
leds {
@@ -72,6 +75,11 @@
};
};
+&gmac0 {
+ nvmem-cells = <&et0macaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
&usb3 {
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
};