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mediatek: update patches
adds a few ethernet fixes Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 49132
This commit is contained in:
John Crispin
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8b8dfeb027
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From c30a296646a42302065ba452abe95b0b4b550883 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 27 Jul 2014 09:38:50 +0100
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Subject: [PATCH 01/78] NET: multi phy support
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Subject: [PATCH 01/81] NET: multi phy support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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From 2c93328ed05061a50e3bd4111379dbcf6946d3ac Mon Sep 17 00:00:00 2001
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From: James Liao <jamesjj.liao@mediatek.com>
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Date: Wed, 30 Dec 2015 14:41:43 +0800
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Subject: [PATCH 02/78] soc: mediatek: Separate scpsys driver common code
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Subject: [PATCH 02/81] soc: mediatek: Separate scpsys driver common code
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Separate scpsys driver common code to mtk-scpsys.c, and move MT8173
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platform code to mtk-scpsys-mt8173.c.
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From c359272f86805259c5801385d60fdeea9d629cf9 Mon Sep 17 00:00:00 2001
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From: James Liao <jamesjj.liao@mediatek.com>
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Date: Wed, 30 Dec 2015 14:41:44 +0800
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Subject: [PATCH 03/78] soc: mediatek: Init MT8173 scpsys driver earlier
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Subject: [PATCH 03/81] soc: mediatek: Init MT8173 scpsys driver earlier
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Some power domain comsumers may init before module_init.
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So the power domain provider (scpsys) need to be initialized
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From f371844374fff273f817d6c43f679606417af59e Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Wed, 30 Dec 2015 14:41:45 +0800
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Subject: [PATCH 04/78] soc: mediatek: Add MT2701 power dt-bindings
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Subject: [PATCH 04/81] soc: mediatek: Add MT2701 power dt-bindings
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Add power dt-bindings for MT2701.
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From c6711565985f359d7d3c05f01f081e4c216902de Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Wed, 30 Dec 2015 14:41:46 +0800
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Subject: [PATCH 05/78] soc: mediatek: Add MT2701/MT7623 scpsys driver
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Subject: [PATCH 05/81] soc: mediatek: Add MT2701/MT7623 scpsys driver
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Add scpsys driver for MT2701 and MT7623.
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From 0c39bcd17fa6ce723f56ad3756b4bb36c4690342 Mon Sep 17 00:00:00 2001
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From: James Liao <jamesjj.liao@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:17 +0800
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Subject: [PATCH 06/78] clk: mediatek: Refine the makefile to support multiple
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Subject: [PATCH 06/81] clk: mediatek: Refine the makefile to support multiple
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clock drivers
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Add a Kconfig to define clock configuration for each SoC, and
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From d7e96f87f66c571e9f4171ecd89c656fbd2de89b Mon Sep 17 00:00:00 2001
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From: James Liao <jamesjj.liao@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:18 +0800
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Subject: [PATCH 07/78] dt-bindings: ARM: Mediatek: Document bindings for
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Subject: [PATCH 07/81] dt-bindings: ARM: Mediatek: Document bindings for
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MT2701
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This patch adds the binding documentation for apmixedsys, bdpsys,
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From 2fcbc15da2f13164e0851b9c7fae290249f0b44d Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:19 +0800
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Subject: [PATCH 08/78] clk: mediatek: Add dt-bindings for MT2701 clocks
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Subject: [PATCH 08/81] clk: mediatek: Add dt-bindings for MT2701 clocks
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Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
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infracfg, pericfg and subsystem clocks.
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From f2c07eaa2df52f9acac9ffc3457d3d81079dd723 Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:20 +0800
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Subject: [PATCH 09/78] clk: mediatek: Add MT2701 clock support
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Subject: [PATCH 09/81] clk: mediatek: Add MT2701 clock support
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Add MT2701 clock support, include topckgen, apmixedsys,
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infracfg, pericfg and subsystem clocks.
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From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:21 +0800
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Subject: [PATCH 10/78] reset: mediatek: mt2701 reset controller dt-binding
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Subject: [PATCH 10/81] reset: mediatek: mt2701 reset controller dt-binding
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file
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Dt-binding file about reset controller is used to provide
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From b86d3303db25a8296e4c3de46ee1470f60f71b0c Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:22 +0800
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Subject: [PATCH 11/78] reset: mediatek: mt2701 reset driver
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Subject: [PATCH 11/81] reset: mediatek: mt2701 reset driver
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In infrasys and perifsys, there are many reset
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control bits for kinds of modules. These bits are
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From 3b5df542d52b13a1b20d25311fa4c4029a3b83af Mon Sep 17 00:00:00 2001
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From: Erin Lo <erin.lo@mediatek.com>
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Date: Mon, 28 Dec 2015 15:09:02 +0800
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Subject: [PATCH 12/78] ARM: mediatek: Add MT2701 config options for mediatek
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Subject: [PATCH 12/81] ARM: mediatek: Add MT2701 config options for mediatek
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SoCs.
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The upcoming MTK pinctrl driver have a big pin table for each SoC
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From 1a254735cad9db5c8605c972b0f16b3929dc0d6e Mon Sep 17 00:00:00 2001
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From: Biao Huang <biao.huang@mediatek.com>
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Date: Mon, 28 Dec 2015 15:09:03 +0800
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Subject: [PATCH 13/78] dt-bindings: mediatek: Modify pinctrl bindings for
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Subject: [PATCH 13/81] dt-bindings: mediatek: Modify pinctrl bindings for
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mt2701
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Signed-off-by: Biao Huang <biao.huang@mediatek.com>
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From 416720ba33d4fd7d3166c17be7c13651cc08d408 Mon Sep 17 00:00:00 2001
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From: Biao Huang <biao.huang@mediatek.com>
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Date: Mon, 28 Dec 2015 15:09:04 +0800
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Subject: [PATCH 14/78] pinctrl: dt bindings: Add pinfunc header file for
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Subject: [PATCH 14/81] pinctrl: dt bindings: Add pinfunc header file for
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mt2701
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Add pinfunc header file, mt2701 related dts will include it
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From ddc72b659b3642d0496dee4e1ee39416ca008053 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 7 Jan 2016 23:42:06 +0100
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Subject: [PATCH 15/78] dt-bindings: mediatek: Modify pinctrl bindings for
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Subject: [PATCH 15/81] dt-bindings: mediatek: Modify pinctrl bindings for
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mt7623
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Signed-off-by: John Crispin <blogic@openwrt.org>
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From 1255eaacd6cc9d1fa6bb33185380efed22008baf Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 27 Jun 2015 13:13:05 +0200
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Subject: [PATCH 16/78] pinctrl: dt bindings: Add pinctrl file for mt7623
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Subject: [PATCH 16/81] pinctrl: dt bindings: Add pinctrl file for mt7623
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Add the driver and header files required to make pinctrl work on MediaTek
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MT7623.
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From 294cf90337d70ad74edf147180bbeef837298bd0 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 6 Jan 2016 20:06:49 +0100
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Subject: [PATCH 17/78] clk: add hifsys reset
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Subject: [PATCH 17/81] clk: add hifsys reset
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Hi,
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From 84d37aeef94deae3ce87e677f6016a5d980429e8 Mon Sep 17 00:00:00 2001
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From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
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Date: Tue, 17 Nov 2015 17:18:39 +0800
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Subject: [PATCH 18/78] dt-bindings: Add a binding for Mediatek xHCI host
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Subject: [PATCH 18/81] dt-bindings: Add a binding for Mediatek xHCI host
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controller
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add a DT binding documentation of xHCI host controller for the
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From 651d8fff94718c7e48b8a40d7774878eb8ed62ee Mon Sep 17 00:00:00 2001
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From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
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Date: Tue, 17 Nov 2015 17:18:40 +0800
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Subject: [PATCH 19/78] xhci: mediatek: support MTK xHCI host controller
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Subject: [PATCH 19/81] xhci: mediatek: support MTK xHCI host controller
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There some vendor quirks for MTK xhci host controller:
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1. It defines some extra SW scheduling parameters for HW
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From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
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From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
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Date: Tue, 17 Nov 2015 17:18:41 +0800
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Subject: [PATCH 20/78] arm64: dts: mediatek: add xHCI & usb phy for mt8173
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Subject: [PATCH 20/81] arm64: dts: mediatek: add xHCI & usb phy for mt8173
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add xHCI and phy drivers for MT8173-EVB
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From 162deec293400cb132161606629654acaec7cb4b Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 5 Jan 2016 12:13:54 +0100
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Subject: [PATCH 21/78] Document: DT: Add bindings for mediatek MT7623 SoC
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Subject: [PATCH 21/81] Document: DT: Add bindings for mediatek MT7623 SoC
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Platform
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This adds a DT binding documentation for the MT7623 SoC from Mediatek.
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From fa5d94d6b4b314f751b1c32bb5a87a80b866d05e Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 5 Jan 2016 16:52:31 +0100
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Subject: [PATCH 22/78] soc: mediatek: add compat string for mt7623 to scpsys
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Subject: [PATCH 22/81] soc: mediatek: add compat string for mt7623 to scpsys
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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From a4df3e7e4e906a4e9dac1f8c43f6192f22ef6242 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 5 Jan 2016 12:16:17 +0100
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Subject: [PATCH 23/78] ARM: dts: mediatek: add MT7623 basic support
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Subject: [PATCH 23/81] ARM: dts: mediatek: add MT7623 basic support
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This adds basic chip support for Mediatek MT7623.
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From 97478bae3a11b5e87d61b88267e915f7c5ddf4e9 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 6 Jan 2016 21:55:10 +0100
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Subject: [PATCH 24/78] dt-bindings: add MediaTek PCIe binding documentation
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Subject: [PATCH 24/81] dt-bindings: add MediaTek PCIe binding documentation
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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From b44b44cfdcb9b2d7ba513d24df1b16b8c57cce59 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 5 Jan 2016 20:20:04 +0100
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Subject: [PATCH 25/78] PCI: mediatek: add support for PCIe found on
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Subject: [PATCH 25/81] PCI: mediatek: add support for PCIe found on
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MT7623/MT2701
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Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
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From fe8fd85507870bf3aa5ff257944f15b50888d17c Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 21 Feb 2016 13:52:12 +0100
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Subject: [PATCH 26/78] scpsys: various fixes
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Subject: [PATCH 26/81] scpsys: various fixes
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---
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drivers/clk/mediatek/clk-mt2701.c | 2 ++
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From 2fc7dd0f48d9c2096d76562a1960b78b064701f7 Mon Sep 17 00:00:00 2001
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From: Henry Chen <henryc.chen@mediatek.com>
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Date: Mon, 4 Jan 2016 20:02:52 +0800
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Subject: [PATCH 27/78] soc: mediatek: PMIC wrap: Clear the vldclr if state
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Subject: [PATCH 27/81] soc: mediatek: PMIC wrap: Clear the vldclr if state
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machine stay on FSM_VLDCLR state.
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Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout,
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From b7d11ec865f99085a907f1a082f70404734e954c Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 5 Jan 2016 17:24:28 +0100
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Subject: [PATCH 28/78] ARM: mediatek: add MT7623 smp bringup code
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Subject: [PATCH 28/81] ARM: mediatek: add MT7623 smp bringup code
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Add support for booting secondary CPUs on MT7623.
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From 7e0c3f4f4c7a55eda670c97b1b3b793ceecc1655 Mon Sep 17 00:00:00 2001
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From: Henry Chen <henryc.chen@mediatek.com>
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Date: Thu, 21 Jan 2016 19:04:00 +0800
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Subject: [PATCH 29/78] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
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Subject: [PATCH 29/81] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
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WDT_SRC_EN
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Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout
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From 672ed0995e4ebf3f14bb58d08d6ba4c78337b90b Mon Sep 17 00:00:00 2001
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From: Louis Yu <louis.yu@mediatek.com>
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Date: Thu, 7 Jan 2016 20:09:43 +0800
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Subject: [PATCH 30/78] ARM: mediatek: add mt2701 smp bringup code
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Subject: [PATCH 30/81] ARM: mediatek: add mt2701 smp bringup code
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Add support for booting secondary CPUs on mt2701.
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From 1474be4d7f9559804671ab01911232368496a1de Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 20 Jan 2016 13:12:19 +0100
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Subject: [PATCH 31/78] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
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Subject: [PATCH 31/81] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
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the PMIC wrapper doc
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Signed-off-by: John Crispin <blogic@openwrt.org>
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From 542f2cd3287fb955efcc5ceca14b690ba19f8c57 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 20 Jan 2016 06:42:01 +0100
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Subject: [PATCH 32/78] soc: mediatek: PMIC wrap: don't duplicate the wrapper
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Subject: [PATCH 32/81] soc: mediatek: PMIC wrap: don't duplicate the wrapper
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data
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As we add support for more devices struct pmic_wrapper_type will grow and
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From 915340f70c0594d1f0717fee3eb678fa71206509 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 20 Jan 2016 05:27:17 +0100
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Subject: [PATCH 33/78] soc: mediatek: PMIC wrap: add wrapper callbacks for
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Subject: [PATCH 33/81] soc: mediatek: PMIC wrap: add wrapper callbacks for
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init_reg_clock
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Split init_reg_clock up into SoC specific callbacks. The patch also
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From b2287b0afb757870ce0f4324bb4bc597d3f90a2a Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 20 Jan 2016 10:12:00 +0100
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Subject: [PATCH 34/78] soc: mediatek: PMIC wrap: split SoC specific init into
|
||||
Subject: [PATCH 34/81] soc: mediatek: PMIC wrap: split SoC specific init into
|
||||
callback
|
||||
|
||||
This patch moves the SoC specific wrapper init code into separate callback
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 76f0c7770046ed436be085af1257e0ab06fdd41f Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 20 Jan 2016 10:14:39 +0100
|
||||
Subject: [PATCH 35/78] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
|
||||
Subject: [PATCH 35/81] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
|
||||
different bitmask for MT2701/7623
|
||||
|
||||
MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From fca1819591e7824d474c900a3524c0c1fee6a300 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 20 Jan 2016 10:21:42 +0100
|
||||
Subject: [PATCH 36/78] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
|
||||
Subject: [PATCH 36/81] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
|
||||
bitmask for MT2701/7623
|
||||
|
||||
Different SoCs will use different bitmask for the SPI_WRITE command. This
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From dfdef729324d87d40468f76f0f2767a09c9b0ab0 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 20 Jan 2016 10:48:35 +0100
|
||||
Subject: [PATCH 37/78] soc: mediatek: PMIC wrap: move wdt_src into the
|
||||
Subject: [PATCH 37/81] soc: mediatek: PMIC wrap: move wdt_src into the
|
||||
pmic_wrapper_type struct
|
||||
|
||||
Different SoCs will use different bitmask for the wdt_src. This patch
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 34d49f015488dcb3de31060846414bd4254e752a Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 20 Jan 2016 10:54:18 +0100
|
||||
Subject: [PATCH 38/78] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
|
||||
Subject: [PATCH 38/81] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
|
||||
pwrap_is_mt8173()
|
||||
|
||||
With more SoCs being added the list of helper functions like these would
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From ae593b270b87f9ed6c35dec3ac69dd6bda43c0a0 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 20 Jan 2016 09:55:08 +0100
|
||||
Subject: [PATCH 39/78] soc: mediatek: PMIC wrap: add a slave specific struct
|
||||
Subject: [PATCH 39/81] soc: mediatek: PMIC wrap: add a slave specific struct
|
||||
|
||||
This patch adds a new struct pwrap_slv_type that we use to store the slave
|
||||
specific data. The patch adds 2 new helper functions to access the dew
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 8f3597ca8c8a28d2501d03643569f0cea920c24d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 20 Jan 2016 11:40:43 +0100
|
||||
Subject: [PATCH 40/78] soc: mediatek: PMIC wrap: add mt6323 slave support
|
||||
Subject: [PATCH 40/81] soc: mediatek: PMIC wrap: add mt6323 slave support
|
||||
|
||||
Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623
|
||||
EVB. The only function that we need to touch is pwrap_init_cipher().
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 09351f7c59e08d9c259546e03af3af05c10d644c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 20 Jan 2016 12:09:14 +0100
|
||||
Subject: [PATCH 41/78] soc: mediatek: PMIC wrap: add MT2701/7623 support
|
||||
Subject: [PATCH 41/81] soc: mediatek: PMIC wrap: add MT2701/7623 support
|
||||
|
||||
Add the registers, callbacks and data structures required to make the
|
||||
wrapper work on MT2701 and MT7623.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 94f7b9dabcd073bf629268514f87e5dbd2cafd13 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 10 Jan 2016 17:12:37 +0100
|
||||
Subject: [PATCH 42/78] dt-bindings: mfd: Add bindings for the MediaTek MT6323
|
||||
Subject: [PATCH 42/81] dt-bindings: mfd: Add bindings for the MediaTek MT6323
|
||||
PMIC
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From aa90d988b627b41c774891fd72560699f30faefa Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 8 Jan 2016 08:33:17 +0100
|
||||
Subject: [PATCH 43/78] mfd: mt6397: int_con and int_status may vary in
|
||||
Subject: [PATCH 43/81] mfd: mt6397: int_con and int_status may vary in
|
||||
location
|
||||
|
||||
MT6323 has the INT_CON and INT_STATUS located at a different position.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 1ef53a11f0c282008aa572eb7c97fa1e79621ea3 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 8 Jan 2016 08:41:52 +0100
|
||||
Subject: [PATCH 44/78] mfd: mt6397: add support for different Slave types
|
||||
Subject: [PATCH 44/81] mfd: mt6397: add support for different Slave types
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 49d9c28b1252c7920840662425aa7e4705cfbccf Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 8 Jan 2016 04:09:43 +0100
|
||||
Subject: [PATCH 45/78] mfd: mt6397: add MT6323 support to MT6397 driver
|
||||
Subject: [PATCH 45/81] mfd: mt6397: add MT6323 support to MT6397 driver
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From f5b5c70021187c0ef70edf83865b62fec473e8fb Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 10 Jan 2016 17:31:46 +0100
|
||||
Subject: [PATCH 46/78] regulator: Add document for MT6323 regulator
|
||||
Subject: [PATCH 46/81] regulator: Add document for MT6323 regulator
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Cc: devicetree@vger.kernel.org
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 031a2ff537366855e88bc95e5d42ea522b6c5ad8 Mon Sep 17 00:00:00 2001
|
||||
From: Chen Zhong <chen.zhong@mediatek.com>
|
||||
Date: Fri, 8 Jan 2016 04:17:37 +0100
|
||||
Subject: [PATCH 47/78] regulator: mt6323: Add support for MT6323 regulator
|
||||
Subject: [PATCH 47/81] regulator: mt6323: Add support for MT6323 regulator
|
||||
|
||||
The MT6323 is a regulator found on boards based on MediaTek MT7623 and
|
||||
probably other SoCs. It is a so called pmic and connects as a slave to
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From b79b0519fb67c22cbed341c5e9dca5ad0aa4d15c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 2 Mar 2016 07:18:52 +0100
|
||||
Subject: [PATCH 48/78] net-next: mediatek: document MediaTek SoC ethernet
|
||||
Subject: [PATCH 48/81] net-next: mediatek: document MediaTek SoC ethernet
|
||||
binding
|
||||
|
||||
This adds the binding documentation for the MediaTek Ethernet
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 999621b6bfff903d16691799a23bfccac91c31df Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 2 Mar 2016 04:27:10 +0100
|
||||
Subject: [PATCH 49/78] net-next: mediatek: add support for MT7623 ethernet
|
||||
Subject: [PATCH 49/81] net-next: mediatek: add support for MT7623 ethernet
|
||||
|
||||
Add ethernet support for MediaTek SoCs from the MT7623 family. These have
|
||||
dual GMAC. Depending on the exact version, there might be a built-in
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 0189b71d0ce9feef1c3fac7d9c3eb7dae57dabdf Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 2 Mar 2016 04:32:43 +0100
|
||||
Subject: [PATCH 50/78] net-next: mediatek: add Kconfig and Makefile
|
||||
Subject: [PATCH 50/81] net-next: mediatek: add Kconfig and Makefile
|
||||
|
||||
This patch adds the Makefile and Kconfig required to make the driver build.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 76ac7ac355452b4a2cf5cf7b1d9ab5b08e349b4b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 2 Mar 2016 04:34:04 +0100
|
||||
Subject: [PATCH 51/78] net-next: mediatek: add an entry to MAINTAINERS
|
||||
Subject: [PATCH 51/81] net-next: mediatek: add an entry to MAINTAINERS
|
||||
|
||||
Add myself and Felix as the Maintainers for the MediaTek ethernet driver.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 17b9724cf84aa32f15334c23d5df34ad3cb885f3 Mon Sep 17 00:00:00 2001
|
||||
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
Date: Mon, 16 Nov 2015 14:37:35 +0100
|
||||
Subject: [PATCH 52/78] mtd: nand: add an mtd_to_nand() helper
|
||||
Subject: [PATCH 52/81] mtd: nand: add an mtd_to_nand() helper
|
||||
|
||||
Some drivers are retrieving the nand_chip pointer using the container_of
|
||||
macro on a struct wrapping both the nand_chip and the mtd_info struct while
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 86e5fe2edbe2ca4f0d83a26d9b3d02620cd78f37 Mon Sep 17 00:00:00 2001
|
||||
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
Date: Tue, 1 Dec 2015 12:03:07 +0100
|
||||
Subject: [PATCH 53/78] mtd: nand: add nand_to_mtd() helper
|
||||
Subject: [PATCH 53/81] mtd: nand: add nand_to_mtd() helper
|
||||
|
||||
Add a new helper to retrieve the MTD device attached to a NAND chip.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From ca10b32de369729b8e7947fe1945e8e393d803cd Mon Sep 17 00:00:00 2001
|
||||
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
Date: Thu, 10 Dec 2015 09:00:39 +0100
|
||||
Subject: [PATCH 54/78] mtd: nand: add helpers to access ->priv
|
||||
Subject: [PATCH 54/81] mtd: nand: add helpers to access ->priv
|
||||
|
||||
Add two helpers to access the field reserved for private controller data.
|
||||
This makes it clearer what this field is reserved for and ease future
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From b4a93bff70545d73337e2cae7209fd1ae4d9d8e8 Mon Sep 17 00:00:00 2001
|
||||
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
Date: Tue, 1 Dec 2015 12:03:06 +0100
|
||||
Subject: [PATCH 55/78] mtd: nand: embed an mtd_info structure into nand_chip
|
||||
Subject: [PATCH 55/81] mtd: nand: embed an mtd_info structure into nand_chip
|
||||
|
||||
Currently all NAND controller drivers are providing both the mtd_info and
|
||||
nand_chip struct and then let the NAND subsystem to initialize a few
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 3ed29e95facfd50427721f8e9093dc36c2304e42 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 22 Mar 2016 03:52:07 +0100
|
||||
Subject: [PATCH 56/78] mtd: add get/set of_node/flash_node helpers
|
||||
Subject: [PATCH 56/81] mtd: add get/set of_node/flash_node helpers
|
||||
|
||||
We are going to begin using the mtd->dev.of_node field for MTD device
|
||||
nodes, so let's add helpers for it. Also, we'll be making some
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 5f0a1fa77e5d53b8dbb751fcfc59c7ef3d78ddf2 Mon Sep 17 00:00:00 2001
|
||||
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
|
||||
Date: Wed, 2 Mar 2016 12:00:11 -0500
|
||||
Subject: [PATCH 57/78] mtd: mediatek: device tree docs for MTK Smart Device
|
||||
Subject: [PATCH 57/81] mtd: mediatek: device tree docs for MTK Smart Device
|
||||
Gen1 NAND
|
||||
|
||||
This patch adds documentation support for Smart Device Gen1 type of
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From cc1959d5bc9a709729fcd02d78f4c27394393109 Mon Sep 17 00:00:00 2001
|
||||
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
|
||||
Date: Wed, 2 Mar 2016 12:00:12 -0500
|
||||
Subject: [PATCH 58/78] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
|
||||
Subject: [PATCH 58/81] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
|
||||
|
||||
This patch adds support for mediatek's SDG1 NFC nand controller
|
||||
embedded in SoC 2701.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 96ec6b2ee8a19799835209d0a6753519b96277f8 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 31 Mar 2016 02:28:08 +0200
|
||||
Subject: [PATCH 59/78] mtd: nand: backport fixes
|
||||
Subject: [PATCH 59/81] mtd: nand: backport fixes
|
||||
|
||||
---
|
||||
drivers/mtd/nand/mtksdg1_nand.c | 9 ++++++++-
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From c657573d75d71076fef8294f9d4f7f9a0e6f7a9e Mon Sep 17 00:00:00 2001
|
||||
From: Dan Carpenter <dan.carpenter@oracle.com>
|
||||
Date: Tue, 15 Mar 2016 10:18:49 +0300
|
||||
Subject: [PATCH 60/78] net: mediatek: checking for IS_ERR() instead of NULL
|
||||
Subject: [PATCH 60/81] net: mediatek: checking for IS_ERR() instead of NULL
|
||||
|
||||
of_phy_connect() returns NULL on error, it never returns error pointers.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From d8261ad9e408adfa5d1758a0f655c7726f0f831b Mon Sep 17 00:00:00 2001
|
||||
From: Dan Carpenter <dan.carpenter@oracle.com>
|
||||
Date: Tue, 15 Mar 2016 10:19:04 +0300
|
||||
Subject: [PATCH 61/78] net: mediatek: unlock on error in mtk_tx_map()
|
||||
Subject: [PATCH 61/81] net: mediatek: unlock on error in mtk_tx_map()
|
||||
|
||||
There was a missing unlock on the error path.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 26c749e825e87e8be46498be7ac425e83b0f22c6 Mon Sep 17 00:00:00 2001
|
||||
From: Arnd Bergmann <arnd@arndb.de>
|
||||
Date: Mon, 14 Mar 2016 15:07:10 +0100
|
||||
Subject: [PATCH 62/78] net: mediatek: use dma_addr_t correctly
|
||||
Subject: [PATCH 62/81] net: mediatek: use dma_addr_t correctly
|
||||
|
||||
dma_alloc_coherent() expects a dma_addr_t pointer as its argument,
|
||||
not an 'unsigned int', and gcc correctly warns about broken
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 21f52c7a0ec569ae9dd72bfc619a7161e40a2e9d Mon Sep 17 00:00:00 2001
|
||||
From: Arnd Bergmann <arnd@arndb.de>
|
||||
Date: Mon, 14 Mar 2016 15:07:11 +0100
|
||||
Subject: [PATCH 63/78] net: mediatek: remove incorrect dma_mask assignment
|
||||
Subject: [PATCH 63/81] net: mediatek: remove incorrect dma_mask assignment
|
||||
|
||||
Device drivers should not mess with the DMA mask directly,
|
||||
but instead call dma_set_mask() etc if needed.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From e1e7d841480b3a0febdb999fd1c6c4213ee18ea7 Mon Sep 17 00:00:00 2001
|
||||
From: Arnd Bergmann <arnd@arndb.de>
|
||||
Date: Mon, 14 Mar 2016 15:07:12 +0100
|
||||
Subject: [PATCH 64/78] net: mediatek: check device_reset return code
|
||||
Subject: [PATCH 64/81] net: mediatek: check device_reset return code
|
||||
|
||||
The device_reset() function may fail, so we have to check
|
||||
its return value, e.g. to make deferred probing work correctly.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 103d950e6201ab54a8b64402bb0b32a35831b028 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 30 Mar 2016 03:18:17 +0200
|
||||
Subject: [PATCH 65/78] net: mediatek: watchdog_timeo was not set
|
||||
Subject: [PATCH 65/81] net: mediatek: watchdog_timeo was not set
|
||||
|
||||
The original commit failed to set watchdog_timeo. This patch sets
|
||||
watchdog_timeo to HZ.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 1212704e8270f0e673e10a49960318ade0096cf9 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 22 Mar 2016 04:42:27 +0100
|
||||
Subject: [PATCH 66/78] net: mediatek: mtk_cal_txd_req() returns bad value
|
||||
Subject: [PATCH 66/81] net: mediatek: mtk_cal_txd_req() returns bad value
|
||||
|
||||
The code used to also support the PDMA engine, which had 2 packet pointers
|
||||
per descriptor. Because of this we have to divide the result by 2 and round
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 429b5becfb1e4aacf392c4b246a17b83faad3072 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 29 Mar 2016 14:32:07 +0200
|
||||
Subject: [PATCH 67/78] net: mediatek: update the IRQ part of the binding
|
||||
Subject: [PATCH 67/81] net: mediatek: update the IRQ part of the binding
|
||||
document
|
||||
|
||||
The current binding document only describes a single interrupt. Update the
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 3c8781211140cc23750544a52b7310edb3b57f00 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 25 Mar 2016 04:24:27 +0100
|
||||
Subject: [PATCH 68/78] net: mediatek: remove superflous reset call
|
||||
Subject: [PATCH 68/81] net: mediatek: remove superflous reset call
|
||||
|
||||
HW reset is triggered int he mtk_hw_init() function. There is no need to
|
||||
reset the core during probe.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 6f8bfdfe2984467177d2a88982517659ec09ab5d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 29 Mar 2016 16:41:07 +0200
|
||||
Subject: [PATCH 69/78] net: mediatek: fix stop and wakeup of queue
|
||||
Subject: [PATCH 69/81] net: mediatek: fix stop and wakeup of queue
|
||||
|
||||
The driver supports 2 MACs. Both run on the same DMA ring. If we go
|
||||
above/below the TX rings thershold value, we always need to wake/stop
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From a2dfb33c8a0dc03fe2ec2121490df2b9352febef Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 29 Mar 2016 17:00:47 +0200
|
||||
Subject: [PATCH 70/78] net: mediatek: fix mtk_pending_work
|
||||
Subject: [PATCH 70/81] net: mediatek: fix mtk_pending_work
|
||||
|
||||
The driver supports 2 MACs. Both run on the same DMA ring. If we hit a TX
|
||||
timeout we need to stop both netdevs before retarting them again. If we
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From b9df14f712866925856c0ffb2d899511c21e1b8a Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 29 Mar 2016 17:20:01 +0200
|
||||
Subject: [PATCH 71/78] net: mediatek: fix TX locking
|
||||
Subject: [PATCH 71/81] net: mediatek: fix TX locking
|
||||
|
||||
Inside the TX path there is a lock inside the tx_map function. This is
|
||||
however too late. The patch moves the lock to the start of the xmit
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From 147dab4408adcccf702f8c5143e9c6b91f746790 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 29 Mar 2016 17:24:24 +0200
|
||||
Subject: [PATCH 72/78] net: mediatek: move the pending_work struct to the
|
||||
Subject: [PATCH 72/81] net: mediatek: move the pending_work struct to the
|
||||
device generic struct
|
||||
|
||||
The worker always touches both netdevs. It is ethernet core and not MAC
|
||||
|
|
|
|||
|
|
@ -1,314 +0,0 @@
|
|||
From e301da64a9fd2ebc24d4c9b2d184681ec833fd72 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 23 Mar 2016 18:31:48 +0100
|
||||
Subject: [PATCH 73/78] net-next: mediatek: add support for IRQ grouping
|
||||
|
||||
The ethernet core has 3 IRQs. using the IRQ grouping registers we are able
|
||||
to separate TX and RX IRQs, which allows us to service them on separate
|
||||
cores. This patch splits the irq handler into 2 separate functiosn, one for
|
||||
TX and another for RX. The TX housekeeping is split out of the NAPI handler.
|
||||
Instead we use a tasklet to handle housekeeping.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 +++++++++++++++++----------
|
||||
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++-
|
||||
2 files changed, 86 insertions(+), 41 deletions(-)
|
||||
|
||||
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||
index bbcd607..2097ae1 100644
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||
@@ -757,7 +757,7 @@ drop:
|
||||
}
|
||||
|
||||
static int mtk_poll_rx(struct napi_struct *napi, int budget,
|
||||
- struct mtk_eth *eth, u32 rx_intr)
|
||||
+ struct mtk_eth *eth)
|
||||
{
|
||||
struct mtk_rx_ring *ring = ð->rx_ring;
|
||||
int idx = ring->calc_idx;
|
||||
@@ -843,12 +843,12 @@ release_desc:
|
||||
}
|
||||
|
||||
if (done < budget)
|
||||
- mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
|
||||
+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
|
||||
|
||||
return done;
|
||||
}
|
||||
|
||||
-static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
|
||||
+static int mtk_poll_tx(struct mtk_eth *eth, int budget)
|
||||
{
|
||||
struct mtk_tx_ring *ring = ð->tx_ring;
|
||||
struct mtk_tx_dma *desc;
|
||||
@@ -911,9 +911,7 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
|
||||
}
|
||||
|
||||
/* read hw index again make sure no new tx packet */
|
||||
- if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
|
||||
- *tx_again = true;
|
||||
- else
|
||||
+ if (cpu == dma && cpu == mtk_r32(eth, MTK_QTX_DRX_PTR))
|
||||
mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
|
||||
|
||||
if (!total)
|
||||
@@ -925,27 +923,27 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
|
||||
return total;
|
||||
}
|
||||
|
||||
+static void mtk_clean_tx_tasklet(unsigned long arg)
|
||||
+{
|
||||
+ struct mtk_eth *eth = (struct mtk_eth *)arg;
|
||||
+
|
||||
+ if (mtk_poll_tx(eth, MTK_NAPI_WEIGHT) > 0)
|
||||
+ tasklet_schedule(ð->tx_clean_tasklet);
|
||||
+ else
|
||||
+ mtk_irq_enable(eth, MTK_TX_DONE_INT);
|
||||
+}
|
||||
+
|
||||
static int mtk_poll(struct napi_struct *napi, int budget)
|
||||
{
|
||||
struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
|
||||
- u32 status, status2, mask, tx_intr, rx_intr, status_intr;
|
||||
- int tx_done, rx_done;
|
||||
- bool tx_again = false;
|
||||
+ u32 status, status2, mask, status_intr;
|
||||
+ int rx_done = 0;
|
||||
|
||||
status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
|
||||
status2 = mtk_r32(eth, MTK_INT_STATUS2);
|
||||
- tx_intr = MTK_TX_DONE_INT;
|
||||
- rx_intr = MTK_RX_DONE_INT;
|
||||
status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
|
||||
- tx_done = 0;
|
||||
- rx_done = 0;
|
||||
- tx_again = 0;
|
||||
|
||||
- if (status & tx_intr)
|
||||
- tx_done = mtk_poll_tx(eth, budget, &tx_again);
|
||||
-
|
||||
- if (status & rx_intr)
|
||||
- rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
|
||||
+ rx_done = mtk_poll_rx(napi, budget, eth);
|
||||
|
||||
if (unlikely(status2 & status_intr)) {
|
||||
mtk_stats_update(eth);
|
||||
@@ -954,20 +952,20 @@ static int mtk_poll(struct napi_struct *napi, int budget)
|
||||
|
||||
if (unlikely(netif_msg_intr(eth))) {
|
||||
mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
|
||||
- netdev_info(eth->netdev[0],
|
||||
- "done tx %d, rx %d, intr 0x%08x/0x%x\n",
|
||||
- tx_done, rx_done, status, mask);
|
||||
+ dev_info(eth->dev,
|
||||
+ "done rx %d, intr 0x%08x/0x%x\n",
|
||||
+ rx_done, status, mask);
|
||||
}
|
||||
|
||||
- if (tx_again || rx_done == budget)
|
||||
+ if (rx_done == budget)
|
||||
return budget;
|
||||
|
||||
status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
|
||||
- if (status & (tx_intr | rx_intr))
|
||||
+ if (status & MTK_RX_DONE_INT)
|
||||
return budget;
|
||||
|
||||
napi_complete(napi);
|
||||
- mtk_irq_enable(eth, tx_intr | rx_intr);
|
||||
+ mtk_irq_enable(eth, MTK_RX_DONE_INT);
|
||||
|
||||
return rx_done;
|
||||
}
|
||||
@@ -1196,22 +1194,43 @@ static void mtk_tx_timeout(struct net_device *dev)
|
||||
schedule_work(ð->pending_work);
|
||||
}
|
||||
|
||||
-static irqreturn_t mtk_handle_irq(int irq, void *_eth)
|
||||
+static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
|
||||
{
|
||||
struct mtk_eth *eth = _eth;
|
||||
u32 status;
|
||||
|
||||
status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
|
||||
+ status &= ~MTK_TX_DONE_INT;
|
||||
+
|
||||
if (unlikely(!status))
|
||||
return IRQ_NONE;
|
||||
|
||||
- if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
|
||||
+ if (status & MTK_RX_DONE_INT) {
|
||||
if (likely(napi_schedule_prep(ð->rx_napi)))
|
||||
__napi_schedule(ð->rx_napi);
|
||||
- } else {
|
||||
- mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
|
||||
+ mtk_irq_disable(eth, MTK_RX_DONE_INT);
|
||||
}
|
||||
- mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
|
||||
+ mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
|
||||
+{
|
||||
+ struct mtk_eth *eth = _eth;
|
||||
+ u32 status;
|
||||
+
|
||||
+ status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
|
||||
+ status &= ~MTK_RX_DONE_INT;
|
||||
+
|
||||
+ if (unlikely(!status))
|
||||
+ return IRQ_NONE;
|
||||
+
|
||||
+ if (status & MTK_TX_DONE_INT) {
|
||||
+ tasklet_schedule(ð->tx_clean_tasklet);
|
||||
+ mtk_irq_disable(eth, MTK_TX_DONE_INT);
|
||||
+ }
|
||||
+ mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
@@ -1224,7 +1243,7 @@ static void mtk_poll_controller(struct net_device *dev)
|
||||
u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
|
||||
|
||||
mtk_irq_disable(eth, int_mask);
|
||||
- mtk_handle_irq(dev->irq, dev);
|
||||
+ mtk_handle_irq(dev->irq[0], dev);
|
||||
mtk_irq_enable(eth, int_mask);
|
||||
}
|
||||
#endif
|
||||
@@ -1345,7 +1364,11 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
|
||||
/* Enable RX VLan Offloading */
|
||||
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
|
||||
|
||||
- err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
|
||||
+ err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
|
||||
+ dev_name(eth->dev), eth);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+ err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
|
||||
dev_name(eth->dev), eth);
|
||||
if (err)
|
||||
return err;
|
||||
@@ -1361,7 +1384,11 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
|
||||
mtk_w32(eth, 0, MTK_RST_GL);
|
||||
|
||||
/* FE int grouping */
|
||||
- mtk_w32(eth, 0, MTK_FE_INT_GRP);
|
||||
+ mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
|
||||
+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
|
||||
+ mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
|
||||
+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
|
||||
+ mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
|
||||
@@ -1409,7 +1436,9 @@ static void mtk_uninit(struct net_device *dev)
|
||||
phy_disconnect(mac->phy_dev);
|
||||
mtk_mdio_cleanup(eth);
|
||||
mtk_irq_disable(eth, ~0);
|
||||
- free_irq(dev->irq, dev);
|
||||
+ free_irq(eth->irq[0], dev);
|
||||
+ free_irq(eth->irq[1], dev);
|
||||
+ free_irq(eth->irq[2], dev);
|
||||
}
|
||||
|
||||
static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
||||
@@ -1684,10 +1713,10 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
|
||||
dev_err(eth->dev, "error bringing up device\n");
|
||||
goto free_netdev;
|
||||
}
|
||||
- eth->netdev[id]->irq = eth->irq;
|
||||
+ eth->netdev[id]->irq = eth->irq[0];
|
||||
netif_info(eth, probe, eth->netdev[id],
|
||||
"mediatek frame engine at 0x%08lx, irq %d\n",
|
||||
- eth->netdev[id]->base_addr, eth->netdev[id]->irq);
|
||||
+ eth->netdev[id]->base_addr, eth->irq[0]);
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -1704,6 +1733,7 @@ static int mtk_probe(struct platform_device *pdev)
|
||||
struct mtk_soc_data *soc;
|
||||
struct mtk_eth *eth;
|
||||
int err;
|
||||
+ int i;
|
||||
|
||||
match = of_match_device(of_mtk_match, &pdev->dev);
|
||||
soc = (struct mtk_soc_data *)match->data;
|
||||
@@ -1738,10 +1768,12 @@ static int mtk_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(eth->rstc);
|
||||
}
|
||||
|
||||
- eth->irq = platform_get_irq(pdev, 0);
|
||||
- if (eth->irq < 0) {
|
||||
- dev_err(&pdev->dev, "no IRQ resource found\n");
|
||||
- return -ENXIO;
|
||||
+ for (i = 0; i < 3; i++) {
|
||||
+ eth->irq[i] = platform_get_irq(pdev, i);
|
||||
+ if (eth->irq[i] < 0) {
|
||||
+ dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
|
||||
+ return -ENXIO;
|
||||
+ }
|
||||
}
|
||||
|
||||
eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
|
||||
@@ -1785,6 +1817,9 @@ static int mtk_probe(struct platform_device *pdev)
|
||||
netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_poll,
|
||||
MTK_NAPI_WEIGHT);
|
||||
|
||||
+ tasklet_init(ð->tx_clean_tasklet,
|
||||
+ mtk_clean_tx_tasklet, (unsigned long)eth);
|
||||
+
|
||||
platform_set_drvdata(pdev, eth);
|
||||
|
||||
return 0;
|
||||
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||
index eed626d..4cfb40c 100644
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||
@@ -68,6 +68,10 @@
|
||||
/* Unicast Filter MAC Address Register - High */
|
||||
#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
|
||||
|
||||
+/* PDMA Interrupt grouping registers */
|
||||
+#define MTK_PDMA_INT_GRP1 0xa50
|
||||
+#define MTK_PDMA_INT_GRP2 0xa54
|
||||
+
|
||||
/* QDMA TX Queue Configuration Registers */
|
||||
#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
|
||||
#define QDMA_RES_THRES 4
|
||||
@@ -124,6 +128,11 @@
|
||||
#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
|
||||
MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
|
||||
|
||||
+/* QDMA Interrupt grouping registers */
|
||||
+#define MTK_QDMA_INT_GRP1 0x1a20
|
||||
+#define MTK_QDMA_INT_GRP2 0x1a24
|
||||
+#define MTK_RLS_DONE_INT BIT(0)
|
||||
+
|
||||
/* QDMA Interrupt Status Register */
|
||||
#define MTK_QDMA_INT_MASK 0x1A1C
|
||||
|
||||
@@ -374,7 +383,7 @@ struct mtk_eth {
|
||||
struct net_device dummy_dev;
|
||||
struct net_device *netdev[MTK_MAX_DEVS];
|
||||
struct mtk_mac *mac[MTK_MAX_DEVS];
|
||||
- int irq;
|
||||
+ int irq[3];
|
||||
u32 msg_enable;
|
||||
unsigned long sysclk;
|
||||
struct regmap *ethsys;
|
||||
@@ -391,6 +400,7 @@ struct mtk_eth {
|
||||
struct clk *clk_gp2;
|
||||
struct mii_bus *mii_bus;
|
||||
struct work_struct pending_work;
|
||||
+ struct tasklet_struct tx_clean_tasklet;
|
||||
};
|
||||
|
||||
/* struct mtk_mac - the structure that holds the info about the MACs of the
|
||||
--
|
||||
1.7.10.4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,74 +0,0 @@
|
|||
From b7a101f53b7cb0e05658e04accf9fd12512b5735 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 31 Mar 2016 06:46:51 +0200
|
||||
Subject: [PATCH 75/78] clk: mediatek: enable critical clocks
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/clk/mediatek/clk-mt2701.c | 22 ++++++++++++++++++++--
|
||||
1 file changed, 20 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
|
||||
index 812b347..1634288 100644
|
||||
--- a/drivers/clk/mediatek/clk-mt2701.c
|
||||
+++ b/drivers/clk/mediatek/clk-mt2701.c
|
||||
@@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[] __initconst = {
|
||||
GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
|
||||
};
|
||||
|
||||
+static struct clk_onecell_data *mt7623_top_clk_data __initdata;
|
||||
+static struct clk_onecell_data *mt7623_pll_clk_data __initdata;
|
||||
+
|
||||
+static void __init mtk_clk_enable_critical(void)
|
||||
+{
|
||||
+ if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
|
||||
+ return;
|
||||
+
|
||||
+ clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
|
||||
+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
|
||||
+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
|
||||
+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
|
||||
+}
|
||||
+
|
||||
static void __init mtk_topckgen_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
@@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
|
||||
return;
|
||||
}
|
||||
|
||||
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
|
||||
+ mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
|
||||
|
||||
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
|
||||
clk_data);
|
||||
@@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(struct device_node *node)
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
+
|
||||
+ mtk_clk_enable_critical();
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
|
||||
|
||||
@@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
|
||||
+ mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
|
||||
if (!clk_data)
|
||||
return;
|
||||
|
||||
@@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
+
|
||||
+ mtk_clk_enable_critical();
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
|
||||
mtk_apmixedsys_init);
|
||||
--
|
||||
1.7.10.4
|
||||
|
||||
|
|
@ -1,306 +0,0 @@
|
|||
From cc94bef897241da9b978c9799defbdbabe9ff6ec Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 31 Mar 2016 02:26:37 +0200
|
||||
Subject: [PATCH 76/78] clk: mediatek: Export CPU mux clocks for CPU frequency
|
||||
control
|
||||
|
||||
This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
|
||||
for intermediate clock source switching.
|
||||
|
||||
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
---
|
||||
drivers/clk/mediatek/Makefile | 2 +-
|
||||
drivers/clk/mediatek/clk-cpumux.c | 127 ++++++++++++++++++++++++++++++++
|
||||
drivers/clk/mediatek/clk-cpumux.h | 22 ++++++
|
||||
drivers/clk/mediatek/clk-mt2701.c | 8 ++
|
||||
drivers/clk/mediatek/clk-mt8173.c | 23 ++++++
|
||||
include/dt-bindings/clock/mt2701-clk.h | 3 +-
|
||||
include/dt-bindings/clock/mt8173-clk.h | 4 +-
|
||||
7 files changed, 186 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/clk/mediatek/clk-cpumux.c
|
||||
create mode 100644 drivers/clk/mediatek/clk-cpumux.h
|
||||
|
||||
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
|
||||
index 5b2b91b..76bfab6 100644
|
||||
--- a/drivers/clk/mediatek/Makefile
|
||||
+++ b/drivers/clk/mediatek/Makefile
|
||||
@@ -1,4 +1,4 @@
|
||||
-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
|
||||
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
|
||||
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
|
||||
diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
|
||||
new file mode 100644
|
||||
index 0000000..91b5238
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/mediatek/clk-cpumux.c
|
||||
@@ -0,0 +1,127 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015 Linaro Ltd.
|
||||
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk-provider.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/slab.h>
|
||||
+
|
||||
+#include "clk-mtk.h"
|
||||
+#include "clk-cpumux.h"
|
||||
+
|
||||
+struct mtk_clk_cpumux {
|
||||
+ struct clk_hw hw;
|
||||
+ struct regmap *regmap;
|
||||
+ u32 reg;
|
||||
+ u32 mask;
|
||||
+ u8 shift;
|
||||
+};
|
||||
+
|
||||
+static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
|
||||
+{
|
||||
+ return container_of(_hw, struct mtk_clk_cpumux, hw);
|
||||
+}
|
||||
+
|
||||
+static u8 clk_cpumux_get_parent(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
|
||||
+ int num_parents = clk_hw_get_num_parents(hw);
|
||||
+ unsigned int val;
|
||||
+
|
||||
+ regmap_read(mux->regmap, mux->reg, &val);
|
||||
+
|
||||
+ val >>= mux->shift;
|
||||
+ val &= mux->mask;
|
||||
+
|
||||
+ if (val >= num_parents)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
|
||||
+{
|
||||
+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
|
||||
+ u32 mask, val;
|
||||
+
|
||||
+ val = index << mux->shift;
|
||||
+ mask = mux->mask << mux->shift;
|
||||
+
|
||||
+ return regmap_update_bits(mux->regmap, mux->reg, mask, val);
|
||||
+}
|
||||
+
|
||||
+static const struct clk_ops clk_cpumux_ops = {
|
||||
+ .get_parent = clk_cpumux_get_parent,
|
||||
+ .set_parent = clk_cpumux_set_parent,
|
||||
+};
|
||||
+
|
||||
+static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
|
||||
+ struct regmap *regmap)
|
||||
+{
|
||||
+ struct mtk_clk_cpumux *cpumux;
|
||||
+ struct clk *clk;
|
||||
+ struct clk_init_data init;
|
||||
+
|
||||
+ cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
|
||||
+ if (!cpumux)
|
||||
+ return ERR_PTR(-ENOMEM);
|
||||
+
|
||||
+ init.name = mux->name;
|
||||
+ init.ops = &clk_cpumux_ops;
|
||||
+ init.parent_names = mux->parent_names;
|
||||
+ init.num_parents = mux->num_parents;
|
||||
+ init.flags = mux->flags;
|
||||
+
|
||||
+ cpumux->reg = mux->mux_reg;
|
||||
+ cpumux->shift = mux->mux_shift;
|
||||
+ cpumux->mask = BIT(mux->mux_width) - 1;
|
||||
+ cpumux->regmap = regmap;
|
||||
+ cpumux->hw.init = &init;
|
||||
+
|
||||
+ clk = clk_register(NULL, &cpumux->hw);
|
||||
+ if (IS_ERR(clk))
|
||||
+ kfree(cpumux);
|
||||
+
|
||||
+ return clk;
|
||||
+}
|
||||
+
|
||||
+int __init mtk_clk_register_cpumuxes(struct device_node *node,
|
||||
+ const struct mtk_composite *clks, int num,
|
||||
+ struct clk_onecell_data *clk_data)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct clk *clk;
|
||||
+ struct regmap *regmap;
|
||||
+
|
||||
+ regmap = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(regmap)) {
|
||||
+ pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
|
||||
+ PTR_ERR(regmap));
|
||||
+ return PTR_ERR(regmap);
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < num; i++) {
|
||||
+ const struct mtk_composite *mux = &clks[i];
|
||||
+
|
||||
+ clk = mtk_clk_register_cpumux(mux, regmap);
|
||||
+ if (IS_ERR(clk)) {
|
||||
+ pr_err("Failed to register clk %s: %ld\n",
|
||||
+ mux->name, PTR_ERR(clk));
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ clk_data->clks[mux->id] = clk;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
|
||||
new file mode 100644
|
||||
index 0000000..52c769f
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/mediatek/clk-cpumux.h
|
||||
@@ -0,0 +1,22 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015 Linaro Ltd.
|
||||
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#ifndef __DRV_CLK_CPUMUX_H
|
||||
+#define __DRV_CLK_CPUMUX_H
|
||||
+
|
||||
+int mtk_clk_register_cpumuxes(struct device_node *node,
|
||||
+ const struct mtk_composite *clks, int num,
|
||||
+ struct clk_onecell_data *clk_data);
|
||||
+
|
||||
+#endif /* __DRV_CLK_CPUMUX_H */
|
||||
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
|
||||
index 1634288..5c37fcb 100644
|
||||
--- a/drivers/clk/mediatek/clk-mt2701.c
|
||||
+++ b/drivers/clk/mediatek/clk-mt2701.c
|
||||
@@ -18,6 +18,7 @@
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
+#include "clk-cpumux.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2701-clk.h>
|
||||
|
||||
@@ -465,6 +466,10 @@ static const char * const cpu_parents[] __initconst = {
|
||||
"mmpll"
|
||||
};
|
||||
|
||||
+static const struct mtk_composite cpu_muxes[] __initconst = {
|
||||
+ MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
|
||||
+};
|
||||
+
|
||||
static const struct mtk_composite top_muxes[] __initconst = {
|
||||
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
|
||||
0x0040, 0, 3, INVALID_MUX_GATE_BIT),
|
||||
@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
||||
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
|
||||
clk_data);
|
||||
|
||||
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
||||
+ clk_data);
|
||||
+
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
|
||||
index 227e356..dfb109f 100644
|
||||
--- a/drivers/clk/mediatek/clk-mt8173.c
|
||||
+++ b/drivers/clk/mediatek/clk-mt8173.c
|
||||
@@ -18,6 +18,7 @@
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
+#include "clk-cpumux.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
|
||||
@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
|
||||
"apll2_div5"
|
||||
};
|
||||
|
||||
+static const char * const ca53_parents[] __initconst = {
|
||||
+ "clk26m",
|
||||
+ "armca7pll",
|
||||
+ "mainpll",
|
||||
+ "univpll"
|
||||
+};
|
||||
+
|
||||
+static const char * const ca57_parents[] __initconst = {
|
||||
+ "clk26m",
|
||||
+ "armca15pll",
|
||||
+ "mainpll",
|
||||
+ "univpll"
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_composite cpu_muxes[] __initdata = {
|
||||
+ MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
|
||||
+ MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
|
||||
+};
|
||||
+
|
||||
static const struct mtk_composite top_muxes[] __initconst = {
|
||||
/* CLK_CFG_0 */
|
||||
MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
|
||||
@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
||||
clk_data);
|
||||
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
|
||||
|
||||
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
||||
+ clk_data);
|
||||
+
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
|
||||
index 50972d1..a6c63b8 100644
|
||||
--- a/include/dt-bindings/clock/mt2701-clk.h
|
||||
+++ b/include/dt-bindings/clock/mt2701-clk.h
|
||||
@@ -217,7 +217,8 @@
|
||||
#define CLK_INFRA_PMICWRAP 17
|
||||
#define CLK_INFRA_DDCCI 18
|
||||
#define CLK_INFRA_CLK_13M 19
|
||||
-#define CLK_INFRA_NR 20
|
||||
+#define CLK_INFRA_CPUSEL 20
|
||||
+#define CLK_INFRA_NR 21
|
||||
|
||||
/* PERICFG */
|
||||
|
||||
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
|
||||
index 7956ba1..c82ed7c 100644
|
||||
--- a/include/dt-bindings/clock/mt8173-clk.h
|
||||
+++ b/include/dt-bindings/clock/mt8173-clk.h
|
||||
@@ -192,7 +192,9 @@
|
||||
#define CLK_INFRA_PMICSPI 10
|
||||
#define CLK_INFRA_PMICWRAP 11
|
||||
#define CLK_INFRA_CLK_13M 12
|
||||
-#define CLK_INFRA_NR_CLK 13
|
||||
+#define CLK_INFRA_CA53SEL 13
|
||||
+#define CLK_INFRA_CA57SEL 14
|
||||
+#define CLK_INFRA_NR_CLK 15
|
||||
|
||||
/* PERI_SYS */
|
||||
|
||||
--
|
||||
1.7.10.4
|
||||
|
||||
|
|
@ -1,727 +0,0 @@
|
|||
From d1421147c328a7d06d9a6b8330c73e45139b1e48 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 30 Mar 2016 23:48:53 +0200
|
||||
Subject: [PATCH 77/78] cpufreq: mediatek: add driver
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/arm/boot/dts/mt7623-evb.dts | 160 ++++++++++++----
|
||||
arch/arm/boot/dts/mt7623.dtsi | 50 ++++-
|
||||
drivers/cpufreq/Kconfig.arm | 9 +
|
||||
drivers/cpufreq/Makefile | 1 +
|
||||
drivers/cpufreq/mt7623-cpufreq.c | 389 ++++++++++++++++++++++++++++++++++++++
|
||||
5 files changed, 570 insertions(+), 39 deletions(-)
|
||||
create mode 100644 drivers/cpufreq/mt7623-cpufreq.c
|
||||
|
||||
diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
|
||||
index bc2b3f1..4a433f0 100644
|
||||
--- a/arch/arm/boot/dts/mt7623-evb.dts
|
||||
+++ b/arch/arm/boot/dts/mt7623-evb.dts
|
||||
@@ -39,6 +39,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&cpu0 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
&pwrap {
|
||||
pmic: mt6323 {
|
||||
compatible = "mediatek,mt6323";
|
||||
@@ -267,38 +283,36 @@
|
||||
};
|
||||
};
|
||||
|
||||
-&uart2 {
|
||||
- status = "okay";
|
||||
-};
|
||||
+&pio {
|
||||
+ nand_pins_default: nanddefault {
|
||||
+ pins_dat {
|
||||
+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
|
||||
+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
|
||||
+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
|
||||
+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
|
||||
+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
|
||||
+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
|
||||
+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
|
||||
+ <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
|
||||
+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
|
||||
+ input-enable;
|
||||
+ drive-strength = <MTK_DRIVE_8mA>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
|
||||
-&mmc0 {
|
||||
- status = "okay";
|
||||
- pinctrl-names = "default", "state_uhs";
|
||||
- pinctrl-0 = <&mmc0_pins_default>;
|
||||
- pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
- bus-width = <8>;
|
||||
- max-frequency = <50000000>;
|
||||
- cap-mmc-highspeed;
|
||||
- vmmc-supply = <&mt6323_vemc3v3_reg>;
|
||||
- vqmmc-supply = <&mt6323_vio18_reg>;
|
||||
- non-removable;
|
||||
-};
|
||||
+ pins_we {
|
||||
+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
|
||||
+ drive-strength = <MTK_DRIVE_8mA>;
|
||||
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
+ };
|
||||
|
||||
-&mmc1 {
|
||||
- status = "okay";
|
||||
- pinctrl-names = "default", "state_uhs";
|
||||
- pinctrl-0 = <&mmc1_pins_default>;
|
||||
- pinctrl-1 = <&mmc1_pins_uhs>;
|
||||
- bus-width = <4>;
|
||||
- max-frequency = <50000000>;
|
||||
- cap-sd-highspeed;
|
||||
- sd-uhs-sdr25;
|
||||
-// cd-gpios = <&pio 132 0>;
|
||||
- vmmc-supply = <&mt6323_vmch_reg>;
|
||||
- vqmmc-supply = <&mt6323_vmc_reg>;
|
||||
-};
|
||||
+ pins_ale {
|
||||
+ pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
|
||||
+ drive-strength = <MTK_DRIVE_8mA>;
|
||||
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
+ };
|
||||
+ };
|
||||
|
||||
-&pio {
|
||||
mmc0_pins_default: mmc0default {
|
||||
pins_cmd_dat {
|
||||
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
|
||||
@@ -370,11 +384,6 @@
|
||||
bias-pull-down;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
};
|
||||
-
|
||||
-// pins_insert {
|
||||
-// pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
|
||||
-// bias-pull-up;
|
||||
-// };
|
||||
};
|
||||
|
||||
mmc1_pins_uhs: mmc1 {
|
||||
@@ -422,6 +431,36 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mmc0 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default", "state_uhs";
|
||||
+ pinctrl-0 = <&mmc0_pins_default>;
|
||||
+ pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <50000000>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ vmmc-supply = <&mt6323_vemc3v3_reg>;
|
||||
+ vqmmc-supply = <&mt6323_vio18_reg>;
|
||||
+ non-removable;
|
||||
+};
|
||||
+
|
||||
+&mmc1 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default", "state_uhs";
|
||||
+ pinctrl-0 = <&mmc1_pins_default>;
|
||||
+ pinctrl-1 = <&mmc1_pins_uhs>;
|
||||
+ bus-width = <4>;
|
||||
+ max-frequency = <50000000>;
|
||||
+ cap-sd-highspeed;
|
||||
+ sd-uhs-sdr25;
|
||||
+ vmmc-supply = <&mt6323_vmch_reg>;
|
||||
+ vqmmc-supply = <&mt6323_vmc_reg>;
|
||||
+};
|
||||
+
|
||||
&usb1 {
|
||||
vusb33-supply = <&mt6323_vusb_reg>;
|
||||
vbus-supply = <&usb_p1_vbus>;
|
||||
@@ -456,3 +495,56 @@
|
||||
mediatek,reset-pin = <&pio 15 0>;
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&nand {
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&nand_pins_default>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "preloader";
|
||||
+ reg = <0x0 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@1 {
|
||||
+ label = "u-boot";
|
||||
+ reg = <0x40000 0x80000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@2 {
|
||||
+ label = "u-boot-env";
|
||||
+ reg = <0xc0000 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@3 {
|
||||
+ label = "factory";
|
||||
+ reg = <0x100000 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@4 {
|
||||
+ label = "kernel";
|
||||
+ reg = <0x140000 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@4 {
|
||||
+ label = "kernel2";
|
||||
+ reg = <0x2140000 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@5 {
|
||||
+ label = "rootfs";
|
||||
+ reg = <0x4140000 0x1000000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@6 {
|
||||
+ label = "usrdata";
|
||||
+ reg = <0x5140000 0x9f80000>;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
|
||||
index f405ec7..76d603a 100644
|
||||
--- a/arch/arm/boot/dts/mt7623.dtsi
|
||||
+++ b/arch/arm/boot/dts/mt7623.dtsi
|
||||
@@ -31,25 +31,65 @@
|
||||
#size-cells = <0>;
|
||||
enable-method = "mediatek,mt6589-smp";
|
||||
|
||||
- cpu@0 {
|
||||
+ cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
- cpu@1 {
|
||||
+ cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
- cpu@2 {
|
||||
+ cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
- cpu@3 {
|
||||
+ cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -300,7 +340,7 @@
|
||||
clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
|
||||
<&pericfg CLK_PERI_NFI_PAD>;
|
||||
clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
|
||||
- nand-on-flash-bbt;
|
||||
+ // nand-on-flash-bbt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
|
||||
index b1f8a73..baf945e 100644
|
||||
--- a/drivers/cpufreq/Kconfig.arm
|
||||
+++ b/drivers/cpufreq/Kconfig.arm
|
||||
@@ -81,6 +81,15 @@ config ARM_KIRKWOOD_CPUFREQ
|
||||
This adds the CPUFreq driver for Marvell Kirkwood
|
||||
SoCs.
|
||||
|
||||
+config ARM_MT7623_CPUFREQ
|
||||
+ bool "Mediatek MT7623 CPUFreq support"
|
||||
+ depends on ARCH_MEDIATEK && REGULATOR
|
||||
+ depends on ARM || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
|
||||
+ depends on !CPU_THERMAL || THERMAL=y
|
||||
+ select PM_OPP
|
||||
+ help
|
||||
+ This adds the CPUFreq driver support for Mediatek MT7623 SoC.
|
||||
+
|
||||
config ARM_MT8173_CPUFREQ
|
||||
bool "Mediatek MT8173 CPUFreq support"
|
||||
depends on ARCH_MEDIATEK && REGULATOR
|
||||
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
|
||||
index c0af1a1..e198752 100644
|
||||
--- a/drivers/cpufreq/Makefile
|
||||
+++ b/drivers/cpufreq/Makefile
|
||||
@@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += hisi-acpu-cpufreq.o
|
||||
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
|
||||
obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o
|
||||
obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
|
||||
+obj-$(CONFIG_ARM_MT7623_CPUFREQ) += mt7623-cpufreq.o
|
||||
obj-$(CONFIG_ARM_MT8173_CPUFREQ) += mt8173-cpufreq.o
|
||||
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
|
||||
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
|
||||
diff --git a/drivers/cpufreq/mt7623-cpufreq.c b/drivers/cpufreq/mt7623-cpufreq.c
|
||||
new file mode 100644
|
||||
index 0000000..8d154ce
|
||||
--- /dev/null
|
||||
+++ b/drivers/cpufreq/mt7623-cpufreq.c
|
||||
@@ -0,0 +1,389 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015 Linaro Ltd.
|
||||
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/cpu.h>
|
||||
+#include <linux/cpu_cooling.h>
|
||||
+#include <linux/cpufreq.h>
|
||||
+#include <linux/cpumask.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/pm_opp.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/thermal.h>
|
||||
+
|
||||
+#define VOLT_TOL (10000)
|
||||
+
|
||||
+/*
|
||||
+ * When scaling the clock frequency of a CPU clock domain, the clock source
|
||||
+ * needs to be switched to another stable PLL clock temporarily until
|
||||
+ * the original PLL becomes stable at target frequency.
|
||||
+ */
|
||||
+struct mtk_cpu_dvfs_info {
|
||||
+ struct device *cpu_dev;
|
||||
+ struct regulator *proc_reg;
|
||||
+ struct clk *cpu_clk;
|
||||
+ struct clk *inter_clk;
|
||||
+ struct thermal_cooling_device *cdev;
|
||||
+ int intermediate_voltage;
|
||||
+};
|
||||
+
|
||||
+static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
|
||||
+{
|
||||
+ return regulator_set_voltage(info->proc_reg, vproc,
|
||||
+ vproc + VOLT_TOL);
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
|
||||
+ unsigned int index)
|
||||
+{
|
||||
+ struct cpufreq_frequency_table *freq_table = policy->freq_table;
|
||||
+ struct clk *cpu_clk = policy->clk;
|
||||
+ struct clk *armpll = clk_get_parent(cpu_clk);
|
||||
+ struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
||||
+ struct device *cpu_dev = info->cpu_dev;
|
||||
+ struct dev_pm_opp *opp;
|
||||
+ long freq_hz, old_freq_hz;
|
||||
+ int vproc, old_vproc, inter_vproc, target_vproc, ret;
|
||||
+
|
||||
+ inter_vproc = info->intermediate_voltage;
|
||||
+
|
||||
+ old_freq_hz = clk_get_rate(cpu_clk);
|
||||
+ old_vproc = regulator_get_voltage(info->proc_reg);
|
||||
+
|
||||
+ freq_hz = freq_table[index].frequency * 1000;
|
||||
+
|
||||
+ rcu_read_lock();
|
||||
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
|
||||
+ if (IS_ERR(opp)) {
|
||||
+ rcu_read_unlock();
|
||||
+ pr_err("cpu%d: failed to find OPP for %ld\n",
|
||||
+ policy->cpu, freq_hz);
|
||||
+ return PTR_ERR(opp);
|
||||
+ }
|
||||
+ vproc = dev_pm_opp_get_voltage(opp);
|
||||
+ rcu_read_unlock();
|
||||
+
|
||||
+ /*
|
||||
+ * If the new voltage or the intermediate voltage is higher than the
|
||||
+ * current voltage, scale up voltage first.
|
||||
+ */
|
||||
+ target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
|
||||
+ if (old_vproc < target_vproc) {
|
||||
+ ret = mtk_cpufreq_set_voltage(info, target_vproc);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to scale up voltage!\n",
|
||||
+ policy->cpu);
|
||||
+ mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Reparent the CPU clock to intermediate clock. */
|
||||
+ ret = clk_set_parent(cpu_clk, info->inter_clk);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to re-parent cpu clock!\n",
|
||||
+ policy->cpu);
|
||||
+ mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
+ WARN_ON(1);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Set the original PLL to target rate. */
|
||||
+ ret = clk_set_rate(armpll, freq_hz);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to scale cpu clock rate!\n",
|
||||
+ policy->cpu);
|
||||
+ clk_set_parent(cpu_clk, armpll);
|
||||
+ mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Set parent of CPU clock back to the original PLL. */
|
||||
+ ret = clk_set_parent(cpu_clk, armpll);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to re-parent cpu clock!\n",
|
||||
+ policy->cpu);
|
||||
+ mtk_cpufreq_set_voltage(info, inter_vproc);
|
||||
+ WARN_ON(1);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * If the new voltage is lower than the intermediate voltage or the
|
||||
+ * original voltage, scale down to the new voltage.
|
||||
+ */
|
||||
+ if (vproc < inter_vproc || vproc < old_vproc) {
|
||||
+ ret = mtk_cpufreq_set_voltage(info, vproc);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to scale down voltage!\n",
|
||||
+ policy->cpu);
|
||||
+ clk_set_parent(cpu_clk, info->inter_clk);
|
||||
+ clk_set_rate(armpll, old_freq_hz);
|
||||
+ clk_set_parent(cpu_clk, armpll);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void mtk_cpufreq_ready(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
||||
+ struct device_node *np = of_node_get(info->cpu_dev->of_node);
|
||||
+
|
||||
+ if (WARN_ON(!np))
|
||||
+ return;
|
||||
+
|
||||
+ if (of_find_property(np, "#cooling-cells", NULL)) {
|
||||
+ info->cdev = of_cpufreq_cooling_register(np,
|
||||
+ policy->related_cpus);
|
||||
+
|
||||
+ if (IS_ERR(info->cdev)) {
|
||||
+ dev_err(info->cpu_dev,
|
||||
+ "running cpufreq without cooling device: %ld\n",
|
||||
+ PTR_ERR(info->cdev));
|
||||
+
|
||||
+ info->cdev = NULL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ of_node_put(np);
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
|
||||
+{
|
||||
+ struct device *cpu_dev;
|
||||
+ struct regulator *proc_reg = ERR_PTR(-ENODEV);
|
||||
+ struct clk *cpu_clk = ERR_PTR(-ENODEV);
|
||||
+ struct clk *inter_clk = ERR_PTR(-ENODEV);
|
||||
+ struct dev_pm_opp *opp;
|
||||
+ unsigned long rate;
|
||||
+ int ret;
|
||||
+
|
||||
+ cpu_dev = get_cpu_device(cpu);
|
||||
+ if (!cpu_dev) {
|
||||
+ pr_err("failed to get cpu%d device\n", cpu);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ cpu_clk = clk_get(cpu_dev, "cpu");
|
||||
+ if (IS_ERR(cpu_clk)) {
|
||||
+ if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
|
||||
+ pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
|
||||
+ else
|
||||
+ pr_err("failed to get cpu clk for cpu%d\n", cpu);
|
||||
+
|
||||
+ ret = PTR_ERR(cpu_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ inter_clk = clk_get(cpu_dev, "intermediate");
|
||||
+ if (IS_ERR(inter_clk)) {
|
||||
+ if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
|
||||
+ pr_warn("intermediate clk for cpu%d not ready, retry.\n",
|
||||
+ cpu);
|
||||
+ else
|
||||
+ pr_err("failed to get intermediate clk for cpu%d\n",
|
||||
+ cpu);
|
||||
+
|
||||
+ ret = PTR_ERR(inter_clk);
|
||||
+ goto out_free_resources;
|
||||
+ }
|
||||
+
|
||||
+ proc_reg = regulator_get_exclusive(cpu_dev, "proc");
|
||||
+ if (IS_ERR(proc_reg)) {
|
||||
+ if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
|
||||
+ pr_warn("proc regulator for cpu%d not ready, retry.\n",
|
||||
+ cpu);
|
||||
+ else
|
||||
+ pr_err("failed to get proc regulator for cpu%d\n",
|
||||
+ cpu);
|
||||
+
|
||||
+ ret = PTR_ERR(proc_reg);
|
||||
+ goto out_free_resources;
|
||||
+ }
|
||||
+
|
||||
+ ret = dev_pm_opp_of_add_table(cpu_dev);
|
||||
+ if (ret) {
|
||||
+ pr_warn("no OPP table for cpu%d\n", cpu);
|
||||
+ goto out_free_resources;
|
||||
+ }
|
||||
+
|
||||
+ /* Search a safe voltage for intermediate frequency. */
|
||||
+ rate = clk_get_rate(inter_clk);
|
||||
+ rcu_read_lock();
|
||||
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
|
||||
+ if (IS_ERR(opp)) {
|
||||
+ rcu_read_unlock();
|
||||
+ pr_err("failed to get intermediate opp for cpu%d\n", cpu);
|
||||
+ ret = PTR_ERR(opp);
|
||||
+ goto out_free_opp_table;
|
||||
+ }
|
||||
+ info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
|
||||
+ rcu_read_unlock();
|
||||
+
|
||||
+ info->cpu_dev = cpu_dev;
|
||||
+ info->proc_reg = proc_reg;
|
||||
+ info->cpu_clk = cpu_clk;
|
||||
+ info->inter_clk = inter_clk;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+out_free_opp_table:
|
||||
+ dev_pm_opp_of_remove_table(cpu_dev);
|
||||
+
|
||||
+out_free_resources:
|
||||
+ if (!IS_ERR(proc_reg))
|
||||
+ regulator_put(proc_reg);
|
||||
+ if (!IS_ERR(cpu_clk))
|
||||
+ clk_put(cpu_clk);
|
||||
+ if (!IS_ERR(inter_clk))
|
||||
+ clk_put(inter_clk);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
|
||||
+{
|
||||
+ if (!IS_ERR(info->proc_reg))
|
||||
+ regulator_put(info->proc_reg);
|
||||
+ if (!IS_ERR(info->cpu_clk))
|
||||
+ clk_put(info->cpu_clk);
|
||||
+ if (!IS_ERR(info->inter_clk))
|
||||
+ clk_put(info->inter_clk);
|
||||
+
|
||||
+ dev_pm_opp_of_remove_table(info->cpu_dev);
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpufreq_init(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ struct mtk_cpu_dvfs_info *info;
|
||||
+ struct cpufreq_frequency_table *freq_table;
|
||||
+ int ret;
|
||||
+
|
||||
+ info = kzalloc(sizeof(*info), GFP_KERNEL);
|
||||
+ if (!info)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ ret = mtk_cpu_dvfs_info_init(info, policy->cpu);
|
||||
+ if (ret) {
|
||||
+ pr_err("%s failed to initialize dvfs info for cpu%d\n",
|
||||
+ __func__, policy->cpu);
|
||||
+ goto out_free_dvfs_info;
|
||||
+ }
|
||||
+
|
||||
+ ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
|
||||
+ if (ret) {
|
||||
+ pr_err("failed to init cpufreq table for cpu%d: %d\n",
|
||||
+ policy->cpu, ret);
|
||||
+ goto out_release_dvfs_info;
|
||||
+ }
|
||||
+
|
||||
+ ret = cpufreq_table_validate_and_show(policy, freq_table);
|
||||
+ if (ret) {
|
||||
+ pr_err("%s: invalid frequency table: %d\n", __func__, ret);
|
||||
+ goto out_free_cpufreq_table;
|
||||
+ }
|
||||
+
|
||||
+ /* CPUs in the same cluster share a clock and power domain. */
|
||||
+ cpumask_setall(policy->cpus);
|
||||
+ policy->driver_data = info;
|
||||
+ policy->clk = info->cpu_clk;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+out_free_cpufreq_table:
|
||||
+ dev_pm_opp_free_cpufreq_table(info->cpu_dev, &freq_table);
|
||||
+
|
||||
+out_release_dvfs_info:
|
||||
+ mtk_cpu_dvfs_info_release(info);
|
||||
+
|
||||
+out_free_dvfs_info:
|
||||
+ kfree(info);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
||||
+
|
||||
+ cpufreq_cooling_unregister(info->cdev);
|
||||
+ dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
|
||||
+ mtk_cpu_dvfs_info_release(info);
|
||||
+ kfree(info);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct cpufreq_driver mt7623_cpufreq_driver = {
|
||||
+ .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
|
||||
+ .verify = cpufreq_generic_frequency_table_verify,
|
||||
+ .target_index = mtk_cpufreq_set_target,
|
||||
+ .get = cpufreq_generic_get,
|
||||
+ .init = mtk_cpufreq_init,
|
||||
+ .exit = mtk_cpufreq_exit,
|
||||
+ .ready = mtk_cpufreq_ready,
|
||||
+ .name = "mtk-cpufreq",
|
||||
+ .attr = cpufreq_generic_attr,
|
||||
+};
|
||||
+
|
||||
+static int mt7623_cpufreq_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = cpufreq_register_driver(&mt7623_cpufreq_driver);
|
||||
+ if (ret)
|
||||
+ pr_err("failed to register mtk cpufreq driver\n");
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver mt7623_cpufreq_platdrv = {
|
||||
+ .driver = {
|
||||
+ .name = "mt7623-cpufreq",
|
||||
+ },
|
||||
+ .probe = mt7623_cpufreq_probe,
|
||||
+};
|
||||
+
|
||||
+static int mt7623_cpufreq_driver_init(void)
|
||||
+{
|
||||
+ struct platform_device *pdev;
|
||||
+ int err;
|
||||
+
|
||||
+ if (!of_machine_is_compatible("mediatek,mt7623"))
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ err = platform_driver_register(&mt7623_cpufreq_platdrv);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ /*
|
||||
+ * Since there's no place to hold device registration code and no
|
||||
+ * device tree based way to match cpufreq driver yet, both the driver
|
||||
+ * and the device registration codes are put here to handle defer
|
||||
+ * probing.
|
||||
+ */
|
||||
+ pdev = platform_device_register_simple("mt7623-cpufreq", -1, NULL, 0);
|
||||
+ if (IS_ERR(pdev)) {
|
||||
+ pr_err("failed to register mtk-cpufreq platform device\n");
|
||||
+ return PTR_ERR(pdev);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+device_initcall(mt7623_cpufreq_driver_init);
|
||||
--
|
||||
1.7.10.4
|
||||
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
From e722886f122fd3dd6240160f21937d2f21e9d910 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 31 Mar 2016 06:07:01 +0200
|
||||
Subject: [PATCH 78/78] arm: mediatek: make a7 timer work Signed-off-by: John
|
||||
Crispin <blogic@openwrt.org>
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/mt7623.dtsi | 2 ++
|
||||
arch/arm/mach-mediatek/Kconfig | 1 +
|
||||
arch/arm/mach-mediatek/mediatek.c | 1 +
|
||||
3 files changed, 4 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
|
||||
index 76d603a..cd08b6e 100644
|
||||
--- a/arch/arm/boot/dts/mt7623.dtsi
|
||||
+++ b/arch/arm/boot/dts/mt7623.dtsi
|
||||
@@ -120,6 +120,8 @@
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ clock-frequency = <13000000>;
|
||||
+ arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
topckgen: power-controller@10000000 {
|
||||
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
|
||||
index a7fef77..2c05bc31 100644
|
||||
--- a/arch/arm/mach-mediatek/Kconfig
|
||||
+++ b/arch/arm/mach-mediatek/Kconfig
|
||||
@@ -24,6 +24,7 @@ config MACH_MT6592
|
||||
config MACH_MT7623
|
||||
bool "MediaTek MT7623 SoCs support"
|
||||
default ARCH_MEDIATEK
|
||||
+ select HAVE_ARM_ARCH_TIMER
|
||||
select MIGHT_HAVE_PCI
|
||||
|
||||
config MACH_MT8127
|
||||
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
|
||||
index bcfca37..7553a8c 100644
|
||||
--- a/arch/arm/mach-mediatek/mediatek.c
|
||||
+++ b/arch/arm/mach-mediatek/mediatek.c
|
||||
@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void)
|
||||
void __iomem *gpt_base;
|
||||
|
||||
if (of_machine_is_compatible("mediatek,mt6589") ||
|
||||
+ of_machine_is_compatible("mediatek,mt7623") ||
|
||||
of_machine_is_compatible("mediatek,mt8135") ||
|
||||
of_machine_is_compatible("mediatek,mt8127")) {
|
||||
/* turn on GPT6 which ungates arch timer clocks */
|
||||
--
|
||||
1.7.10.4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user