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switch to 2.6.38 

SVN-Revision: 31546
This commit is contained in:
Imre Kaloz 2012-05-01 07:00:17 +00:00
parent 7a8d12bafa
commit 880de62f91
117 changed files with 91478 additions and 21919 deletions
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4
target/linux/coldfire/Makefile
View File

@ -1,5 +1,5 @@
#
# Copyright (C) 2009-2010 OpenWrt.org
# Copyright (C) 2009-2012 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
@ -12,7 +12,7 @@ BOARDNAME:=Freescale Coldfire v4e
FEATURES:=squashfs broken
MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
LINUX_VERSION:=2.6.31.14
LINUX_VERSION:=2.6.38.8
include $(INCLUDE_DIR)/target.mk

6
target/linux/coldfire/config-default
View File

@ -34,7 +34,7 @@ CONFIG_COLDFIRE=y
CONFIG_FEC_548x_AUTO_NEGOTIATION=y
CONFIG_FEC_548x_ENABLE_FEC2=y
CONFIG_FEC_548x=y
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_IOMAP=y
# CONFIG_GENERIC_TIME is not set
# CONFIG_GEN_RTC is not set
@ -80,6 +80,8 @@ CONFIG_MCF_USER_HALT=y
CONFIG_MMU_CFV4E=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
# CONFIG_MTD_CFI_GEOMETRY is not set
# CONFIG_NATIONAL8364x_PHY is not set
# CONFIG_NATIONAL8384x_PHY is not set
# CONFIG_NE2K_PCI is not set
CONFIG_NEED_MULTIPLE_NODES=y
# CONFIG_NETDEV_1000 is not set
@ -87,11 +89,13 @@ CONFIG_NEED_MULTIPLE_NODES=y
# CONFIG_NO_DMA is not set
# CONFIG_NO_IOPORT is not set
CONFIG_NOR_FLASH_BASE=0xE0000000
CONFIG_PCI=y
CONFIG_PCI_LEGACY=y
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_PROC_HARDWARE is not set
# CONFIG_Q40 is not set
# CONFIG_R6040 is not set
# CONFIG_SERIAL_PCH_UART is not set
# CONFIG_RMW_INSNS is not set
# CONFIG_SCSI_DMA is not set
CONFIG_SDRAM_BASE=0x00000000

68
target/linux/coldfire/files-2.6.31/arch/m68k/boot/Makefile
View File

@ -1,68 +0,0 @@
#
# arch/m68k/boot/Makefile
#
# Based on arch/sh/boot/Makefile by Stuart Menefy
#
# Copyright (c) 2008 Freescale Semiconductor, Inc. All Rights Reserved.
# by Kurt Mahan <kmahan@freescale.com>
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
MKIMAGE := $(srctree)/scripts/mkuboot.sh
#
# Assign safe dummy values if these variables are not defined,
# in order to suppress error message.
#
CONFIG_SDRAM_BASE ?= 0x40000000
CONFIG_IMG_START ?= 0x00020000
export CONFIG_SDRAM_BASE CONFIG_IMG_START
targets := zImage zImage.srec vmlinux.srec uImage uImage.srec
$(obj)/zImage: $(obj)/vmlinux.bin FORCE
$(call if_changed,gzip)
@echo ' Image $@ is ready'
OBJCOPYFLAGS_zImage.srec := -I binary -O srec
$(obj)/zImage.srec: $(obj)/zImage
$(call if_changed,objcopy)
KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \
$$[$(CONFIG_SDRAM_BASE) + \
$(CONFIG_IMG_START)]')
KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \
$$[$(CONFIG_SDRAM_BASE) + \
$(CONFIG_IMG_START)]')
quiet_cmd_uimage = UIMAGE $@
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A m68k -O linux -T kernel \
-C gzip -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \
-n 'Linux-$(KERNELRELEASE)' -d $< $@
$(obj)/uImage: $(obj)/vmlinux.bin.gz FORCE
$(call if_changed,uimage)
@echo ' Image $@ is ready'
$(obj)/vmlinux.bin: vmlinux FORCE
$(call if_changed,objcopy)
$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
$(call if_changed,gzip)
OBJCOPYFLAGS_vmlinux.srec := -I binary -O srec
$(obj)/vmlinux.srec: $(obj)/vmlinux.bin
$(call if_changed,objcopy)
OBJCOPYFLAGS_uImage.srec := -I binary -O srec
$(obj)/uImage.srec: $(obj)/uImage
$(call if_changed,objcopy)
clean-files += uImage uImage.srec \
zImage zImage.srec \
vmlinux.srec vmlinux.bin vmlinux.bin.gz

9
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/Makefile
View File

@ -1,9 +0,0 @@
#
# Makefile for Linux arch/m68k/coldfire source directory
#
obj-y += common/
obj-$(CONFIG_VDSO) += vdso/
obj-$(CONFIG_M5445X) += m5445x/
obj-$(CONFIG_M547X_8X) += m547x/

7
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/Makefile
View File

@ -1,7 +0,0 @@
#
# Makefile for Linux arch/m68k/coldfire/common source directory
#
obj-y:= entry.o cache.o signal.o muldi3.o traps.o ints.o time.o
extra-y:= head.o

45
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/cache.c
View File

@ -1,45 +0,0 @@
/*
* linux/arch/m68k/coldfire/cache.c
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Matt Waddel Matt.Waddel@freescale.com
* Kurt Mahan kmahan@freescale.com
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/interrupt.h>
#include <asm/cfcache.h>
#include <asm/coldfire.h>
#include <asm/system.h>
/* Cache Control Reg shadow reg */
unsigned long shadow_cacr;
/**
* cacr_set - Set the Cache Control Register
* @x Value to set
*/
void cacr_set(unsigned long x)
{
shadow_cacr = x;
__asm__ __volatile__ ("movec %0, %%cacr"
: /* no outputs */
: "r" (shadow_cacr));
}
/**
* cacr_get - Get the current value of the Cache Control Register
*
* @return CACR value
*/
unsigned long cacr_get(void)
{
return shadow_cacr;
}

749
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/entry.S
View File

@ -1,749 +0,0 @@
/*
* arch/m68k/coldfire/entry.S
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Matt Waddel Matt.Waddel@freescale.com
* Kurt Mahan kmahan@freescale.com
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*
* Based on:
*
* arch/m68knommu/platform/5307/entry.S &
* arch/m68k/kernel/entry.S
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file README.legal in the main directory of this archive
* for more details.
*/
#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/cf_entry.h>
#include <asm/errno.h>
#include <asm/setup.h>
#include <asm/segment.h>
#include <asm/traps.h>
#include <asm/unistd.h>
/*
* TASK_INFO:
*
* - TINFO_PREEMPT (struct thread_info / preempt_count)
* Used to keep track of preemptability
* - TINFO_FLAGS (struct thread_info / flags - include/asm-m68k/thread_info.h)
* Various bit flags that are checked for scheduling/tracing
* Bits 0-7 are checked every exception exit
* 8-15 are checked every syscall exit
*
* TIF_SIGPENDING 6
* TIF_NEED_RESCHED 7
* TIF_DELAYED_TRACE 14
* TIF_SYSCALL_TRACE 15
* TIF_MEMDIE 16 (never checked here)
*/
.bss
sw_ksp:
.long 0
sw_usp:
.long 0
.text
.globl system_call
.globl buserr
.globl trap
.globl resume
.globl ret_from_exception
.globl ret_from_signal
.globl sys_call_table
.globl ret_from_interrupt
.globl inthandler
ENTRY(buserr)
#ifdef CONFIG_COLDFIRE_FOO
movew #0x2700,%sr /* lock interrupts */
#endif
SAVE_ALL_INT
#ifdef CONFIG_COLDFIRE_FOO
movew PT_SR(%sp),%d3 /* get original %sr */
oril #0x2000,%d3 /* set supervisor mode in it */
movew %d3,%sr /* recover irq state */
#endif
GET_CURRENT(%d0)
movel %sp,%sp@- /* stack frame pointer argument */
jsr buserr_c
addql #4,%sp
jra .Lret_from_exception
ENTRY(trap)
SAVE_ALL_INT
GET_CURRENT(%d0)
movel %sp,%sp@- /* stack frame pointer argument */
jsr trap_c
addql #4,%sp
jra .Lret_from_exception
/* After a fork we jump here directly from resume,
%d1 contains the previous task schedule_tail */
ENTRY(ret_from_fork)
movel %d1,%sp@-
jsr schedule_tail
addql #4,%sp
jra .Lret_from_exception
do_trace_entry:
movel #-ENOSYS,%d1 /* needed for strace */
movel %d1,%sp@(PT_D0)
subql #4,%sp
SAVE_SWITCH_STACK
jbsr syscall_trace
RESTORE_SWITCH_STACK
addql #4,%sp
movel %sp@(PT_ORIG_D0),%d0
cmpl #NR_syscalls,%d0
jcs syscall
badsys:
movel #-ENOSYS,%d1
movel %d1,%sp@(PT_D0)
jra ret_from_exception
do_trace_exit:
subql #4,%sp
SAVE_SWITCH_STACK
jbsr syscall_trace
RESTORE_SWITCH_STACK
addql #4,%sp
jra .Lret_from_exception
ENTRY(ret_from_signal)
RESTORE_SWITCH_STACK
addql #4,%sp
jra .Lret_from_exception
ENTRY(system_call)
SAVE_ALL_SYS
GET_CURRENT(%d1)
/* save top of frame */
movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
/* syscall trace */
tstb %curptr@(TASK_INFO+TINFO_FLAGS+2)
jmi do_trace_entry /* SYSCALL_TRACE is set */
cmpl #NR_syscalls,%d0
jcc badsys
syscall:
movel #sys_call_table,%a0
asll #2,%d0
addl %d0,%a0
movel %a0@,%a0
jsr %a0@
movel %d0,%sp@(PT_D0) /* save the return value */
ret_from_syscall:
movew %curptr@(TASK_INFO+TINFO_FLAGS+2),%d0
jne syscall_exit_work /* flags set so process */
1: RESTORE_ALL
syscall_exit_work:
btst #5,%sp@(PT_SR) /* check if returning to kernel */
bnes 1b /* if so, skip resched, signals */
btstl #15,%d0 /* check if SYSCALL_TRACE */
jne do_trace_exit
btstl #14,%d0 /* check if DELAYED_TRACE */
jne do_delayed_trace
btstl #6,%d0 /* check if SIGPENDING */
jne do_signal_return
pea resume_userspace
jra schedule
ENTRY(ret_from_exception)
.Lret_from_exception:
btst #5,%sp@(PT_SR) /* check if returning to kernel */
bnes 1f /* if so, skip resched, signals */
movel %d0,%sp@- /* Only allow interrupts when we are */
move %sr,%d0 /* last one on the kernel stack, */
andl #ALLOWINT,%d0 /* otherwise stack overflow can occur */
move %d0,%sr /* during heavy interrupt load. */
movel %sp@+,%d0
resume_userspace:
moveb %curptr@(TASK_INFO+TINFO_FLAGS+3),%d0
jne exit_work /* SIGPENDING and/or NEED_RESCHED set */
1: RESTORE_ALL
exit_work:
/* save top of frame */
movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
btstl #6,%d0 /* check for SIGPENDING in flags */
jne do_signal_return
pea resume_userspace
jra schedule
do_signal_return:
subql #4,%sp /* dummy return address */
SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
clrl %sp@-
bsrl do_signal
addql #8,%sp
RESTORE_SWITCH_STACK
addql #4,%sp
jbra resume_userspace
do_delayed_trace:
bclr #7,%sp@(PT_SR) /* clear trace bit in SR */
pea 1 /* send SIGTRAP */
movel %curptr,%sp@-
pea LSIGTRAP
jbsr send_sig
addql #8,%sp
addql #4,%sp
jbra resume_userspace
/*
* This is the interrupt handler (for all hardware interrupt
* sources). It figures out the vector number and calls the appropriate
* interrupt service routine directly.
*/
ENTRY(inthandler)
SAVE_ALL_INT
GET_CURRENT(%d0)
movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0
addil #0x10000,%d0
movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT)
/* put exception # in d0 */
movel %sp@(PT_VECTOR),%d0
swap %d0 /* extract bits 25:18 */
lsrl #2,%d0
andl #0x0ff,%d0
movel %sp,%sp@-
movel %d0,%sp@- /* put vector # on stack */
auto_irqhandler_fixup = . + 2
jbsr process_int /* process the IRQ */
addql #8,%sp /* pop parameters off stack */
ret_from_interrupt:
movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0
subil #0x10000,%d0
movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT)
jeq ret_from_last_interrupt
2: RESTORE_ALL
ALIGN
ret_from_last_interrupt:
moveb %sp@(PT_SR),%d0
andl #(~ALLOWINT>>8)&0xff,%d0
jne 2b
/* check if we need to do software interrupts */
tstl irq_stat+CPUSTAT_SOFTIRQ_PENDING
jeq .Lret_from_exception
pea ret_from_exception
jra do_softirq
ENTRY(user_inthandler)
SAVE_ALL_INT
GET_CURRENT(%d0)
movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0
addil #0x10000,%d0
movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT)
/* put exception # in d0 */
movel %sp@(PT_VECTOR),%d0
user_irqvec_fixup = . + 2
swap %d0 /* extract bits 25:18 */
lsrl #2,%d0
andl #0x0ff,%d0
movel %sp,%sp@-
movel %d0,%sp@- /* put vector # on stack */
user_irqhandler_fixup = . + 2
jbsr process_int /* process the IRQ */
addql #8,%sp /* pop parameters off stack */
movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0
subil #0x10000,%d0
movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT)
jeq ret_from_last_interrupt
RESTORE_ALL
/* Handler for uninitialized and spurious interrupts */
ENTRY(bad_inthandler)
SAVE_ALL_INT
GET_CURRENT(%d0)
movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0
addil #0x10000,%d0
movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT)
movel %sp,%sp@-
jsr handle_badint
addql #4,%sp
movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0
subil #0x10000,%d0
movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT)
jeq ret_from_last_interrupt
RESTORE_ALL
ENTRY(sys_fork)
SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
jbsr m68k_fork
addql #4,%sp
RESTORE_SWITCH_STACK
rts
ENTRY(sys_clone)
SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
jbsr m68k_clone
addql #4,%sp
RESTORE_SWITCH_STACK
rts
ENTRY(sys_vfork)
SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
jbsr m68k_vfork
addql #4,%sp
RESTORE_SWITCH_STACK
rts
ENTRY(sys_sigsuspend)
SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
jbsr do_sigsuspend
addql #4,%sp
RESTORE_SWITCH_STACK
rts
ENTRY(sys_rt_sigsuspend)
SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
jbsr do_rt_sigsuspend
addql #4,%sp
RESTORE_SWITCH_STACK
rts
ENTRY(sys_sigreturn)
SAVE_SWITCH_STACK
jbsr do_sigreturn
RESTORE_SWITCH_STACK
rts
ENTRY(sys_rt_sigreturn)
SAVE_SWITCH_STACK
jbsr do_rt_sigreturn
RESTORE_SWITCH_STACK
rts
resume:
/*
* Beware - when entering resume, prev (the current task) is
* in a0, next (the new task) is in a1,so don't change these
* registers until their contents are no longer needed.
*/
/* save sr */
movew %sr,%d0
movew %d0,%a0@(TASK_THREAD+THREAD_SR)
/* save usp */
/* Save USP via %a1 (which is saved/restored from %d0) */
movel %a1,%d0
movel %usp,%a1
movel %a1,%a0@(TASK_THREAD+THREAD_USP)
movel %d0,%a1
/* save non-scratch registers on stack */
SAVE_SWITCH_STACK
/* save current kernel stack pointer */
movel %sp,%a0@(TASK_THREAD+THREAD_KSP)
#ifdef CONFIG_FPU
/* save floating point context */
fsave %a0@(TASK_THREAD+THREAD_FPSTATE)
1: tstb %a0@(TASK_THREAD+THREAD_FPSTATE)
jeq 3f
2:
fmovemd %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG)
3:
#endif
/* Return previous task in %d1 */
movel %curptr,%d1
/* switch to new task (a1 contains new task) */
movel %a1,%curptr
#ifdef CONFIG_FPU
/* restore floating point context */
1: tstb %a1@(TASK_THREAD+THREAD_FPSTATE)
jeq 3f
2:
fmovemd %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7
/* frestore %a1@(TASK_THREAD+THREAD_FPCNTL)*/
3: frestore %a1@(TASK_THREAD+THREAD_FPSTATE)
#endif
/* restore the kernel stack pointer */
movel %a1@(TASK_THREAD+THREAD_KSP),%sp
/* restore non-scratch registers */
RESTORE_SWITCH_STACK
/* restore user stack pointer */
movel %a1@(TASK_THREAD+THREAD_USP),%a0
movel %a0,%usp
/* restore status register */
movew %a1@(TASK_THREAD+THREAD_SR),%d0
movew %d0,%sr
rts
.data
ALIGN
sys_call_table:
.long sys_ni_syscall /* 0 - old "setup()" system call*/
.long sys_exit
.long sys_fork
.long sys_read
.long sys_write
.long sys_open /* 5 */
.long sys_close
.long sys_waitpid
.long sys_creat
.long sys_link
.long sys_unlink /* 10 */
.long sys_execve
.long sys_chdir
.long sys_time
.long sys_mknod
.long sys_chmod /* 15 */
.long sys_chown16
.long sys_ni_syscall /* old break syscall holder */
.long sys_stat
.long sys_lseek
.long sys_getpid /* 20 */
.long sys_mount
.long sys_oldumount
.long sys_setuid16
.long sys_getuid16
.long sys_stime /* 25 */
.long sys_ptrace
.long sys_alarm
.long sys_fstat
.long sys_pause
.long sys_utime /* 30 */
.long sys_ni_syscall /* old stty syscall holder */
.long sys_ni_syscall /* old gtty syscall holder */
.long sys_access
.long sys_nice
.long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
.long sys_sync
.long sys_kill
.long sys_rename
.long sys_mkdir
.long sys_rmdir /* 40 */
.long sys_dup
.long sys_pipe
.long sys_times
.long sys_ni_syscall /* old prof syscall holder */
.long sys_brk /* 45 */
.long sys_setgid16
.long sys_getgid16
.long sys_signal
.long sys_geteuid16
.long sys_getegid16 /* 50 */
.long sys_acct
.long sys_umount /* recycled never used phys() */
.long sys_ni_syscall /* old lock syscall holder */
.long sys_ioctl
.long sys_fcntl /* 55 */
.long sys_ni_syscall /* old mpx syscall holder */
.long sys_setpgid
.long sys_ni_syscall /* old ulimit syscall holder */
.long sys_ni_syscall
.long sys_umask /* 60 */
.long sys_chroot
.long sys_ustat
.long sys_dup2
.long sys_getppid
.long sys_getpgrp /* 65 */
.long sys_setsid
.long sys_sigaction
.long sys_sgetmask
.long sys_ssetmask
.long sys_setreuid16 /* 70 */
.long sys_setregid16
.long sys_sigsuspend
.long sys_sigpending
.long sys_sethostname
.long sys_setrlimit /* 75 */
.long sys_old_getrlimit
.long sys_getrusage
.long sys_gettimeofday
.long sys_settimeofday
.long sys_getgroups16 /* 80 */
.long sys_setgroups16
.long old_select
.long sys_symlink
.long sys_lstat
.long sys_readlink /* 85 */
.long sys_uselib
.long sys_swapon
.long sys_reboot
.long sys_old_readdir
.long old_mmap /* 90 */
.long sys_munmap
.long sys_truncate
.long sys_ftruncate
.long sys_fchmod
.long sys_fchown16 /* 95 */
.long sys_getpriority
.long sys_setpriority
.long sys_ni_syscall /* old profil syscall holder */
.long sys_statfs
.long sys_fstatfs /* 100 */
.long sys_ni_syscall /* ioperm for i386 */
.long sys_socketcall
.long sys_syslog
.long sys_setitimer
.long sys_getitimer /* 105 */
.long sys_newstat
.long sys_newlstat
.long sys_newfstat
.long sys_ni_syscall
.long sys_ni_syscall /* 110 */ /* iopl for i386 */
.long sys_vhangup
.long sys_ni_syscall /* obsolete idle() syscall */
.long sys_ni_syscall /* vm86old for i386 */
.long sys_wait4
.long sys_swapoff /* 115 */
.long sys_sysinfo
.long sys_ipc
.long sys_fsync
.long sys_sigreturn
.long sys_clone /* 120 */
.long sys_setdomainname
.long sys_newuname
.long sys_cacheflush /* modify_ldt for i386 */
.long sys_adjtimex
.long sys_mprotect /* 125 */
.long sys_sigprocmask
.long sys_ni_syscall /* old "create_module" */
.long sys_init_module
.long sys_delete_module
.long sys_ni_syscall /* 130 - old "get_kernel_syms" */
.long sys_quotactl
.long sys_getpgid
.long sys_fchdir
.long sys_bdflush
.long sys_sysfs /* 135 */
.long sys_personality
.long sys_ni_syscall /* for afs_syscall */
.long sys_setfsuid16
.long sys_setfsgid16
.long sys_llseek /* 140 */
.long sys_getdents
.long sys_select
.long sys_flock
.long sys_msync
.long sys_readv /* 145 */
.long sys_writev
.long sys_getsid
.long sys_fdatasync
.long sys_sysctl
.long sys_mlock /* 150 */
.long sys_munlock
.long sys_mlockall
.long sys_munlockall
.long sys_sched_setparam
.long sys_sched_getparam /* 155 */
.long sys_sched_setscheduler
.long sys_sched_getscheduler
.long sys_sched_yield
.long sys_sched_get_priority_max
.long sys_sched_get_priority_min /* 160 */
.long sys_sched_rr_get_interval
.long sys_nanosleep
.long sys_mremap
.long sys_setresuid16
.long sys_getresuid16 /* 165 */
.long sys_getpagesize
.long sys_ni_syscall /* old sys_query_module */
.long sys_poll
.long sys_nfsservctl
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl
.long sys_rt_sigreturn
.long sys_rt_sigaction
.long sys_rt_sigprocmask /* 175 */
.long sys_rt_sigpending
.long sys_rt_sigtimedwait
.long sys_rt_sigqueueinfo
.long sys_rt_sigsuspend
.long sys_pread64 /* 180 */
.long sys_pwrite64
.long sys_lchown16;
.long sys_getcwd
.long sys_capget
.long sys_capset /* 185 */
.long sys_sigaltstack
.long sys_sendfile
.long sys_ni_syscall /* streams1 */
.long sys_ni_syscall /* streams2 */
.long sys_vfork /* 190 */
.long sys_getrlimit
.long sys_mmap2
.long sys_truncate64
.long sys_ftruncate64
.long sys_stat64 /* 195 */
.long sys_lstat64
.long sys_fstat64
.long sys_chown
.long sys_getuid
.long sys_getgid /* 200 */
.long sys_geteuid
.long sys_getegid
.long sys_setreuid
.long sys_setregid
.long sys_getgroups /* 205 */
.long sys_setgroups
.long sys_fchown
.long sys_setresuid
.long sys_getresuid
.long sys_setresgid /* 210 */
.long sys_getresgid
.long sys_lchown
.long sys_setuid
.long sys_setgid
.long sys_setfsuid /* 215 */
.long sys_setfsgid
.long sys_pivot_root
.long sys_ni_syscall
.long sys_ni_syscall
.long sys_getdents64 /* 220 */
.long sys_gettid
.long sys_tkill
.long sys_setxattr
.long sys_lsetxattr
.long sys_fsetxattr /* 225 */
.long sys_getxattr
.long sys_lgetxattr
.long sys_fgetxattr
.long sys_listxattr
.long sys_llistxattr /* 230 */
.long sys_flistxattr
.long sys_removexattr
.long sys_lremovexattr
.long sys_fremovexattr
.long sys_futex /* 235 */
.long sys_sendfile64
.long sys_mincore
.long sys_madvise
.long sys_fcntl64
.long sys_readahead /* 240 */
.long sys_io_setup
.long sys_io_destroy
.long sys_io_getevents
.long sys_io_submit
.long sys_io_cancel /* 245 */
.long sys_fadvise64
.long sys_exit_group
.long sys_lookup_dcookie
.long sys_epoll_create
.long sys_epoll_ctl /* 250 */
.long sys_epoll_wait
.long sys_remap_file_pages
.long sys_set_tid_address
.long sys_timer_create
.long sys_timer_settime /* 255 */
.long sys_timer_gettime
.long sys_timer_getoverrun
.long sys_timer_delete
.long sys_clock_settime
.long sys_clock_gettime /* 260 */
.long sys_clock_getres
.long sys_clock_nanosleep
.long sys_statfs64
.long sys_fstatfs64
.long sys_tgkill /* 265 */
.long sys_utimes
.long sys_fadvise64_64
.long sys_mbind
.long sys_get_mempolicy
.long sys_set_mempolicy /* 270 */
.long sys_mq_open
.long sys_mq_unlink
.long sys_mq_timedsend
.long sys_mq_timedreceive
.long sys_mq_notify /* 275 */
.long sys_mq_getsetattr
.long sys_waitid
.long sys_ni_syscall /* for sys_vserver */
.long sys_add_key
.long sys_request_key /* 280 */
.long sys_keyctl
.long sys_ioprio_set
.long sys_ioprio_get
.long sys_inotify_init
.long sys_inotify_add_watch /* 285 */
.long sys_inotify_rm_watch
.long sys_migrate_pages
.long sys_openat
.long sys_mkdirat
.long sys_mknodat /* 290 */
.long sys_fchownat
.long sys_futimesat
.long sys_fstatat64
.long sys_unlinkat
.long sys_renameat /* 295 */
.long sys_linkat
.long sys_symlinkat
.long sys_readlinkat
.long sys_fchmodat
.long sys_faccessat /* 300 */
.long sys_ni_syscall /* Reserved for pselect6 */
.long sys_ni_syscall /* Reserved for ppoll */
.long sys_unshare
.long sys_set_robust_list
.long sys_get_robust_list /* 305 */
.long sys_splice
.long sys_sync_file_range
.long sys_tee
.long sys_vmsplice
.long sys_move_pages /* 310 */
.long sys_sched_setaffinity
.long sys_sched_getaffinity
.long sys_kexec_load
.long sys_getcpu
.long sys_epoll_pwait /* 315 */
.long sys_utimensat
.long sys_signalfd
.long sys_timerfd_create
.long sys_eventfd
.long sys_fallocate /* 320 */
.long sys_timerfd_settime
.long sys_timerfd_gettime
.long sys_signalfd4
.long sys_eventfd2
.long sys_epoll_create1 /* 325 */
.long sys_dup3
.long sys_pipe2
.long sys_inotify_init1
.long sys_ni_syscall /* Reserved */
.long sys_ni_syscall /* 330 Reserved */
.long sys_ni_syscall /* Reserved */
.long sys_ni_syscall /* Reserved */
.long sys_read_tp
.long sys_write_tp
.long sys_atomic_cmpxchg_32 /* 335 */
.long sys_atomic_barrier

700
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/head.S
View File

@ -1,700 +0,0 @@
/*
* head.S is the MMU enabled ColdFire specific initial boot code
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Matt Waddel Matt.Waddel@freescale.com
* Kurt Mahan kmahan@freescale.com
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Parts of this code came from arch/m68k/kernel/head.S
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/bootinfo.h>
#include <asm/setup.h>
#include <asm/entry.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/coldfire.h>
#include <asm/cfcache.h>
#define DEBUG
.globl kernel_pg_dir
.globl availmem
.globl set_context
.globl set_fpga
#ifdef DEBUG
/* When debugging use readable names for labels */
#ifdef __STDC__
#define L(name) .head.S.##name
#else
#define L(name) .head.S./**/name
#endif
#else
#ifdef __STDC__
#define L(name) .L##name
#else
#define L(name) .L/**/name
#endif
#endif
/* The __INITDATA stuff is a no-op when ftrace or kgdb are turned on */
#ifndef __INITDATA
#define __INITDATA .data
#define __FINIT .previous
#endif
#if CONFIG_SDRAM_BASE != PAGE_OFFSET
/*
* Kernel mapped to virtual ram address.
*
* M5445x:
* Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
* Data[1]: 0xA0000000 -> 0xAFFFFFFF PCI
* Code[0]: Not Mapped
* Code[1]: Not Mapped
*
* M547x/M548x
* Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
* Data[1]: Not Mapped
* Code[0]: Not Mapped
* Code[1]: Not Mapped
*/
#if defined(CONFIG_M5445X)
#define ACR0_DEFAULT #0xF00FA048 /* System regs */
#define ACR1_DEFAULT #0xA00FA048 /* PCI */
#define ACR2_DEFAULT #0x00000000 /* Not Mapped */
#define ACR3_DEFAULT #0x00000000 /* Not Mapped */
#elif defined(CONFIG_M547X_8X)
#define ACR0_DEFAULT #0xF00FA048 /* System Regs */
#define ACR1_DEFAULT #0x00000000 /* Not Mapped */
#define ACR2_DEFAULT #0x00000000 /* Not Mapped */
#define ACR3_DEFAULT #0x00000000 /* Not Mapped */
#endif
#else /* CONFIG_SDRAM_BASE = PAGE_OFFSET */
/*
* Kernel mapped to physical ram address.
*
* M5445x:
* Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
* Data[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - uncached
* Code[0]: Not Mapped
* Code[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached
*
* M547x/M548x
* Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
* Data[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - uncached
* Code[0]: Not Mapped
* Code[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - cached
*/
#if defined(CONFIG_M5445X)
#define ACR0_DEFAULT #0xF00FA048 /* System Regs uncached/precise */
#define ACR1_DEFAULT #0x400FA028 /* SDRAM cached/copyback */
#define ACR2_DEFAULT #0x00000000 /* Not mapped */
#define ACR3_DEFAULT #0x400FA028 /* SDRAM cached/copyback */
#elif defined(CONFIG_M547X_8X)
#define ACR0_DEFAULT #0xF00FA048 /* System Regs */
#define ACR1_DEFAULT #0x000FA028 /* SDRAM cached/copy-back */
#define ACR2_DEFAULT #0x00000000 /* Not mapped */
#define ACR3_DEFAULT #0x000FA028 /* Instruction cached/copy-back */
#endif
#endif
/* ACR mapping for FPGA (maps 0) */
#define ACR0_FPGA #0x000FA048 /* ACR0 enable FPGA */
/* Several macros to make the writing of subroutines easier:
* - func_start marks the beginning of the routine which setups the frame
* register and saves the registers, it also defines another macro
* to automatically restore the registers again.
* - func_return marks the end of the routine and simply calls the prepared
* macro to restore registers and jump back to the caller.
* - func_define generates another macro to automatically put arguments
* onto the stack call the subroutine and cleanup the stack again.
*/
.macro load_symbol_address symbol,register
movel #\symbol,\register
.endm
.macro func_start name,saveregs,savesize,stack=0
L(\name):
linkw %a6,#-\stack
subal #(\savesize),%sp
moveml \saveregs,%sp@
.set stackstart,-\stack
.macro func_return_\name
moveml %sp@,\saveregs
addal #(\savesize),%sp
unlk %a6
rts
.endm
.endm
.macro func_return name
func_return_\name
.endm
.macro func_call name
jbsr L(\name)
.endm
.macro move_stack nr,arg1,arg2,arg3,arg4
.if \nr
move_stack "(\nr-1)",\arg2,\arg3,\arg4
movel \arg1,%sp@-
.endif
.endm
.macro func_define name,nr=0
.macro \name arg1,arg2,arg3,arg4
move_stack \nr,\arg1,\arg2,\arg3,\arg4
func_call \name
.if \nr
lea %sp@(\nr*4),%sp
.endif
.endm
.endm
func_define serial_putc,1
.macro putc ch
pea \ch
func_call serial_putc
addql #4,%sp
.endm
.macro dputc ch
#ifdef DEBUG
putc \ch
#endif
.endm
func_define putn,1
.macro dputn nr
#ifdef DEBUG
putn \nr
#endif
.endm
/*
mmu_map - creates a new TLB entry
virt_addr Must be on proper boundary
phys_addr Must be on proper boundary
itlb MMUOR_ITLB if instruction TLB or 0
asid address space ID
shared_global MMUTR_SG if shared between different ASIDs or 0
size_code MMUDR_SZ1M 1 MB
MMUDR_SZ4K 4 KB
MMUDR_SZ8K 8 KB
MMUDR_SZ16M 16 MB
cache_mode MMUDR_INC instruction non-cacheable
MMUDR_IC instruction cacheable
MMUDR_DWT data writethrough
MMUDR_DCB data copyback
MMUDR_DNCP data non-cacheable, precise
MMUDR_DNCIP data non-cacheable, imprecise
super_prot MMUDR_SP if user mode generates exception or 0
readable MMUDR_R if permits read access (data TLB) or 0
writable MMUDR_W if permits write access (data TLB) or 0
executable MMUDR_X if permits execute access (instruction TLB) or 0
locked MMUDR_LK prevents TLB entry from being replaced or 0
temp_data_reg a data register to use for temporary values
*/
.macro mmu_map virt_addr,phys_addr,itlb,asid,shared_global,size_code,cache_mode,super_prot,readable,writable,executable,locked,temp_data_reg
/* Set up search of TLB. */
movel #(\virt_addr+1), \temp_data_reg
movel \temp_data_reg, MMUAR
/* Search. */
movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg
movew \temp_data_reg, (MMUOR)
/* Set up tag value. */
movel #(\virt_addr + \asid + \shared_global + MMUTR_V), \temp_data_reg
movel \temp_data_reg, MMUTR
/* Set up data value. */
movel #(\phys_addr + \size_code + \cache_mode + \super_prot + \readable + \writable + \executable + \locked), \temp_data_reg
movel \temp_data_reg, MMUDR
/* Save it. */
movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg
movew \temp_data_reg, (MMUOR)
.endm /* mmu_map */
.macro mmu_unmap virt_addr,itlb,temp_data_reg
/* Set up search of TLB. */
movel #(\virt_addr+1), \temp_data_reg
movel \temp_data_reg, MMUAR
/* Search. */
movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg
movew \temp_data_reg, (MMUOR)
/* Test for hit. */
movel MMUSR,\temp_data_reg
btst #MMUSR_HITN,\temp_data_reg
beq 1f
/* Read the TLB. */
movel #(MMUOR_RW + MMUOR_ACC +\itlb), \temp_data_reg
movew \temp_data_reg, (MMUOR)
movel MMUSR,\temp_data_reg
/* Set up tag value. */
movel #0, \temp_data_reg
movel \temp_data_reg, MMUTR
/* Set up data value. */
movel #0, \temp_data_reg
movel \temp_data_reg, MMUDR
/* Save it. */
movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg
movew \temp_data_reg, (MMUOR)
1:
.endm /* mmu_unmap */
/* .text */
.section ".text.head","ax"
ENTRY(_stext)
/* Version numbers of the bootinfo interface -- if we later pass info
* from boot ROM we might want to put something real here.
*
* The area from _stext to _start will later be used as kernel pointer table
*/
bras 1f /* Jump over bootinfo version numbers */
.long BOOTINFOV_MAGIC
.long 0
1: jmp __start
.equ kernel_pg_dir,_stext
.equ .,_stext+0x1000
ENTRY(_start)
jra __start
__INIT
ENTRY(__start)
/* Save the location of u-boot info - cmd line, bd_info, etc. */
movel %a7,%a4 /* Don't use %a4 before cf_early_init */
addl #0x00000004,%a4 /* offset past top */
addl #(PAGE_OFFSET-CONFIG_SDRAM_BASE),%a4 /* high mem offset */
/* Setup initial stack pointer */
movel #CONFIG_SDRAM_BASE+0x1000,%sp
/* Setup usp */
subl %a0,%a0
movel %a0,%usp
#if defined(CONFIG_M5445X)
#if defined(CONFIG_SRAM)
movel #(CONFIG_SRAM_BASE+0x221), %d0
#else
movel #0x80000000, %d0
#endif
movec %d0, %rambar1
#elif defined(CONFIG_M547X_8X)
movel #MCF_MBAR, %d0
movec %d0, %mbar
move.l #(MCF_RAMBAR0 + 0x21), %d0
movec %d0, %rambar0
move.l #(MCF_RAMBAR1 + 0x21), %d0
movec %d0, %rambar1
#endif
movew #0x2700,%sr
/* reset cache */
movel #(CF_CACR_ICINVA + CF_CACR_DCINVA),%d0
movecl %d0,%cacr
movel #(MMU_BASE+1),%d0
movecl %d0,%mmubar
movel #MMUOR_CA,%a0 /* Clear tlb entries */
movew %a0,(MMUOR)
movel #(MMUOR_CA + MMUOR_ITLB),%a0 /* Use ITLB for searches */
movew %a0,(MMUOR)
movel #0,%a0 /* Clear Addr Space User ID */
movecl %a0,%asid
/* setup ACRs */
movel ACR0_DEFAULT, %d0 /* ACR0 (DATA) setup */
movec %d0, %acr0
nop
movel ACR1_DEFAULT, %d0 /* ACR1 (DATA) setup */
movec %d0, %acr1
nop
movel ACR2_DEFAULT, %d0 /* ACR2 (CODE) setup */
movec %d0, %acr2
nop
movel ACR3_DEFAULT, %d0 /* ACR3 (CODE) setup */
movec %d0, %acr3
nop
/* If you change the memory size to another value make a matching
change in paging_init(cf-mmu.c) to zones_size[]. */
#if CONFIG_SDRAM_BASE != PAGE_OFFSET
#if defined(CONFIG_M5445X)
/* Map 256MB as code */
mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
0, 0, MMUDR_X, MMUDR_LK, %d0
/* Map 256MB as data also */
mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
/* Map ATA registers -- sacrifice a data TLB due to the hw design */
mmu_map (0x90000000), (0x90000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
#elif defined(CONFIG_M547X_8X)
/* Map first 8 MB as code */
mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
MMUDR_LK, %d0
/* Map first 8 MB as data */
mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
#endif
/*
* Do unity mapping to enable the MMU. Map first chunk of memory
* in place as code/data. The TLBs will be deleted after the MMU is
* enabled and we are executing in high memory.
*/
#if defined(CONFIG_M5445X)
/* Map first 16 MB as code */
mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_INC, MMUDR_SP, 0, \
0, MMUDR_X, 0, %d0
/* Map first 16 MB as data too */
mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, 0, %d0
#elif defined(CONFIG_M547X_8X)
/* Map first 4 MB as code */
mmu_map (0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
MMUDR_X, 0, %d0
mmu_map (1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
MMUDR_X, 0, %d0
mmu_map (2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
MMUDR_X, 0, %d0
mmu_map (3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
MMUDR_X, 0, %d0
/* Map first 4 MB as data too */
mmu_map (0*1024*1024), (0*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, 0, %d0
mmu_map (1*1024*1024), (1*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, 0, %d0
mmu_map (2*1024*1024), (2*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, 0, %d0
mmu_map (3*1024*1024), (3*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, 0, %d0
#endif
#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
/* Turn on MMU */
movel #(MMUCR_EN),%a0
movel %a0,MMUCR
nop /* This synchs the pipeline after a write to MMUCR */
movel #__running_high,%a0 /* Get around PC-relative addressing. */
jmp %a0@
ENTRY(__running_high)
load_symbol_address _stext,%sp
movel L(memory_start),%a0
movel %a0,availmem
load_symbol_address L(phys_kernel_start),%a0
load_symbol_address _stext,%a1
subl #_stext,%a1
addl #PAGE_OFFSET,%a1
movel %a1,%a0@
/* zero bss */
lea _sbss,%a0
lea _ebss,%a1
clrl %d0
_loop_bss:
movel %d0,(%a0)+
cmpl %a0,%a1
bne _loop_bss
/* Unmap unity mappings */
#if CONFIG_SDRAM_BASE != PAGE_OFFSET
#if defined(CONFIG_M5445X)
mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
#elif defined(CONFIG_M547X_8X)
mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
mmu_unmap (PHYS_OFFSET+1*0x1000000), MMUOR_ITLB, %d0
mmu_unmap (PHYS_OFFSET+2*0x1000000), MMUOR_ITLB, %d0
mmu_unmap (PHYS_OFFSET+3*0x1000000), MMUOR_ITLB, %d0
mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
mmu_unmap (PHYS_OFFSET+1*0x1000000), 0, %d0
mmu_unmap (PHYS_OFFSET+2*0x1000000), 0, %d0
mmu_unmap (PHYS_OFFSET+3*0x1000000), 0, %d0
#endif
#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
/* create dma memory mirror TLB mapping */
#if defined(CONFIG_M5445X)
mmu_map CONFIG_DMA_BASE, \
CONFIG_SDRAM_BASE, 0, 0, \
MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
0, MMUDR_LK, %d0
#elif defined(CONFIG_M547X_8X)
mmu_map (CONFIG_DMA_BASE + 0*1024*1024), \
(CONFIG_SDRAM_BASE + 0*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (CONFIG_DMA_BASE + 1*1024*1024), \
(CONFIG_SDRAM_BASE + 1*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (CONFIG_DMA_BASE + 2*1024*1024), \
(CONFIG_SDRAM_BASE + 2*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (CONFIG_DMA_BASE + 3*1024*1024), \
(CONFIG_SDRAM_BASE + 3*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (CONFIG_DMA_BASE + 4*1024*1024), \
(CONFIG_SDRAM_BASE + 4*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (CONFIG_DMA_BASE + 5*1024*1024), \
(CONFIG_SDRAM_BASE + 5*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (CONFIG_DMA_BASE + 6*1024*1024), \
(CONFIG_SDRAM_BASE + 6*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
mmu_map (CONFIG_DMA_BASE + 7*1024*1024), \
(CONFIG_SDRAM_BASE + 7*1024*1024), 0, 0, \
MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
MMUDR_W, 0, MMUDR_LK, %d0
#endif
/* Setup initial stack pointer */
lea init_task,%a2
lea init_thread_union+THREAD_SIZE,%sp
subl %a6,%a6 /* clear a6 for gdb */
#ifdef CONFIG_MCF_USER_HALT
/* Setup debug control reg to allow halts from user space */
lea wdbg_uhe,%a0
wdebug (%a0)
#endif
movel %a4,uboot_info_stk /* save uboot info to variable */
jsr cf_early_init
jmp start_kernel
.section ".text.head","ax"
set_context:
func_start set_context,%d0,(1*4)
movel 12(%sp),%d0
movec %d0,%asid
func_return set_context
#ifdef CONFIG_M5445X
/*
* set_fpga(addr,val) on the M5445X
*
* Map in 0x00000000 -> 0x0fffffff and then do the write.
*/
set_fpga:
movew %sr,%d1
movew #0x2700,%sr
movel ACR0_FPGA, %d0
movec %d0, %acr0
nop
moveal 4(%sp),%a0
movel 8(%sp),%a0@
movel ACR0_DEFAULT, %d0
movec %d0, %acr0
nop
movew %d1,%sr
rts
#endif
.data
.align 4
availmem:
.long 0
L(phys_kernel_start):
.long PAGE_OFFSET
L(kernel_end):
.long 0
L(memory_start):
.long PAGE_OFFSET_RAW
#ifdef CONFIG_MCF_USER_HALT
/*
* Enable User Halt Enable in the debug control register.
*/
wdbg_uhe:
.word 0x2c80 /* DR0 */
.word 0x00b0 /* 31:16 */
.word 0x0400 /* 15:0 -- enable UHE */
.word 0x0000 /* unused */
#endif

467
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/ints.c
View File

@ -1,467 +0,0 @@
/*
* linux/arch/m68k/coldfire/ints.c -- General interrupt handling code
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Matt Waddel Matt.Waddel@freescale.com
* Kurt Mahan kmahan@freescale.com
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*
* Based on:
* linux/arch/m68k/kernel/ints.c &
* linux/arch/m68knommu/5307/ints.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/errno.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/irq_regs.h>
#include <asm/mcfsim.h>
/*
* IRQ Handler lists.
*/
static struct irq_node *irq_list[SYS_IRQS];
static struct irq_controller *irq_controller[SYS_IRQS];
static int irq_depth[SYS_IRQS];
/*
* IRQ Controller
*/
#if defined(CONFIG_M5445X)
void m5445x_irq_enable(unsigned int irq);
void m5445x_irq_disable(unsigned int irq);
static struct irq_controller m5445x_irq_controller = {
.name = "M5445X",
.lock = SPIN_LOCK_UNLOCKED,
.enable = m5445x_irq_enable,
.disable = m5445x_irq_disable,
};
#elif defined(CONFIG_M547X_8X)
void m547x_8x_irq_enable(unsigned int irq);
void m547x_8x_irq_disable(unsigned int irq);
static struct irq_controller m547x_8x_irq_controller = {
.name = "M547X_8X",
.lock = SPIN_LOCK_UNLOCKED,
.enable = m547x_8x_irq_enable,
.disable = m547x_8x_irq_disable,
};
#else
# error No IRQ controller defined
#endif
#define POOL_SIZE SYS_IRQS
static struct irq_node pool[POOL_SIZE];
static struct irq_node *get_irq_node(void);
/* The number of spurious interrupts */
unsigned int num_spurious;
asmlinkage void handle_badint(struct pt_regs *regs);
/*
* void init_IRQ(void)
*
* This function should be called during kernel startup to initialize
* the IRQ handling routines.
*/
void __init init_IRQ(void)
{
int i;
#if defined(CONFIG_M5445X)
for (i = 0; i < SYS_IRQS; i++)
irq_controller[i] = &m5445x_irq_controller;
#elif defined(CONFIG_M547X_8X)
for (i = 0; i < SYS_IRQS; i++)
irq_controller[i] = &m547x_8x_irq_controller;
#endif
}
/*
* process_int(unsigned long vec, struct pt_regs *fp)
*
* Process an interrupt. Called from entry.S.
*/
asmlinkage void process_int(unsigned long vec, struct pt_regs *fp)
{
struct pt_regs *old_regs;
struct irq_node *node;
old_regs = set_irq_regs(fp);
kstat_cpu(0).irqs[vec]++;
node = irq_list[vec];
if (!node)
handle_badint(fp);
else {
do {
node->handler(vec, node->dev_id);
node = node->next;
} while (node);
}
set_irq_regs(old_regs);
}
/*
* show_interrupts( struct seq_file *p, void *v)
*
* Called to show all the current interrupt information.
*/
int show_interrupts(struct seq_file *p, void *v)
{
struct irq_controller *contr;
struct irq_node *node;
int i = *(loff_t *) v;
if ((i < NR_IRQS) && (irq_list[i])) {
contr = irq_controller[i];
node = irq_list[i];
seq_printf(p, "%-8s %3u: %10u %s", contr->name, i,
kstat_cpu(0).irqs[i], node->devname);
while ((node = node->next))
seq_printf(p, ", %s", node->devname);
seq_printf(p, "\n");
}
return 0;
}
/*
* get_irq_node(void)
*
* Get an irq node from the pool.
*/
struct irq_node *get_irq_node(void)
{
struct irq_node *p = pool;
int i;
for (i = 0; i < POOL_SIZE; i++, p++) {
if (!p->handler) {
memset(p, 0, sizeof(struct irq_node));
return p;
}
}
printk(KERN_INFO "%s(%s:%d): No more irq nodes, I suggest you \
increase POOL_SIZE", __FUNCTION__, __FILE__, __LINE__);
return NULL;
}
void init_irq_proc(void)
{
/* Insert /proc/irq driver here */
}
int setup_irq(unsigned int irq, struct irq_node *node)
{
struct irq_controller *contr;
struct irq_node **prev;
unsigned long flags;
if (irq >= NR_IRQS || !irq_controller[irq]) {
printk("%s: Incorrect IRQ %d from %s\n",
__FUNCTION__, irq, node->devname);
return -ENXIO;
}
contr = irq_controller[irq];
spin_lock_irqsave(&contr->lock, flags);
prev = irq_list + irq;
if (*prev) {
/* Can't share interrupts unless both agree to */
if (!((*prev)->flags & node->flags & IRQF_SHARED)) {
spin_unlock_irqrestore(&contr->lock, flags);
printk(KERN_INFO "%s: -BUSY-Incorrect IRQ %d \n",
__FUNCTION__, irq);
return -EBUSY;
}
while (*prev)
prev = &(*prev)->next;
}
if (!irq_list[irq]) {
if (contr->startup)
contr->startup(irq);
else
contr->enable(irq);
}
node->next = NULL;
*prev = node;
spin_unlock_irqrestore(&contr->lock, flags);
return 0;
}
int request_irq(unsigned int irq,
irq_handler_t handler,
unsigned long flags, const char *devname, void *dev_id)
{
struct irq_node *node = get_irq_node();
int res;
if (!node) {
printk(KERN_INFO "%s:get_irq_node error %x\n",
__FUNCTION__,(unsigned int) node);
return -ENOMEM;
}
node->handler = handler;
node->flags = flags;
node->dev_id = dev_id;
node->devname = devname;
res = setup_irq(irq, node);
if (res)
node->handler = NULL;
return res;
}
EXPORT_SYMBOL(request_irq);
void free_irq(unsigned int irq, void *dev_id)
{
struct irq_controller *contr;
struct irq_node **p, *node;
unsigned long flags;
if (irq >= NR_IRQS || !irq_controller[irq]) {
printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __FUNCTION__, irq);
return;
}
contr = irq_controller[irq];
spin_lock_irqsave(&contr->lock, flags);
p = irq_list + irq;
while ((node = *p)) {
if (node->dev_id == dev_id)
break;
p = &node->next;
}
if (node) {
*p = node->next;
node->handler = NULL;
} else
printk(KERN_DEBUG "%s: Removing probably wrong IRQ %d\n",
__FUNCTION__, irq);
if (!irq_list[irq]) {
if (contr->shutdown)
contr->shutdown(irq);
else
contr->disable(irq);
}
spin_unlock_irqrestore(&contr->lock, flags);
}
EXPORT_SYMBOL(free_irq);
void enable_irq(unsigned int irq)
{
struct irq_controller *contr;
unsigned long flags;
if (irq >= NR_IRQS || !irq_controller[irq]) {
printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __FUNCTION__, irq);
return;
}
contr = irq_controller[irq];
spin_lock_irqsave(&contr->lock, flags);
if (irq_depth[irq]) {
if (!--irq_depth[irq]) {
if (contr->enable)
contr->enable(irq);
}
} else
WARN_ON(1);
spin_unlock_irqrestore(&contr->lock, flags);
}
EXPORT_SYMBOL(enable_irq);
void disable_irq(unsigned int irq)
{
struct irq_controller *contr;
unsigned long flags;
if (irq >= NR_IRQS || !irq_controller[irq]) {
printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __FUNCTION__, irq);
return;
}
contr = irq_controller[irq];
spin_lock_irqsave(&contr->lock, flags);
if (!irq_depth[irq]++) {
if (contr->disable)
contr->disable(irq);
}
spin_unlock_irqrestore(&contr->lock, flags);
}
EXPORT_SYMBOL(disable_irq);
void disable_irq_nosync(unsigned int irq) __attribute__((alias("disable_irq")));
EXPORT_SYMBOL(disable_irq_nosync);
unsigned long probe_irq_on(void)
{
return 0;
}
EXPORT_SYMBOL(probe_irq_on);
int probe_irq_off(unsigned long irqs)
{
return 0;
}
EXPORT_SYMBOL(probe_irq_off);
asmlinkage void handle_badint(struct pt_regs *regs)
{
kstat_cpu(0).irqs[0]++;
num_spurious++;
printk(KERN_DEBUG "unexpected interrupt from %u\n", regs->vector);
}
EXPORT_SYMBOL(handle_badint);
unsigned int irq_canonicalize(unsigned int irq)
{
#ifdef CONFIG_Q40
if (MACH_IS_Q40 && irq == 11)
irq = 10;
#endif
return irq;
}
EXPORT_SYMBOL(irq_canonicalize);
#ifdef CONFIG_M5445X
/*
* M5445X Implementation
*/
void m5445x_irq_enable(unsigned int irq)
{
/* enable the interrupt hardware */
if (irq < 64)
return;
/* adjust past non-hardware ints */
irq -= 64;
/* check for eport */
if ((irq > 0) && (irq < 8)) {
/* enable eport */
MCF_EPORT_EPPAR &= ~(3 << (irq*2)); /* level */
MCF_EPORT_EPDDR &= ~(1 << irq); /* input */
MCF_EPORT_EPIER |= 1 << irq; /* irq enabled */
}
if (irq < 64) {
/* controller 0 */
MCF_INTC0_ICR(irq) = 0x02;
MCF_INTC0_CIMR = irq;
} else {
/* controller 1 */
irq -= 64;
MCF_INTC1_ICR(irq) = 0x02;
MCF_INTC1_CIMR = irq;
}
}
void m5445x_irq_disable(unsigned int irq)
{
/* disable the interrupt hardware */
if (irq < 64)
return;
/* adjust past non-hardware ints */
irq -= 64;
/* check for eport */
if ((irq > 0) && (irq < 8)) {
/* disable eport */
MCF_EPORT_EPIER &= ~(1 << irq);
}
if (irq < 64) {
/* controller 0 */
MCF_INTC0_ICR(irq) = 0x00;
MCF_INTC0_SIMR = irq;
} else {
/* controller 1 */
irq -= 64;
MCF_INTC1_ICR(irq) = 0x00;
MCF_INTC1_SIMR = irq;
}
}
#elif defined(CONFIG_M547X_8X)
/*
* M547X_8X Implementation
*/
void m547x_8x_irq_enable(unsigned int irq)
{
/* enable the interrupt hardware */
if (irq < 64)
return;
/* adjust past non-hardware ints */
irq -= 64;
/* check for eport */
if ((irq > 0) && (irq < 8)) {
/* enable eport */
MCF_EPPAR &= ~(3 << (irq*2));
/* level */
MCF_EPDDR &= ~(1 << irq);
/* input */
MCF_EPIER |= 1 << irq;
/* irq enabled */
}
if (irq < 32) {
/* *grumble* don't set low bit of IMRL */
MCF_IMRL &= (~(1 << irq) & 0xfffffffe);
} else {
MCF_IMRH &= ~(1 << (irq - 32));
}
}
void m547x_8x_irq_disable(unsigned int irq)
{
/* disable the interrupt hardware */
if (irq < 64)
return;
/* adjust past non-hardware ints */
irq -= 64;
/* check for eport */
if ((irq > 0) && (irq < 8)) {
/* disable eport */
MCF_EPIER &= ~(1 << irq);
}
if (irq < 32)
MCF_IMRL |= (1 << irq);
else
MCF_IMRH |= (1 << (irq - 32));
}
#endif

67
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/muldi3.S
View File

@ -1,67 +0,0 @@
/*
* Coldfire muldi3 assembly verion
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*/
#include <linux/linkage.h>
.globl __muldi3
ENTRY(__muldi3)
linkw %fp,#0
lea %sp@(-32),%sp
moveml %d2-%d7/%a2-%a3,%sp@
moveal %fp@(8), %a2
moveal %fp@(12), %a3
moveal %fp@(16), %a0
moveal %fp@(20),%a1
movel %a3,%d2
andil #65535,%d2
movel %a3,%d3
clrw %d3
swap %d3
movel %a1,%d0
andil #65535,%d0
movel %a1,%d1
clrw %d1
swap %d1
movel %d2,%d7
mulsl %d0,%d7
movel %d2,%d4
mulsl %d1,%d4
movel %d3,%d2
mulsl %d0,%d2
mulsl %d1,%d3
movel %d7,%d0
clrw %d0
swap %d0
addl %d0,%d4
addl %d2,%d4
cmpl %d4,%d2
blss 1f
addil #65536,%d3
1:
movel %d4,%d0
clrw %d0
swap %d0
movel %d3,%d5
addl %d0,%d5
movew %d4,%d6
swap %d6
movew %d7,%d6
movel %d5,%d0
movel %d6,%d1
movel %a3,%d2
movel %a0,%d3
mulsl %d3,%d2
movel %a2,%d3
movel %a1,%d4
mulsl %d4,%d3
addl %d3,%d2
movel %d2,%d0
addl %d5,%d0
moveml %sp@, %d2-%d7/%a2-%a3
lea %sp@(32),%sp
unlk %fp
rts

991
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/signal.c
View File

@ -1,991 +0,0 @@
/*
* linux/arch/m68k/kernel/signal.c
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Matt Waddel Matt.Waddel@freescale.com
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* Derived from m68k/kernel/signal.c and the original authors are credited
* there.
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/syscalls.h>
#include <linux/errno.h>
#include <linux/wait.h>
#include <linux/ptrace.h>
#include <linux/unistd.h>
#include <linux/stddef.h>
#include <linux/highuid.h>
#include <linux/personality.h>
#include <linux/tty.h>
#include <linux/binfmts.h>
#include <asm/setup.h>
#include <asm/cf_uaccess.h>
#include <asm/cf_pgtable.h>
#include <asm/traps.h>
#include <asm/ucontext.h>
#include <asm/cacheflush.h>
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs);
const int frame_extra_sizes[16] = {
[1] = -1,
[2] = sizeof(((struct frame *)0)->un.fmt2),
[3] = sizeof(((struct frame *)0)->un.fmt3),
[4] = 0,
[5] = -1,
[6] = -1,
[7] = sizeof(((struct frame *)0)->un.fmt7),
[8] = -1,
[9] = sizeof(((struct frame *)0)->un.fmt9),
[10] = sizeof(((struct frame *)0)->un.fmta),
[11] = sizeof(((struct frame *)0)->un.fmtb),
[12] = -1,
[13] = -1,
[14] = -1,
[15] = -1,
};
/*
* Atomically swap in the new signal mask, and wait for a signal.
*/
asmlinkage int do_sigsuspend(struct pt_regs *regs)
{
old_sigset_t mask = regs->d3;
sigset_t saveset;
mask &= _BLOCKABLE;
spin_lock_irq(&current->sighand->siglock);
saveset = current->blocked;
siginitset(&current->blocked, mask);
recalc_sigpending();
spin_unlock_irq(&current->sighand->siglock);
regs->d0 = -EINTR;
while (1) {
current->state = TASK_INTERRUPTIBLE;
schedule();
if (do_signal(&saveset, regs))
return -EINTR;
}
}
asmlinkage int
do_rt_sigsuspend(struct pt_regs *regs)
{
sigset_t __user *unewset = (sigset_t __user *)regs->d1;
size_t sigsetsize = (size_t)regs->d2;
sigset_t saveset, newset;
/* XXX: Don't preclude handling different sized sigset_t's. */
if (sigsetsize != sizeof(sigset_t))
return -EINVAL;
if (copy_from_user(&newset, unewset, sizeof(newset)))
return -EFAULT;
sigdelsetmask(&newset, ~_BLOCKABLE);
spin_lock_irq(&current->sighand->siglock);
saveset = current->blocked;
current->blocked = newset;
recalc_sigpending();
spin_unlock_irq(&current->sighand->siglock);
regs->d0 = -EINTR;
while (1) {
current->state = TASK_INTERRUPTIBLE;
schedule();
if (do_signal(&saveset, regs))
return -EINTR;
}
}
asmlinkage int
sys_sigaction(int sig, const struct old_sigaction __user *act,
struct old_sigaction __user *oact)
{
struct k_sigaction new_ka, old_ka;
int ret;
if (act) {
old_sigset_t mask;
if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
__get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
__get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
return -EFAULT;
__get_user(new_ka.sa.sa_flags, &act->sa_flags);
__get_user(mask, &act->sa_mask);
siginitset(&new_ka.sa.sa_mask, mask);
}
ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
if (!ret && oact) {
if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
__put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
__put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
return -EFAULT;
__put_user(old_ka.sa.sa_flags, &oact->sa_flags);
__put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
}
return ret;
}
asmlinkage int
sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
{
return do_sigaltstack(uss, uoss, rdusp());
}
/*
* Do a signal return; undo the signal stack.
*
* Keep the return code on the stack quadword aligned!
* That makes the cache flush below easier.
*/
struct sigframe
{
char __user *pretcode;
int sig;
int code;
struct sigcontext __user *psc;
char retcode[8];
unsigned long extramask[_NSIG_WORDS-1];
struct sigcontext sc;
};
struct rt_sigframe
{
char __user *pretcode;
int sig;
struct siginfo __user *pinfo;
void __user *puc;
char retcode[8];
struct siginfo info;
struct ucontext uc;
};
#define FPCONTEXT_SIZE 216
#define uc_fpstate uc_filler[0]
#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4]
#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1]
#ifdef CONFIG_FPU
static unsigned char fpu_version; /* version num of fpu, set by setup_frame */
static inline int restore_fpu_state(struct sigcontext *sc)
{
int err = 1;
if (FPU_IS_EMU) {
/* restore registers */
memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
memcpy(current->thread.fp, sc->sc_fpregs, 24);
return 0;
}
if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
/* Verify the frame format. */
if (!CPU_IS_060 && (sc->sc_fpstate[0] != fpu_version))
goto out;
if (CPU_IS_020_OR_030) {
if (m68k_fputype & FPU_68881 &&
!(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4))
goto out;
if (m68k_fputype & FPU_68882 &&
!(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4))
goto out;
} else if (CPU_IS_040) {
if (!(sc->sc_fpstate[1] == 0x00 ||
sc->sc_fpstate[1] == 0x28 ||
sc->sc_fpstate[1] == 0x60))
goto out;
} else if (CPU_IS_060) {
if (!(sc->sc_fpstate[3] == 0x00 ||
sc->sc_fpstate[3] == 0x60 ||
sc->sc_fpstate[3] == 0xe0))
goto out;
} else if (CPU_IS_CFV4E) {
pr_debug("restore v4e fpu state at %s\n", __func__);
} else
goto out;
#ifdef CONFIG_CFV4E
__asm__ volatile ("fmovem %0,%/fp0-%/fp1\n\t"
QCHIP_RESTORE_DIRECTIVE
: /* no outputs */
: "m" (sc->sc_fpregs[0][0])
: "memory");
__asm__ volatile ("fmovel %0,%/fpcr"
: : "m" (sc->sc_fpcntl[0])
: "memory" );
__asm__ volatile ("fmovel %0,%/fpsr"
: : "m" (sc->sc_fpcntl[1])
: "memory" );
__asm__ volatile ("fmovel %0,%/fpiar"
: : "m" (sc->sc_fpcntl[2])
: "memory" );
#endif
}
#ifdef CONFIG_CFV4E
__asm__ volatile ("frestore %0\n\t"
QCHIP_RESTORE_DIRECTIVE : : "m" (*sc->sc_fpstate));
#endif
err = 0;
out:
return err;
}
static inline int rt_restore_fpu_state(struct ucontext __user *uc)
{
unsigned char fpstate[FPCONTEXT_SIZE];
int context_size = CPU_IS_060 ? 8 : 0;
fpregset_t fpregs;
int err = 1;
if (FPU_IS_EMU) {
/* restore fpu control register */
if (__copy_from_user(current->thread.fpcntl,
uc->uc_mcontext.fpregs.f_fpcntl, 12))
goto out;
/* restore all other fpu register */
if (__copy_from_user(current->thread.fp,
uc->uc_mcontext.fpregs.f_fpregs, 96))
goto out;
return 0;
}
if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
goto out;
if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
if (!CPU_IS_060)
context_size = fpstate[1];
/* Verify the frame format. */
if (!CPU_IS_060 && (fpstate[0] != fpu_version))
goto out;
if (CPU_IS_020_OR_030) {
if (m68k_fputype & FPU_68881 &&
!(context_size == 0x18 || context_size == 0xb4))
goto out;
if (m68k_fputype & FPU_68882 &&
!(context_size == 0x38 || context_size == 0xd4))
goto out;
} else if (CPU_IS_040) {
if (!(context_size == 0x00 ||
context_size == 0x28 ||
context_size == 0x60))
goto out;
} else if (CPU_IS_060) {
if (!(fpstate[3] == 0x00 ||
fpstate[3] == 0x60 ||
fpstate[3] == 0xe0))
goto out;
} else if (CPU_IS_CFV4E) {
pr_debug("restore coldfire rt v4e fpu"
" state at %s\n", __func__);
} else
goto out;
if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
sizeof(fpregs)))
goto out;
#ifdef CONFIG_CFV4E
__asm__ volatile ("fmovem %0,%/fp0-%/fp7\n\t"
QCHIP_RESTORE_DIRECTIVE
: /* no outputs */
: "m" (fpregs.f_fpregs[0][0])
: "memory");
__asm__ volatile ("fmovel %0,%/fpcr"
: : "m" (fpregs.f_fpcntl[0])
: "memory" );
__asm__ volatile ("fmovel %0,%/fpsr"
: : "m" (fpregs.f_fpcntl[1])
: "memory" );
__asm__ volatile ("fmovel %0,%/fpiar"
: : "m" (fpregs.f_fpcntl[2])
: "memory" );
#endif
}
if (context_size &&
__copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
context_size))
goto out;
#ifdef CONFIG_CFV4E
__asm__ volatile ("frestore %0\n\t"
QCHIP_RESTORE_DIRECTIVE : : "m" (*fpstate));
#endif
err = 0;
out:
return err;
}
#endif
static inline int
restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc,
void __user *fp, int *pd0)
{
int fsize, formatvec;
struct sigcontext context;
int err = 0;
/* get previous context */
if (copy_from_user(&context, usc, sizeof(context)))
goto badframe;
/* restore passed registers */
regs->d1 = context.sc_d1;
regs->a0 = context.sc_a0;
regs->a1 = context.sc_a1;
regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
regs->pc = context.sc_pc;
regs->orig_d0 = -1; /* disable syscall checks */
wrusp(context.sc_usp);
formatvec = context.sc_formatvec;
regs->format = formatvec >> 12;
regs->vector = formatvec & 0xfff;
#ifdef CONFIG_FPU
err = restore_fpu_state(&context);
#endif
fsize = frame_extra_sizes[regs->format];
if (fsize < 0) {
/*
* user process trying to return with weird frame format
*/
#ifdef DEBUG
printk(KERN_DEBUG "user process returning with weird \
frame format\n");
#endif
goto badframe;
}
/* OK. Make room on the supervisor stack for the extra junk,
* if necessary.
*/
{
struct switch_stack *sw = (struct switch_stack *)regs - 1;
regs->d0 = context.sc_d0;
#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
__asm__ __volatile__
(" movel %0,%/sp\n\t"
" bra ret_from_signal\n"
"4:\n"
".section __ex_table,\"a\"\n"
" .align 4\n"
" .long 2b,4b\n"
".previous"
: /* no outputs, it doesn't ever return */
: "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
"n" (frame_offset), "a" (fp)
: "a0");
#undef frame_offset
/*
* If we ever get here an exception occurred while
* building the above stack-frame.
*/
goto badframe;
}
*pd0 = context.sc_d0;
return err;
badframe:
return 1;
}
static inline int
rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
struct ucontext __user *uc, int *pd0)
{
int fsize, temp;
greg_t __user *gregs = uc->uc_mcontext.gregs;
unsigned long usp;
int err;
err = __get_user(temp, &uc->uc_mcontext.version);
if (temp != MCONTEXT_VERSION)
goto badframe;
/* restore passed registers */
err |= __get_user(regs->d0, &gregs[0]);
err |= __get_user(regs->d1, &gregs[1]);
err |= __get_user(regs->d2, &gregs[2]);
err |= __get_user(regs->d3, &gregs[3]);
err |= __get_user(regs->d4, &gregs[4]);
err |= __get_user(regs->d5, &gregs[5]);
err |= __get_user(sw->d6, &gregs[6]);
err |= __get_user(sw->d7, &gregs[7]);
err |= __get_user(regs->a0, &gregs[8]);
err |= __get_user(regs->a1, &gregs[9]);
err |= __get_user(regs->a2, &gregs[10]);
err |= __get_user(sw->a3, &gregs[11]);
err |= __get_user(sw->a4, &gregs[12]);
err |= __get_user(sw->a5, &gregs[13]);
err |= __get_user(sw->a6, &gregs[14]);
err |= __get_user(usp, &gregs[15]);
wrusp(usp);
err |= __get_user(regs->pc, &gregs[16]);
err |= __get_user(temp, &gregs[17]);
regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
regs->orig_d0 = -1; /* disable syscall checks */
err |= __get_user(temp, &uc->uc_formatvec);
regs->format = temp >> 12;
regs->vector = temp & 0xfff;
#ifdef CONFIG_FPU
err |= rt_restore_fpu_state(uc);
#endif
if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
goto badframe;
fsize = frame_extra_sizes[regs->format];
if (fsize < 0) {
/*
* user process trying to return with weird frame format
*/
#ifdef DEBUG
printk(KERN_DEBUG "user process returning with weird \
frame format\n");
#endif
goto badframe;
}
/* OK. Make room on the supervisor stack for the extra junk,
* if necessary.
*/
{
#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
__asm__ __volatile__
(" movel %0,%/sp\n\t"
" bra ret_from_signal\n"
"4:\n"
".section __ex_table,\"a\"\n"
" .align 4\n"
" .long 2b,4b\n"
".previous"
: /* no outputs, it doesn't ever return */
: "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
"n" (frame_offset), "a" (&uc->uc_extra)
: "a0");
#undef frame_offset
/*
* If we ever get here an exception occurred while
* building the above stack-frame.
*/
goto badframe;
}
*pd0 = regs->d0;
return err;
badframe:
return 1;
}
asmlinkage int do_sigreturn(unsigned long __unused)
{
struct switch_stack *sw = (struct switch_stack *) &__unused;
struct pt_regs *regs = (struct pt_regs *) (sw + 1);
unsigned long usp = rdusp();
struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
sigset_t set;
int d0;
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
(_NSIG_WORDS > 1 &&
__copy_from_user(&set.sig[1], &frame->extramask,
sizeof(frame->extramask))))
goto badframe;
sigdelsetmask(&set, ~_BLOCKABLE);
spin_lock_irq(&current->sighand->siglock);
current->blocked = set;
recalc_sigpending();
spin_unlock_irq(&current->sighand->siglock);
if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0))
goto badframe;
return d0;
badframe:
force_sig(SIGSEGV, current);
return 0;
}
asmlinkage int do_rt_sigreturn(unsigned long __unused)
{
struct switch_stack *sw = (struct switch_stack *) &__unused;
struct pt_regs *regs = (struct pt_regs *) (sw + 1);
unsigned long usp = rdusp();
struct rt_sigframe __user *frame =
(struct rt_sigframe __user *)(usp - 4);
sigset_t set;
int d0;
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
goto badframe;
sigdelsetmask(&set, ~_BLOCKABLE);
spin_lock_irq(&current->sighand->siglock);
current->blocked = set;
recalc_sigpending();
spin_unlock_irq(&current->sighand->siglock);
if (rt_restore_ucontext(regs, sw, &frame->uc, &d0))
goto badframe;
return d0;
badframe:
force_sig(SIGSEGV, current);
return 0;
}
#ifdef CONFIG_FPU
/*
* Set up a signal frame.
*/
static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
{
if (FPU_IS_EMU) {
/* save registers */
memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
memcpy(sc->sc_fpregs, current->thread.fp, 24);
return;
}
#ifdef CONFIG_CFV4E
__asm__ volatile ("fsave %0\n\t"
QCHIP_RESTORE_DIRECTIVE
: : "m" (*sc->sc_fpstate) : "memory");
#endif
if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
fpu_version = sc->sc_fpstate[0];
if (CPU_IS_020_OR_030 &&
regs->vector >= (VEC_FPBRUC * 4) &&
regs->vector <= (VEC_FPNAN * 4)) {
/* Clear pending exception in 68882 idle frame */
if (*(unsigned short *) sc->sc_fpstate == 0x1f38)
sc->sc_fpstate[0x38] |= 1 << 3;
}
#ifdef CONFIG_CFV4E
__asm__ volatile ("fmovemd %/fp0-%/fp1,%0"
: : "m" (sc->sc_fpregs[0][0])
: "memory");
__asm__ volatile ("fmovel %/fpcr,%0"
: : "m" (sc->sc_fpcntl[0])
: "memory");
__asm__ volatile ("fmovel %/fpsr,%0"
: : "m" (sc->sc_fpcntl[1])
: "memory");
__asm__ volatile ("fmovel %/fpiar,%0"
: : "m" (sc->sc_fpcntl[2])
: "memory");
#endif
}
}
static inline int rt_save_fpu_state(struct ucontext __user *uc,
struct pt_regs *regs)
{
unsigned char fpstate[FPCONTEXT_SIZE];
int context_size = CPU_IS_060 ? 8 : 0;
int err = 0;
if (FPU_IS_EMU) {
/* save fpu control register */
err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl,
current->thread.fpcntl, 12);
/* save all other fpu register */
err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
current->thread.fp, 96);
return err;
}
#ifdef CONFIG_CFV4E
__asm__ volatile ("fsave %0\n\t"
QCHIP_RESTORE_DIRECTIVE
: : "m" (*fpstate) : "memory");
#endif
err |= __put_user(*(long *)fpstate, (long *)&uc->uc_fpstate);
if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
fpregset_t fpregs;
if (!CPU_IS_060)
context_size = fpstate[1];
fpu_version = fpstate[0];
#ifdef CONFIG_CFV4E
__asm__ volatile ("fmovemd %/fp0-%/fp7,%0"
: : "m" (fpregs.f_fpregs[0][0])
: "memory");
__asm__ volatile ("fmovel %/fpcr,%0"
: : "m" (fpregs.f_fpcntl[0])
: "memory");
__asm__ volatile ("fmovel %/fpsr,%0"
: : "m" (fpregs.f_fpcntl[1])
: "memory");
__asm__ volatile ("fmovel %/fpiar,%0"
: : "m" (fpregs.f_fpcntl[2])
: "memory");
#endif
err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
sizeof(fpregs));
}
if (context_size)
err |= copy_to_user((long *)&uc->uc_fpstate + 1, fpstate + 4,
context_size);
return err;
return err;
}
#endif
static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
unsigned long mask)
{
sc->sc_mask = mask;
sc->sc_usp = rdusp();
sc->sc_d0 = regs->d0;
sc->sc_d1 = regs->d1;
sc->sc_a0 = regs->a0;
sc->sc_a1 = regs->a1;
sc->sc_sr = regs->sr;
sc->sc_pc = regs->pc;
sc->sc_formatvec = regs->format << 12 | regs->vector;
#ifdef CONFIG_FPU
save_fpu_state(sc, regs);
#endif
}
static inline int rt_setup_ucontext(struct ucontext __user *uc,
struct pt_regs *regs)
{
struct switch_stack *sw = (struct switch_stack *)regs - 1;
greg_t __user *gregs = uc->uc_mcontext.gregs;
int err = 0;
err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
err |= __put_user(regs->d0, &gregs[0]);
err |= __put_user(regs->d1, &gregs[1]);
err |= __put_user(regs->d2, &gregs[2]);
err |= __put_user(regs->d3, &gregs[3]);
err |= __put_user(regs->d4, &gregs[4]);
err |= __put_user(regs->d5, &gregs[5]);
err |= __put_user(sw->d6, &gregs[6]);
err |= __put_user(sw->d7, &gregs[7]);
err |= __put_user(regs->a0, &gregs[8]);
err |= __put_user(regs->a1, &gregs[9]);
err |= __put_user(regs->a2, &gregs[10]);
err |= __put_user(sw->a3, &gregs[11]);
err |= __put_user(sw->a4, &gregs[12]);
err |= __put_user(sw->a5, &gregs[13]);
err |= __put_user(sw->a6, &gregs[14]);
err |= __put_user(rdusp(), &gregs[15]);
err |= __put_user(regs->pc, &gregs[16]);
err |= __put_user(regs->sr, &gregs[17]);
err |= __put_user((regs->format << 12) | regs->vector,
&uc->uc_formatvec);
#ifdef CONFIG_FPU
err |= rt_save_fpu_state(uc, regs);
#endif
return err;
}
static inline void push_cache(unsigned long vaddr)
{
#ifdef CONFIG_M5445X
pgd_t *pdir;
pmd_t *pmdp;
pte_t *ptep;
unsigned long paddr;
pdir = pgd_offset(current->mm, vaddr);
pmdp = pmd_offset(pdir, vaddr);
ptep = pte_offset_map(pmdp, vaddr);
paddr = ((pte_val(*ptep) & PAGE_MASK) | (vaddr & ~PAGE_MASK));
cf_icache_flush_range(paddr, paddr + 8);
#elif CONFIG_M547X_8X
flush_icache_range(vaddr, vaddr + 8);
#endif
}
static inline void __user *
get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
{
unsigned long usp;
/* Default to using normal stack. */
usp = rdusp();
/* This is the X/Open sanctioned signal stack switching. */
if (ka->sa.sa_flags & SA_ONSTACK) {
if (!sas_ss_flags(usp))
usp = current->sas_ss_sp + current->sas_ss_size;
}
return (void __user *)((usp - frame_size) & -8UL);
}
static void setup_frame(int sig, struct k_sigaction *ka,
sigset_t *set, struct pt_regs *regs)
{
struct sigframe __user *frame;
int fsize = frame_extra_sizes[regs->format];
struct sigcontext context;
int err = 0;
if (fsize < 0) {
#ifdef DEBUG
printk(KERN_DEBUG "setup_frame: Unknown frame format %#x\n",
regs->format);
#endif
goto give_sigsegv;
}
frame = get_sigframe(ka, regs, sizeof(*frame));
err |= __put_user((current_thread_info()->exec_domain
&& current_thread_info()->exec_domain->signal_invmap
&& sig < 32
? current_thread_info()->exec_domain->signal_invmap[sig]
: sig),
&frame->sig);
err |= __put_user(regs->vector, &frame->code);
err |= __put_user(&frame->sc, &frame->psc);
if (_NSIG_WORDS > 1)
err |= copy_to_user(frame->extramask, &set->sig[1],
sizeof(frame->extramask));
setup_sigcontext(&context, regs, set->sig[0]);
err |= copy_to_user(&frame->sc, &context, sizeof(context));
/* Set up to return from userspace. */
err |= __put_user(frame->retcode, &frame->pretcode);
/* moveq #,d0; trap #0 */
err |= __put_user(0x70004e40 + (__NR_sigreturn << 16),
(long __user *)(frame->retcode));
if (err)
goto give_sigsegv;
push_cache((unsigned long) &frame->retcode);
/* Set up registers for signal handler */
wrusp((unsigned long) frame);
regs->pc = (unsigned long) ka->sa.sa_handler;
adjust_stack:
/* Prepare to skip over the extra stuff in the exception frame. */
if (regs->stkadj) {
struct pt_regs *tregs =
(struct pt_regs *)((ulong)regs + regs->stkadj);
#ifdef DEBUG
printk(KERN_DEBUG "Performing stackadjust=%04x\n",
regs->stkadj);
#endif
/* This must be copied with decreasing addresses to
handle overlaps. */
tregs->vector = 0;
tregs->format = 0;
tregs->pc = regs->pc;
tregs->sr = regs->sr;
}
return;
give_sigsegv:
force_sigsegv(sig, current);
goto adjust_stack;
}
static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
sigset_t *set, struct pt_regs *regs)
{
struct rt_sigframe __user *frame;
int fsize = frame_extra_sizes[regs->format];
int err = 0;
if (fsize < 0) {
#ifdef DEBUG
printk(KERN_DEBUG "setup_frame: Unknown frame format %#x\n",
regs->format);
#endif
goto give_sigsegv;
}
frame = get_sigframe(ka, regs, sizeof(*frame));
if (fsize) {
err |= copy_to_user(&frame->uc.uc_extra, regs + 1, fsize);
regs->stkadj = fsize;
}
err |= __put_user((current_thread_info()->exec_domain
&& current_thread_info()->exec_domain->signal_invmap
&& sig < 32
? current_thread_info()->exec_domain->signal_invmap[sig]
: sig),
&frame->sig);
err |= __put_user(&frame->info, &frame->pinfo);
err |= __put_user(&frame->uc, &frame->puc);
err |= copy_siginfo_to_user(&frame->info, info);
/* Create the ucontext. */
err |= __put_user(0, &frame->uc.uc_flags);
err |= __put_user(NULL, &frame->uc.uc_link);
err |= __put_user((void __user *)current->sas_ss_sp,
&frame->uc.uc_stack.ss_sp);
err |= __put_user(sas_ss_flags(rdusp()),
&frame->uc.uc_stack.ss_flags);
err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
err |= rt_setup_ucontext(&frame->uc, regs);
err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
/* Set up to return from userspace. */
err |= __put_user(frame->retcode, &frame->pretcode);
/* movel #__NR_rt_sigreturn(0xAD),d0; trap #0 */
err |= __put_user(0x203c0000, (long *)(frame->retcode + 0));
err |= __put_user(0x00ad4e40, (long *)(frame->retcode + 4));
if (err)
goto give_sigsegv;
push_cache((unsigned long) &frame->retcode);
/* Set up registers for signal handler */
wrusp((unsigned long) frame);
regs->pc = (unsigned long) ka->sa.sa_handler;
adjust_stack:
/* Prepare to skip over the extra stuff in the exception frame. */
if (regs->stkadj) {
struct pt_regs *tregs =
(struct pt_regs *)((ulong)regs + regs->stkadj);
#ifdef DEBUG
printk(KERN_DEBUG "Performing stackadjust=%04x\n",
regs->stkadj);
#endif
/* This must be copied with decreasing addresses to
handle overlaps. */
tregs->vector = 0;
tregs->format = 0;
tregs->pc = regs->pc;
tregs->sr = regs->sr;
}
return;
give_sigsegv:
force_sigsegv(sig, current);
goto adjust_stack;
}
static inline void
handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
{
switch (regs->d0) {
case -ERESTARTNOHAND:
if (!has_handler)
goto do_restart;
regs->d0 = -EINTR;
break;
case -ERESTARTSYS:
if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
regs->d0 = -EINTR;
break;
}
/* fallthrough */
case -ERESTARTNOINTR:
do_restart:
regs->d0 = regs->orig_d0;
regs->pc -= 2;
break;
}
}
/*
* OK, we're invoking a handler
*/
static void
handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
sigset_t *oldset, struct pt_regs *regs)
{
/* are we from a system call? */
if (regs->orig_d0 >= 0)
/* If so, check system call restarting.. */
handle_restart(regs, ka, 1);
/* set up the stack frame */
if (ka->sa.sa_flags & SA_SIGINFO)
setup_rt_frame(sig, ka, info, oldset, regs);
else
setup_frame(sig, ka, oldset, regs);
if (ka->sa.sa_flags & SA_ONESHOT)
ka->sa.sa_handler = SIG_DFL;
spin_lock_irq(&current->sighand->siglock);
sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
if (!(ka->sa.sa_flags & SA_NODEFER))
sigaddset(&current->blocked, sig);
recalc_sigpending();
spin_unlock_irq(&current->sighand->siglock);
}
/*
* Note that 'init' is a special process: it doesn't get signals it doesn't
* want to handle. Thus you cannot kill init even with a SIGKILL even by
* mistake.
*/
asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs)
{
siginfo_t info;
struct k_sigaction ka;
int signr;
current->thread.esp0 = (unsigned long) regs;
if (!oldset)
oldset = &current->blocked;
signr = get_signal_to_deliver(&info, &ka, regs, NULL);
if (signr > 0) {
/* Whee! Actually deliver the signal. */
handle_signal(signr, &ka, &info, oldset, regs);
return 1;
}
/* Did we come from a system call? */
if (regs->orig_d0 >= 0)
/* Restart the system call - no handlers present */
handle_restart(regs, NULL, 0);
return 0;
}

318
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/time.c
View File

@ -1,318 +0,0 @@
/*
* linux/arch/m68k/coldfire/time.c
*
* This file contains the coldfire specific time handling pieces.
*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan <kmahan@freescale.com>
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*
* based on linux/arch/m68k/kernel/time.c
*/
#include <linux/clk.h>
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/sysdev.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/rtc.h>
#include <asm/machdep.h>
#include <linux/io.h>
#include <asm/irq_regs.h>
#include <linux/profile.h>
#include <asm/mcfsim.h>
#ifdef CONFIG_GENERIC_CLOCKEVENTS
/*extern unsigned long long sys_dtim0_read(void);
extern void sys_dtim_init(void);*/
extern unsigned long long sys_dtim2_read(void);
extern void sys_dtim2_init(void);
static int cfv4_set_next_event(unsigned long evt,
struct clock_event_device *dev);
static void cfv4_set_mode(enum clock_event_mode mode,
struct clock_event_device *dev);
#if defined(CONFIG_M5445X)
#define FREQ (MCF_BUSCLK / 16)
#else
#define FREQ (MCF_BUSCLK)
#endif
/*
* realtime clock dummy code
*/
static unsigned long null_rtc_get_time(void)
{
return mktime(2008, 1, 1, 0, 0, 0);
}
static int null_rtc_set_time(unsigned long sec)
{
return 0;
}
static unsigned long (*cf_rtc_get_time)(void) = null_rtc_get_time;
static int (*cf_rtc_set_time)(unsigned long) = null_rtc_set_time;
#endif /* CONFIG_GENERIC_CLOCKEVENTS */
/*
* old pre-GENERIC clock code
*/
#ifndef CONFIG_GENERIC_CLOCKEVENTS
/*
* timer_interrupt() needs to keep up the real-time clock,
* as well as call the "do_timer()" routine every clocktick
*/
static irqreturn_t timer_interrupt(int irq, void *dummy)
{
#ifdef CONFIG_COLDFIRE
/* kick hardware timer if necessary */
if (mach_tick)
mach_tick();
#endif
do_timer(1);
#ifndef CONFIG_SMP
update_process_times(user_mode(get_irq_regs()));
#endif
profile_tick(CPU_PROFILING);
#ifdef CONFIG_HEARTBEAT
/* use power LED as a heartbeat instead -- much more useful
for debugging -- based on the version for PReP by Cort */
/* acts like an actual heart beat -- ie thump-thump-pause... */
if (mach_heartbeat) {
unsigned cnt = 0, period = 0, dist = 0;
if (cnt == 0 || cnt == dist)
mach_heartbeat(1);
else if (cnt == 7 || cnt == dist+7)
mach_heartbeat(0);
if (++cnt > period) {
cnt = 0;
/* The hyperbolic function below modifies
* the heartbeat period length in dependency
* of the current (5min) load. It goes through
* the points f(0)=126, f(1)=86, f(5)=51,
* f(inf)->30. */
period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT)))
+ 30;
dist = period / 4;
}
}
#endif /* CONFIG_HEARTBEAT */
return IRQ_HANDLED;
}
void __init time_init(void)
{
struct rtc_time time;
if (mach_hwclk) {
mach_hwclk(0, &time);
time.tm_year += 1900;
if (time.tm_year < 1970)
time.tm_year += 100;
xtime.tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday,
time.tm_hour, time.tm_min, time.tm_sec);
xtime.tv_nsec = 0;
}
wall_to_monotonic.tv_sec = -xtime.tv_sec;
mach_sched_init(timer_interrupt);
}
#endif /* !CONFIG_GENERIC_CLOCKEVENTS */
#ifndef CONFIG_GENERIC_TIME
/*
* This version of gettimeofday has near microsecond resolution.
*/
void do_gettimeofday(struct timeval *tv)
{
unsigned long flags;
unsigned long seq;
unsigned long usec, sec;
unsigned long max_ntp_tick = tick_usec - tickadj;
do {
seq = read_seqbegin_irqsave(&xtime_lock, flags);
usec = mach_gettimeoffset();
/*
* If time_adjust is negative then NTP is slowing the clock
* so make sure not to go into next possible interval.
* Better to lose some accuracy than have time go backwards..
*/
if (unlikely(time_adjust < 0))
usec = min(usec, max_ntp_tick);
sec = xtime.tv_sec;
usec += xtime.tv_nsec/1000;
} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
while (usec >= 1000000) {
usec -= 1000000;
sec++;
}
tv->tv_sec = sec;
tv->tv_usec = usec;
}
EXPORT_SYMBOL(do_gettimeofday);
int do_settimeofday(struct timespec *tv)
{
time_t wtm_sec, sec = tv->tv_sec;
long wtm_nsec, nsec = tv->tv_nsec;
if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
return -EINVAL;
write_seqlock_irq(&xtime_lock);
/* This is revolting. We need to set the xtime.tv_nsec
* correctly. However, the value in this location is
* is value at the last tick.
* Discover what correction gettimeofday
* would have done, and then undo it!
*/
nsec -= 1000 * mach_gettimeoffset();
wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
set_normalized_timespec(&xtime, sec, nsec);
set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
ntp_clear();
write_sequnlock_irq(&xtime_lock);
clock_was_set();
return 0;
}
EXPORT_SYMBOL(do_settimeofday);
#endif /* !CONFIG_GENERIC_TIME */
#ifdef CONFIG_GENERIC_CLOCKEVENTS
/*
* Clock Evnt setup
*/
static struct clock_event_device clockevent_cfv4 = {
.name = "CFV4 timer2even",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.shift = 20,
.set_mode = cfv4_set_mode,
.set_next_event = cfv4_set_next_event,
};
static int cfv4_set_next_event(unsigned long evt,
struct clock_event_device *dev)
{
return 0;
}
static void cfv4_set_mode(enum clock_event_mode mode,
struct clock_event_device *dev)
{
if (mode != CLOCK_EVT_MODE_ONESHOT)
cfv4_set_next_event((FREQ / HZ), dev);
}
static int __init cfv4_clockevent_init(void)
{
clockevent_cfv4.mult =
div_sc(FREQ, NSEC_PER_SEC,
clockevent_cfv4.shift);
clockevent_cfv4.max_delta_ns =
clockevent_delta2ns((FREQ / HZ),
&clockevent_cfv4);
clockevent_cfv4.min_delta_ns =
clockevent_delta2ns(1, &clockevent_cfv4);
clockevent_cfv4.cpumask = &cpumask_of_cpu(0);
printk(KERN_INFO "timer: register clockevent\n");
clockevents_register_device(&clockevent_cfv4);
return 0;
}
/*
* clocksource setup
*/
struct clocksource clocksource_cfv4 = {
.name = "ColdfireV4",
.rating = 250,
.mask = CLOCKSOURCE_MASK(32),
.read = sys_dtim2_read,
.shift = 20,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/*
* Initialize time subsystem. Called from linux/init/main.c
*/
void __init time_init(void)
{
int ret;
printk(KERN_INFO "Initializing time\n");
#if 0
/* initialize system clocks */
clk_init();
#endif
cfv4_clockevent_init();
/* initialize the system timer */
/*sys_dtim_init();*/
sys_dtim2_init();
/* setup initial system time */
xtime.tv_sec = cf_rtc_get_time();
xtime.tv_nsec = 0;
set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec,
-xtime.tv_nsec);
/* JKM */
clocksource_cfv4.mult = clocksource_hz2mult(FREQ,
clocksource_cfv4.shift);
/* register our clocksource */
ret = clocksource_register(&clocksource_cfv4);
if (ret)
printk(KERN_ERR "timer: unable to "
"register clocksource - %d\n", ret);
}
/*
* sysfs pieces
*/
static struct sysdev_class timer_class = {
.name = "timer",
};
static struct sys_device timer_device = {
.id = 0,
.cls = &timer_class,
};
static int __init timer_init_sysfs(void)
{
int err = sysdev_class_register(&timer_class);
if (!err)
err = sysdev_register(&timer_device);
return err;
}
device_initcall(timer_init_sysfs);
#endif /* CONFIG_GENERIC_CLOCKEVENTS */

456
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/common/traps.c
View File

@ -1,456 +0,0 @@
/*
* linux/arch/m68knommu/kernel/traps.c
*
* Copyright Freescale Semiconductor, Inc. 2008-2009
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/*
* Sets up all exception vectors
*/
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/a.out.h>
#include <linux/user.h>
#include <linux/string.h>
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/ptrace.h>
#include <linux/kallsyms.h>
#include <asm/setup.h>
#include <asm/fpu.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/traps.h>
#include <asm/pgtable.h>
#include <asm/machdep.h>
#include <asm/siginfo.h>
static char const * const vec_names[] = {
"RESET SP", "RESET PC", "BUS ERROR", "ADDRESS ERROR",
"ILLEGAL INSTRUCTION", "ZERO DIVIDE", "CHK", "TRAPcc",
"PRIVILEGE VIOLATION", "TRACE", "LINE 1010", "LINE 1111",
"UNASSIGNED RESERVED 12", "COPROCESSOR PROTOCOL VIOLATION",
"FORMAT ERROR", "UNINITIALIZED INTERRUPT",
"UNASSIGNED RESERVED 16", "UNASSIGNED RESERVED 17",
"UNASSIGNED RESERVED 18", "UNASSIGNED RESERVED 19",
"UNASSIGNED RESERVED 20", "UNASSIGNED RESERVED 21",
"UNASSIGNED RESERVED 22", "UNASSIGNED RESERVED 23",
"SPURIOUS INTERRUPT", "LEVEL 1 INT", "LEVEL 2 INT", "LEVEL 3 INT",
"LEVEL 4 INT", "LEVEL 5 INT", "LEVEL 6 INT", "LEVEL 7 INT",
"SYSCALL", "TRAP #1", "TRAP #2", "TRAP #3",
"TRAP #4", "TRAP #5", "TRAP #6", "TRAP #7",
"TRAP #8", "TRAP #9", "TRAP #10", "TRAP #11",
"TRAP #12", "TRAP #13", "TRAP #14", "TRAP #15",
"FPCP BSUN", "FPCP INEXACT", "FPCP DIV BY 0", "FPCP UNDERFLOW",
"FPCP OPERAND ERROR", "FPCP OVERFLOW", "FPCP SNAN",
"FPCP UNSUPPORTED OPERATION",
"MMU CONFIGURATION ERROR"
};
asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
asmlinkage void trap_c(struct frame *fp);
extern void __init coldfire_trap_init(void);
void __init trap_init(void)
{
coldfire_trap_init();
}
/* The following table converts the FS encoding of a ColdFire
exception stack frame into the error_code value needed by
do_fault. */
static const unsigned char fs_err_code[] = {
0, /* 0000 */
0, /* 0001 */
0, /* 0010 */
0, /* 0011 */
1, /* 0100 */
0, /* 0101 */
0, /* 0110 */
0, /* 0111 */
2, /* 1000 */
3, /* 1001 */
2, /* 1010 */
0, /* 1011 */
1, /* 1100 */
1, /* 1101 */
0, /* 1110 */
0 /* 1111 */
};
#ifdef DEBUG
static const char *fs_err_msg[16] = {
"Normal",
"Reserved",
"Interrupt during debug service routine",
"Reserved",
"X Protection",
"TLB X miss (opword)",
"TLB X miss (ext. word)",
"IFP in emulator mode",
"W Protection",
"Write error",
"TLB W miss",
"Reserved",
"R Protection",
"R/RMW Protection",
"TLB R miss",
"OEP in emulator mode",
};
#endif
static inline void access_errorCF(struct frame *fp)
{
unsigned long int mmusr, complainingAddress;
unsigned int err_code, fs;
int need_page_fault;
mmusr = fp->ptregs.mmusr;
complainingAddress = fp->ptregs.mmuar;
#ifdef DEBUG
printk(KERN_DEBUG "pc %#lx, mmusr %#lx, complainingAddress %#lx\n", \
fp->ptregs.pc, mmusr, complainingAddress);
#endif
/*
* error_code:
* bit 0 == 0 means no page found, 1 means protection fault
* bit 1 == 0 means read, 1 means write
*/
fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1;
switch (fs) {
case 5: /* 0101 TLB opword X miss */
need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 0);
complainingAddress = fp->ptregs.pc;
break;
case 6: /* 0110 TLB extension word X miss */
need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 1);
complainingAddress = fp->ptregs.pc + sizeof(long);
break;
case 10: /* 1010 TLB W miss */
need_page_fault = cf_tlb_miss(&fp->ptregs, 1, 1, 0);
break;
case 14: /* 1110 TLB R miss */
need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 1, 0);
break;
default:
/* 0000 Normal */
/* 0001 Reserved */
/* 0010 Interrupt during debug service routine */
/* 0011 Reserved */
/* 0100 X Protection */
/* 0111 IFP in emulator mode */
/* 1000 W Protection*/
/* 1001 Write error*/
/* 1011 Reserved*/
/* 1100 R Protection*/
/* 1101 R Protection*/
/* 1111 OEP in emulator mode*/
need_page_fault = 1;
break;
}
if (need_page_fault) {
err_code = fs_err_code[fs];
if ((fs == 13) && (mmusr & MMUSR_WF)) /* rd-mod-wr access */
err_code |= 2; /* bit1 - write, bit0 - protection */
do_page_fault(&fp->ptregs, complainingAddress, err_code);
}
}
void die_if_kernel(char *str, struct pt_regs *fp, int nr)
{
if (!(fp->sr & PS_S))
return;
console_verbose();
printk(KERN_EMERG "%s: %08x\n", str, nr);
printk(KERN_EMERG "PC: [<%08lx>]", fp->pc);
print_symbol(" %s", fp->pc);
printk(KERN_EMERG "\nSR: %04x SP: %p a2: %08lx\n",
fp->sr, fp, fp->a2);
printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
fp->d0, fp->d1, fp->d2, fp->d3);
printk(KERN_EMERG "d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
fp->d4, fp->d5, fp->a0, fp->a1);
printk(KERN_EMERG "Process %s (pid: %d, stackpage=%08lx)\n",
current->comm, current->pid, PAGE_SIZE+(unsigned long)current);
show_stack(NULL, (unsigned long *)fp);
do_exit(SIGSEGV);
}
asmlinkage void buserr_c(struct frame *fp)
{
unsigned int fs;
/* Only set esp0 if coming from user mode */
if (user_mode(&fp->ptregs))
current->thread.esp0 = (unsigned long) fp;
fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1;
#if defined(DEBUG)
printk(KERN_DEBUG "*** Bus Error *** (%x)%s\n", fs,
fs_err_msg[fs & 0xf]);
#endif
switch (fs) {
case 0x5:
case 0x6:
case 0x7:
case 0x9:
case 0xa:
case 0xd:
case 0xe:
case 0xf:
access_errorCF(fp);
break;
default:
die_if_kernel("bad frame format", &fp->ptregs, 0);
#if defined(DEBUG)
printk(KERN_DEBUG "Unknown SIGSEGV - 4\n");
#endif
force_sig(SIGSEGV, current);
}
}
void show_trace(unsigned long *stack)
{
unsigned long *endstack;
unsigned long addr;
int i;
printk("Call Trace:");
addr = (unsigned long)stack + THREAD_SIZE - 1;
endstack = (unsigned long *)(addr & -THREAD_SIZE);
i = 0;
while (stack + 1 <= endstack) {
addr = *stack++;
/*
* If the address is either in the text segment of the
* kernel, or in the region which contains vmalloc'ed
* memory, it *may* be the address of a calling
* routine; if so, print it so that someone tracing
* down the cause of the crash will be able to figure
* out the call path that was taken.
*/
if (__kernel_text_address(addr)) {
#ifndef CONFIG_KALLSYMS
if (i % 5 == 0)
printk("\n ");
#endif
printk(" [<%08lx>] %pS\n", addr, (void *)addr);
i++;
}
}
printk("\n");
}
int kstack_depth_to_print = 48;
void show_stack(struct task_struct *task, unsigned long *stack)
{
unsigned long *p;
unsigned long *endstack;
int i;
if (!stack) {
if (task)
stack = (unsigned long *)task->thread.esp0;
else
stack = (unsigned long *)&stack;
}
endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1) & -THREAD_SIZE);
printk("Stack from %08lx:", (unsigned long)stack);
p = stack;
for (i = 0; i < kstack_depth_to_print; i++) {
if (p + 1 > endstack)
break;
if (i % 8 == 0)
printk("\n ");
printk(" %08lx", *p++);
}
printk("\n");
show_trace(stack);
}
void bad_super_trap(struct frame *fp)
{
console_verbose();
if (fp->ptregs.vector < sizeof(vec_names)/sizeof(vec_names[0]))
printk(KERN_WARNING "*** %s *** FORMAT=%X\n",
vec_names[fp->ptregs.vector],
fp->ptregs.format);
else
printk(KERN_WARNING "*** Exception %d *** FORMAT=%X\n",
fp->ptregs.vector,
fp->ptregs.format);
printk(KERN_WARNING "Current process id is %d\n", current->pid);
die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
}
asmlinkage void trap_c(struct frame *fp)
{
int sig;
siginfo_t info;
if (fp->ptregs.sr & PS_S) {
if (fp->ptregs.vector == VEC_TRACE) {
/* traced a trapping instruction */
current->ptrace |= PT_DTRACE;
} else
bad_super_trap(fp);
return;
}
/* send the appropriate signal to the user program */
switch (fp->ptregs.vector) {
case VEC_ADDRERR:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
break;
case VEC_ILLEGAL:
case VEC_LINE10:
case VEC_LINE11:
info.si_code = ILL_ILLOPC;
sig = SIGILL;
break;
case VEC_PRIV:
info.si_code = ILL_PRVOPC;
sig = SIGILL;
break;
case VEC_COPROC:
info.si_code = ILL_COPROC;
sig = SIGILL;
break;
case VEC_TRAP1: /* gdbserver breakpoint */
fp->ptregs.pc -= 2;
info.si_code = TRAP_TRACE;
sig = SIGTRAP;
break;
case VEC_TRAP2:
case VEC_TRAP3:
case VEC_TRAP4:
case VEC_TRAP5:
case VEC_TRAP6:
case VEC_TRAP7:
case VEC_TRAP8:
case VEC_TRAP9:
case VEC_TRAP10:
case VEC_TRAP11:
case VEC_TRAP12:
case VEC_TRAP13:
case VEC_TRAP14:
info.si_code = ILL_ILLTRP;
sig = SIGILL;
break;
case VEC_FPBRUC:
case VEC_FPOE:
case VEC_FPNAN:
info.si_code = FPE_FLTINV;
sig = SIGFPE;
break;
case VEC_FPIR:
info.si_code = FPE_FLTRES;
sig = SIGFPE;
break;
case VEC_FPDIVZ:
info.si_code = FPE_FLTDIV;
sig = SIGFPE;
break;
case VEC_FPUNDER:
info.si_code = FPE_FLTUND;
sig = SIGFPE;
break;
case VEC_FPOVER:
info.si_code = FPE_FLTOVF;
sig = SIGFPE;
break;
case VEC_ZERODIV:
info.si_code = FPE_INTDIV;
sig = SIGFPE;
break;
case VEC_CHK:
case VEC_TRAP:
info.si_code = FPE_INTOVF;
sig = SIGFPE;
break;
case VEC_TRACE: /* ptrace single step */
info.si_code = TRAP_TRACE;
sig = SIGTRAP;
break;
case VEC_TRAP15: /* breakpoint */
info.si_code = TRAP_BRKPT;
sig = SIGTRAP;
break;
default:
info.si_code = ILL_ILLOPC;
sig = SIGILL;
break;
}
info.si_signo = sig;
info.si_errno = 0;
switch (fp->ptregs.format) {
default:
info.si_addr = (void *) fp->ptregs.pc;
break;
case 2:
info.si_addr = (void *) fp->un.fmt2.iaddr;
break;
case 7:
info.si_addr = (void *) fp->un.fmt7.effaddr;
break;
case 9:
info.si_addr = (void *) fp->un.fmt9.iaddr;
break;
case 10:
info.si_addr = (void *) fp->un.fmta.daddr;
break;
case 11:
info.si_addr = (void *) fp->un.fmtb.daddr;
break;
}
force_sig_info(sig, &info, current);
}
asmlinkage void set_esp0(unsigned long ssp)
{
current->thread.esp0 = ssp;
}
/*
* The architecture-independent backtrace generator
*/
void dump_stack(void)
{
unsigned long stack;
show_stack(current, &stack);
}
EXPORT_SYMBOL(dump_stack);
#ifdef CONFIG_M68KFPU_EMU
asmlinkage void fpemu_signal(int signal, int code, void *addr)
{
siginfo_t info;
info.si_signo = signal;
info.si_errno = 0;
info.si_code = code;
info.si_addr = addr;
force_sig_info(signal, &info, current);
}
#endif

431
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/MCD_dma.h
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@ -1,431 +0,0 @@
/*
* drivers/dma/MCD_dma.h
*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan <kmahan@freescale.com>
* Shrek Wu b16972@freescale.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MCD_API_H
#define _MCD_API_H
/*
* Turn Execution Unit tasks ON (#define) or OFF (#undef)
*/
#undef MCD_INCLUDE_EU
/*
* Number of DMA channels
*/
#define NCHANNELS 16
/*
* Total number of variants
*/
#ifdef MCD_INCLUDE_EU
#define NUMOFVARIANTS 6
#else
#define NUMOFVARIANTS 4
#endif
/*
* Define sizes of the various tables
*/
#define TASK_TABLE_SIZE (NCHANNELS*32)
#define VAR_TAB_SIZE (128)
#define CONTEXT_SAVE_SIZE (128)
#define FUNCDESC_TAB_SIZE (256)
#ifdef MCD_INCLUDE_EU
#define FUNCDESC_TAB_NUM 16
#else
#define FUNCDESC_TAB_NUM 1
#endif
#ifndef DEFINESONLY
/*
* Portability typedefs
*/
typedef int s32;
typedef unsigned int u32;
typedef short s16;
typedef unsigned short u16;
typedef char s8;
typedef unsigned char u8;
/*
* These structures represent the internal registers of the
* multi-channel DMA
*/
struct dmaRegs_s {
u32 taskbar; /* task table base address register */
u32 currPtr;
u32 endPtr;
u32 varTablePtr;
u16 dma_rsvd0;
u16 ptdControl; /* ptd control */
u32 intPending; /* interrupt pending register */
u32 intMask; /* interrupt mask register */
u16 taskControl[16]; /* task control registers */
u8 priority[32]; /* priority registers */
u32 initiatorMux; /* initiator mux control */
u32 taskSize0; /* task size control register 0. */
u32 taskSize1; /* task size control register 1. */
u32 dma_rsvd1; /* reserved */
u32 dma_rsvd2; /* reserved */
u32 debugComp1; /* debug comparator 1 */
u32 debugComp2; /* debug comparator 2 */
u32 debugControl; /* debug control */
u32 debugStatus; /* debug status */
u32 ptdDebug; /* priority task decode debug */
u32 dma_rsvd3[31]; /* reserved */
};
typedef volatile struct dmaRegs_s dmaRegs;
#endif
/*
* PTD contrl reg bits
*/
#define PTD_CTL_TSK_PRI 0x8000
#define PTD_CTL_COMM_PREFETCH 0x0001
/*
* Task Control reg bits and field masks
*/
#define TASK_CTL_EN 0x8000
#define TASK_CTL_VALID 0x4000
#define TASK_CTL_ALWAYS 0x2000
#define TASK_CTL_INIT_MASK 0x1f00
#define TASK_CTL_ASTRT 0x0080
#define TASK_CTL_HIPRITSKEN 0x0040
#define TASK_CTL_HLDINITNUM 0x0020
#define TASK_CTL_ASTSKNUM_MASK 0x000f
/*
* Priority reg bits and field masks
*/
#define PRIORITY_HLD 0x80
#define PRIORITY_PRI_MASK 0x07
/*
* Debug Control reg bits and field masks
*/
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
#define DBG_CTL_AUTO_ARM 0x00008000
#define DBG_CTL_BREAK 0x00004000
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
#define DBG_CTL_EXT_BREAK 0x00000004
#define DBG_CTL_INT_BREAK 0x00000002
/*
* PTD Debug reg selector addresses
* This reg must be written with a value to show the contents of
* one of the desired internal register.
*/
#define PTD_DBG_REQ 0x00
/* shows the state of 31 initiators */
#define PTD_DBG_TSK_VLD_INIT 0x01
/* shows which 16 tasks are valid and
* have initiators asserted */
/*
* General return values
*/
#define MCD_OK 0
#define MCD_ERROR -1
#define MCD_TABLE_UNALIGNED -2
#define MCD_CHANNEL_INVALID -3
/*
* MCD_initDma input flags
*/
#define MCD_RELOC_TASKS 0x00000001
#define MCD_NO_RELOC_TASKS 0x00000000
#define MCD_COMM_PREFETCH_EN 0x00000002
/* Commbus Prefetching - MCF547x/548x ONLY */
/*
* MCD_dmaStatus Status Values for each channel
*/
#define MCD_NO_DMA 1
/* No DMA has been requested since reset */
#define MCD_IDLE 2
/* DMA active, but the initiator is currently inactive */
#define MCD_RUNNING 3
/* DMA active, and the initiator is currently active */
#define MCD_PAUSED 4
/* DMA active but it is currently paused */
#define MCD_HALTED 5
/* the most recent DMA has been killed with MCD_killTask() */
#define MCD_DONE 6
/* the most recent DMA has completed. */
/*
* MCD_startDma parameter defines
*/
/*
* Constants for the funcDesc parameter
*/
/* Byte swapping: */
#define MCD_NO_BYTE_SWAP 0x00045670
/* to disable byte swapping. */
#define MCD_BYTE_REVERSE 0x00076540
/* to reverse the bytes of each u32 of the DMAed data. */
#define MCD_U16_REVERSE 0x00067450
/* to reverse the 16-bit halves of
* each 32-bit data value being DMAed.*/
#define MCD_U16_BYTE_REVERSE 0x00054760
/* to reverse the byte halves of each
* 16-bit half of each 32-bit data value DMAed */
#define MCD_NO_BIT_REV 0x00000000
/* do not reverse the bits of each byte DMAed. */
#define MCD_BIT_REV 0x00088880
/* reverse the bits of each byte DMAed */
/* CRCing: */
#define MCD_CRC16 0xc0100000
/* to perform CRC-16 on DMAed data. */
#define MCD_CRCCCITT 0xc0200000
/* to perform CRC-CCITT on DMAed data. */
#define MCD_CRC32 0xc0300000
/* to perform CRC-32 on DMAed data. */
#define MCD_CSUMINET 0xc0400000
/* to perform internet checksums on DMAed data.*/
#define MCD_NO_CSUM 0xa0000000
/* to perform no checksumming. */
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
/*
* Constants for the flags parameter
*/
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
#define MCD_TT_FLAGS_SP 0x00000004
/* Speculative prefetch(XLB) MCF547x/548x ONLY */
#define MCD_TT_FLAGS_PI 0x00000040 /* Precise Increment */
#define MCD_TT_FLAGS_MASK 0x000000ff
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
#define MCD_CHAIN_DMA /* TBD */
#define MCD_EU_DMA /* TBD */
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
/* these flags are valid for MCD_startDma
* and the chained buffer descriptors */
#define MCD_BUF_READY 0x80000000
/* indicates that this buffer is now
* under the DMA's control */
#define MCD_WRAP 0x20000000
/* to tell the FEC Dmas to wrap to the first BD */
#define MCD_INTERRUPT 0x10000000
/* to generate an interrupt after completion of the DMA. */
#define MCD_END_FRAME 0x08000000
/* tell the DMA to end the frame when transferring
* last byte of data in buffer */
#define MCD_CRC_RESTART 0x40000000
/* to empty out the accumulated checksum
prior to performing the DMA. */
/* Defines for the FEC buffer descriptor control/status word*/
#define MCD_FEC_BUF_READY 0x8000
#define MCD_FEC_WRAP 0x2000
#define MCD_FEC_INTERRUPT 0x1000
#define MCD_FEC_END_FRAME 0x0800
/*
* Defines for general intuitiveness
*/
#define MCD_TRUE 1
#define MCD_FALSE 0
/*
* Three different cases for destination and source.
*/
#define MINUS1 -1
#define ZERO 0
#define PLUS1 1
#ifndef DEFINESONLY
/* Task Table Entry struct*/
typedef struct {
u32 TDTstart; /* task descriptor table start */
u32 TDTend; /* task descriptor table end */
u32 varTab; /* variable table start */
u32 FDTandFlags; /* function descriptor table start and flags */
volatile u32 descAddrAndStatus;
volatile u32 modifiedVarTab;
u32 contextSaveSpace; /* context save space start */
u32 literalBases;
} TaskTableEntry;
/* Chained buffer descriptor */
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
u32 flags;
/* flags describing the DMA */
u32 csumResult;
/* checksum from checksumming performed since last checksum reset */
s8 *srcAddr;
/* the address to move data from */
s8 *destAddr;
/* the address to move data to */
s8 *lastDestAddr;
/* the last address written to */
u32 dmaSize;
/* the number of bytes to transfer independent of the transfer size */
MCD_bufDesc *next;
/* next buffer descriptor in chain */
u32 info;
/* private information about this descriptor; DMA does not affect it */
};
/* Progress Query struct */
typedef volatile struct MCD_XferProg_struct {
s8 *lastSrcAddr;
/* the most-recent or last, post-increment source address */
s8 *lastDestAddr;
/* the most-recent or last, post-increment destination address */
u32 dmaSize;
/* the amount of data transferred for the current buffer */
MCD_bufDesc *currBufDesc;
/* pointer to the current buffer descriptor being DMAed */
} MCD_XferProg;
/* FEC buffer descriptor */
typedef volatile struct MCD_bufDescFec_struct {
u16 statCtrl;
u16 length;
u32 dataPointer;
} MCD_bufDescFec;
/*************************************************************************/
/*
* API function Prototypes - see MCD_dmaApi.c for further notes
*/
/*
* MCD_startDma starts a particular kind of DMA .
*/
int MCD_startDma(
int channel,
/* the channel on which to run the DMA */
s8 *srcAddr,
/* the address to move data from, or buffer-descriptor address */
s16 srcIncr,
/* the amount to increment the source address per transfer */
s8 *destAddr,
/* the address to move data to */
s16 destIncr,
/* the amount to increment the destination address per transfer */
u32 dmaSize,
/* the number of bytes to transfer independent of the transfer size */
u32 xferSize,
/* the number bytes in of each data movement (1, 2, or 4) */
u32 initiator,
/* what device initiates the DMA */
int priority,
/* priority of the DMA */
u32 flags,
/* flags describing the DMA */
u32 funcDesc
/* a description of byte swapping, bit swapping, and CRC actions */
);
/*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and
* setting up some global settings
*/
int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
/*
* MCD_dmaStatus() returns the status of the DMA on the requested channel.
*/
int MCD_dmaStatus(int channel);
/*
* MCD_XferProgrQuery() returns progress of DMA on requested channel
*/
int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep);
/*
* MCD_killDma() halts the DMA on the requested channel, without any
* intention of resuming the DMA.
*/
int MCD_killDma(int channel);
/*
* MCD_continDma() continues a DMA which as stopped due to encountering an
* unready buffer descriptor.
*/
int MCD_continDma(int channel);
/*
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
* running on that channel).
*/
int MCD_pauseDma(int channel);
/*
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
* running on that channel).
*/
int MCD_resumeDma(int channel);
/*
* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
*/
int MCD_csumQuery(int channel, u32 *csum);
/*
* MCD_getCodeSize provides the packed size required by the microcoded task
* and structures.
*/
int MCD_getCodeSize(void);
/*
* MCD_getVersion provides a pointer to a version string and returns a
* version number.
*/
int MCD_getVersion(char **longVersion);
/* macro for setting a location in the variable table */
#define MCD_SET_VAR(taskTab, idx, value) \
((u32 *)(taskTab)->varTab)[idx] = value
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
so I'm avoiding surrounding it with "do {} while(0)" */
#endif /* DEFINESONLY */
#endif /* _MCD_API_H */

1045
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/MCD_dmaApi.c
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29
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/MCD_progCheck.h
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@ -1,29 +0,0 @@
/*
* drivers/dma/MCD_progCheck.h
*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan <kmahan@freescale.com>
* Shrek Wu b16972@freescale.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This file is autogenerated. Do not change */
#define CURRBD 4
#define DCOUNT 6
#define DESTPTR 5
#define SRCPTR 7

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target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/MCD_tasks.c
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target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/MCD_tasksInit.c
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/*
* drivers/dma/MCD_tasksInit.c
*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan <kmahan@freescale.com>
* Shrek Wu b16972@freescale.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Autogenerated - Do not edit!
*/
#include "MCD_dma.h"
extern dmaRegs *MCD_dmaBar;
/*
* Task 0
*/
void MCD_startDmaChainNoEu(int *currBD, short srcIncr,
short destIncr, int xferSize, short xferSizeIncr,
int *cSave, volatile TaskTableEntry *taskTable,
int channel)
{
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 25,
(u32)(0xe000 << 16) | (0xffff & srcIncr));
/* inc[1] */
MCD_SET_VAR(taskTable+channel, 24,
(u32)(0xe000 << 16) | (0xffff & destIncr));
/* inc[0] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */
MCD_SET_VAR(taskTable+channel, 26,
(u32)(0x2000 << 16) | (0xffff & xferSizeIncr));
/* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 1
*/
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr,
char *destAddr, short destIncr, int dmaSize,
short xferSizeIncr, int flags, int *currBD, int *cSave,
volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */
MCD_SET_VAR(taskTable+channel, 25,
(u32)(0xe000 << 16) | (0xffff & srcIncr));
/* inc[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */
MCD_SET_VAR(taskTable+channel, 24,
(u32)(0xe000 << 16) | (0xffff & destIncr));
/* inc[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */
MCD_SET_VAR(taskTable+channel, 26,
(u32)(0x2000 << 16) | (0xffff & xferSizeIncr));
/* inc[2] */
MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */
MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 2
*/
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 25,
(u32)(0xe000 << 16) | (0xffff & srcIncr));
/* inc[1] */
MCD_SET_VAR(taskTable+channel, 24,
(u32)(0xe000 << 16) | (0xffff & destIncr));
/* inc[0] */
MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize);
/* var[12] */
MCD_SET_VAR(taskTable+channel, 26,
(u32)(0x2000 << 16) | (0xffff & xferSizeIncr));
/* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */
MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */
MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 3
*/
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr,
char *destAddr, short destIncr, int dmaSize,
short xferSizeIncr, int flags, int *currBD, int *cSave,
volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */
MCD_SET_VAR(taskTable+channel, 25,
(u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */
MCD_SET_VAR(taskTable+channel, 24,
(u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */
MCD_SET_VAR(taskTable+channel, 26,
(u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 4
*/
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 5
*/
void MCD_startDmaENetXmit(char *bDBase, char *currBD,
char *xmitFifoPtr, volatile TaskTableEntry *taskTable,
int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}

84
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/MCD_tasksInit.h
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@ -1,84 +0,0 @@
/*
* drivers/dma/MCD_tasksInit.h
*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan <kmahan@freescale.com>
* Shrek Wu b16972@freescale.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MCD_TSK_INIT_H
#define MCD_TSK_INIT_H 1
/*
* Autogenerated - Do not edit!
*/
/*
* Task 0
*/
void MCD_startDmaChainNoEu(int *currBD, short srcIncr,
short destIncr, int xferSize,
short xferSizeIncr, int *cSave,
volatile TaskTableEntry *taskTable,
int channel);
/*
* Task 1
*/
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr,
char *destAddr, short destIncr, int dmaSize,
short xferSizeIncr, int flags, int *currBD,
int *cSave, volatile TaskTableEntry *taskTable,
int channel);
/*
* Task 2
*/
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry *taskTable,
int channel);
/*
* Task 3
*/
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr,
char *destAddr, short destIncr, int dmaSize,
short xferSizeIncr, int flags, int *currBD,
int *cSave, volatile TaskTableEntry *taskTable,
int channel);
/*
* Task 4
*/
void MCD_startDmaENetRcv(char *bDBase, char *currBD,
char *rcvFifoPtr,
volatile TaskTableEntry *taskTable, int channel);
/*
* Task 5
*/
void MCD_startDmaENetXmit(char *bDBase, char *currBD,
char *xmitFifoPtr,
volatile TaskTableEntry *taskTable, int channel);
#endif /* MCD_TSK_INIT_H */

7
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/Makefile
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@ -1,7 +0,0 @@
#
# Makefile for Linux arch/m68k/coldfire/m547x source directory
#
obj-$(CONFIG_M547X_8X) += config.o mcf548x-devices.o devices.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_MCD_DMA) += dma.o MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o

435
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/config.c
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@ -1,435 +0,0 @@
/*
* linux/arch/m68k/coldfire/config.c
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan kmahan@freescale.com
* Matt Waddel Matt.Waddel@freescale.com
* Shrek Wu b16972@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/bootmem.h>
#include <linux/mm.h>
#include <linux/clockchips.h>
#include <asm/bootinfo.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/cfcache.h>
#include <asm/cacheflush.h>
#include <linux/io.h>
#include <asm/cfmmu.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/movs.h>
#include <asm/movs.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/mcfsim.h>
#define UBOOT_PCI
#include <asm/bootinfo.h>
#include <asm/m5485gpt.h>
extern int get_irq_list(struct seq_file *p, void *v);
extern char _text, _end;
extern char _etext, _edata, __init_begin, __init_end;
extern struct console mcfrs_console;
extern char m68k_command_line[CL_SIZE];
extern unsigned long availmem;
static int irq_enable[NR_IRQS];
unsigned long num_pages;
/* cf dma physical addresses */
unsigned long cf_dma_base;
unsigned long cf_dma_end;
unsigned long cf_dma_size;
EXPORT_SYMBOL(cf_dma_base);
EXPORT_SYMBOL(cf_dma_end);
EXPORT_SYMBOL(cf_dma_size);
/* ethernet mac addresses from uboot */
unsigned char uboot_enet0[6];
unsigned char uboot_enet1[6];
void coldfire_sort_memrec(void)
{
int i, j;
/* Sort the m68k_memory records by address */
for (i = 0; i < m68k_num_memory; ++i) {
for (j = i + 1; j < m68k_num_memory; ++j) {
if (m68k_memory[i].addr > m68k_memory[j].addr) {
struct mem_info tmp;
tmp = m68k_memory[i];
m68k_memory[i] = m68k_memory[j];
m68k_memory[j] = tmp;
}
}
}
/* Trim off discontiguous bits */
for (i = 1; i < m68k_num_memory; ++i) {
if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) !=
m68k_memory[i].addr) {
printk(KERN_DEBUG "m68k_parse_bootinfo: "
"addr gap between 0x%lx & 0x%lx\n",
m68k_memory[i-1].addr+m68k_memory[i-1].size,
m68k_memory[i].addr);
m68k_num_memory = i;
break;
}
}
}
/*
* UBoot Handler
*/
int __init uboot_commandline(char *bootargs)
{
int len = 0, cmd_line_len;
static struct uboot_record uboot_info;
u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET;
extern unsigned long uboot_info_stk;
/* validate address */
if ((uboot_info_stk < PAGE_OFFSET_RAW) ||
(uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE)))
return 0;
/* Add offset to get post-remapped kernel memory location */
uboot_info.bdi = (struct bd_info *)((*(u32 *)(uboot_info_stk))
+ offset);
uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
/* copy over mac addresses */
memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6);
memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6);
/* copy command line */
cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\
cmd_line_len);
return len;
}
/*
* This routine does things not done in the bootloader.
*/
#define DEFAULT_COMMAND_LINE \
"debug root=/dev/nfs rw \
nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ \
ip=172.27.155.75:172.27.155.1"
asmlinkage void __init cf_early_init(void)
{
struct bi_record *record = (struct bi_record *) &_end;
extern char _end;
SET_VBR((void *)MCF_RAMBAR0);
/* Mask all interrupts */
MCF_IMRL = 0xFFFFFFFF;
MCF_IMRH = 0xFFFFFFFF;
m68k_machtype = MACH_CFMMU;
m68k_fputype = FPU_CFV4E;
m68k_mmutype = MMU_CFV4E;
m68k_cputype = CPU_CFV4E;
m68k_num_memory = 0;
m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE;
m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
if (!uboot_commandline(m68k_command_line)) {
#if defined(CONFIG_BOOTPARAM)
strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
#else
strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
#endif
}
#if defined(CONFIG_BLK_DEV_INITRD)
/* add initrd image */
record = (struct bi_record *) ((void *)record + record->size);
record->tag = BI_RAMDISK;
record->size = sizeof(record->tag) + sizeof(record->size)
+ sizeof(record->data[0]) + sizeof(record->data[1]);
#endif
/* Mark end of tags. */
record = (struct bi_record *) ((void *) record + record->size);
record->tag = 0;
record->data[0] = 0;
record->data[1] = 0;
record->size = sizeof(record->tag) + sizeof(record->size)
+ sizeof(record->data[0]) + sizeof(record->data[1]);
/* Invalidate caches via CACR */
flush_bcache();
cacr_set(CACHE_DISABLE_MODE);
/* Turn on caches via CACR, enable EUSP */
cacr_set(CACHE_INITIAL_MODE);
}
/* Assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
void __init coldfire_trap_init(void)
{
int i = 0;
e_vector *vectors;
vectors = (e_vector *)MCF_RAMBAR0;
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
for (i = 3; (i <= 23); i++)
vectors[i] = trap;
for (i = 33; (i <= 63); i++)
vectors[i] = trap;
for (i = 24; (i <= 31); i++)
vectors[i] = inthandler;
for (i = 64; (i < 255); i++)
vectors[i] = inthandler;
vectors[255] = 0;
vectors[2] = buserr;
vectors[32] = system_call;
}
#ifndef CONFIG_GENERIC_CLOCKEVENTS
void coldfire_tick(void)
{
/* Reset the ColdFire timer */
MCF_SSR(0) = MCF_SSR_ST;
}
void __init coldfire_sched_init(irq_handler_t handler)
{
int irq = ISC_SLTn(0);
MCF_SCR(0) = 0;
MCF_ICR(irq) = ILP_SLT0;
request_irq(64 + irq, handler, IRQF_DISABLED, "ColdFire Timer 0", NULL);
MCF_SLTCNT(0) = MCF_BUSCLK / HZ;
MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN;
}
unsigned long coldfire_gettimeoffset(void)
{
volatile unsigned long trr, tcn, offset;
trr = MCF_SLTCNT(0);
tcn = MCF_SCNT(0);
offset = (trr - tcn) * ((1000000 >> 3) / HZ) / (trr >> 3);
if (MCF_SSR(0) & MCF_SSR_ST)
offset += 1000000 / HZ;
return offset;
}
#else
static unsigned long long sched_dtim_clk_val;
unsigned long long sched_clock(void)
{
unsigned long flags;
unsigned long long cycles;
volatile unsigned long trr, tcn, offset;
local_irq_save(flags);
trr = MCF_SLTCNT(0);
tcn = MCF_SCNT(0);
offset = (trr - tcn);
cycles = sched_dtim_clk_val;
local_irq_restore(flags);
return cycles + offset;
}
unsigned long long sys_dtim2_read(void)
{
unsigned long flags;
unsigned long long cycles;
volatile unsigned long trr, tcn, offset;
local_irq_save(flags);
trr = MCF_SLTCNT(0);
tcn = MCF_SCNT(0);
offset = (trr - tcn);
cycles = sched_dtim_clk_val;
local_irq_restore(flags);
return cycles + offset;
}
static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev)
{
struct clock_event_device *evt =
(struct clock_event_device *)dev;
MCF_SSR(0) = MCF_SSR_ST;
sched_dtim_clk_val += (MCF_BUSCLK) / HZ;;
evt->event_handler(evt);
return IRQ_HANDLED;
}
void sys_dtim2_init(struct clock_event_device *evt)
{
int irq = ISC_SLTn(0);
sched_dtim_clk_val = 0;
MCF_SCR(0) = 0;
MCF_ICR(irq) = ILP_SLT0;
request_irq(64 + irq, coldfire_dtim_clk_irq, IRQF_DISABLED,
"ColdFire Timer 0", (void *)evt);
MCF_SLTCNT(0) = MCF_BUSCLK / HZ;
MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN;
}
#endif
void coldfire_reboot(void)
{
/* disable interrupts and enable the watchdog */
printk(KERN_INFO "Rebooting\n");
asm("movew #0x2700, %sr\n");
MCF_GPT_GMS0 = MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4);
}
static void coldfire_get_model(char *model)
{
sprintf(model, "Version 4 ColdFire");
}
static void __init
coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end)
{
unsigned long base_pfn;
/* compute total pages in system */
num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT;
/* align start/end to page boundries */
memory_start = PAGE_ALIGN(memory_start);
memory_end = memory_end & PAGE_MASK;
/* page numbers */
base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT;
min_low_pfn = __pa(memory_start) >> PAGE_SHIFT;
max_low_pfn = __pa(memory_end) >> PAGE_SHIFT;
high_memory = (void *)memory_end;
availmem = memory_start;
/* setup bootmem data */
m68k_setup_node(0);
availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn,
base_pfn, max_low_pfn);
availmem = PAGE_ALIGN(availmem);
printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n",
availmem, __pa(availmem));
printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n",
memory_start, memory_end);
printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n",
base_pfn, min_low_pfn, max_low_pfn);
/* turn over physram */
free_bootmem(__pa(availmem), memory_end - (availmem));
/* configure physical dma area */
cf_dma_base = __pa(PAGE_ALIGN(memory_start));
cf_dma_size = CONFIG_DMA_SIZE;
cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1;
printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n",
cf_dma_base, cf_dma_end, CONFIG_DMA_BASE);
printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n",
MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS));
}
void __init config_coldfire(void)
{
unsigned long endmem, startmem;
int i;
/*
* Calculate endmem from m68k_memory, assume all are contiguous
*/
startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK);
endmem = PAGE_OFFSET;
for (i = 0; i < m68k_num_memory; ++i)
endmem += m68k_memory[i].size;
printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \
size %luMB\n", startmem, endmem, (endmem - startmem) >> 20);
memset(irq_enable, 0, sizeof(irq_enable));
/*
* Setup coldfire mach-specific handlers
*/
mach_max_dma_address = 0xffffffff;
#ifndef CONFIG_GENERIC_CLOCKEVENTS
mach_sched_init = coldfire_sched_init;
mach_tick = coldfire_tick;
mach_gettimeoffset = coldfire_gettimeoffset;
#endif
mach_reset = coldfire_reboot;
/* mach_hwclk = coldfire_hwclk; to be done */
mach_get_model = coldfire_get_model;
coldfire_bootmem_alloc(startmem, endmem-1);
/*
* initrd setup
*/
/* #ifdef CONFIG_BLK_DEV_INITRD
if (m68k_ramdisk.size) {
reserve_bootmem (__pa(m68k_ramdisk.addr), m68k_ramdisk.size);
initrd_start = (unsigned long) m68k_ramdisk.addr;
initrd_end = initrd_start + m68k_ramdisk.size;
printk (KERN_DEBUG "initrd: %08lx - %08lx\n", initrd_start,
initrd_end);
}
#endif */
#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE)
conswitchp = &dummy_con;
#endif
#if defined(CONFIG_SERIAL_COLDFIRE)
/*
* This causes trouble when it is re-registered later.
* Currently this is fixed by conditionally commenting
* out the register_console in mcf_serial.c
*/
register_console(&mcfrs_console);
#endif
}

176
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/devices.c
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@ -1,176 +0,0 @@
/*
* arch/m68k/coldfire/m547x/devices.c
*
* Coldfire M547x/M548x Platform Device Configuration
*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* Kurt Mahan <kmahan@freescale.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#ifdef CONFIG_SPI
#include <asm/mcfqspi.h>
/*
*
* DSPI
*
*/
/* number of supported SPI selects */
#define SPI_NUM_CHIPSELECTS 8
void coldfire_spi_cs_control(u8 cs, u8 command)
{
/* nothing special required */
}
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct coldfire_spi_chip spidev_chip_info = {
.bits_per_word = 8,
};
#endif
static struct spi_board_info spi_board_info[] = {
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */
.bus_num = 1,
.chip_select = 0, /* CS0 */
.controller_data = &spidev_chip_info,
}
#endif
};
static int spi_irq_list[] = {
/* IRQ, ICR Offset, ICR Val,Mask */
64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW, 0x18, 0,
64 + ISC_DSPI_RFOF, ISC_DSPI_RFOF, 0x18, 0,
64 + ISC_DSPI_RFDF, ISC_DSPI_RFDF, 0x18, 0,
64 + ISC_DSPI_TFUF, ISC_DSPI_TFUF, 0x18, 0,
64 + ISC_DSPI_TCF, ISC_DSPI_TCF, 0x18, 0,
64 + ISC_DSPI_TFFF, ISC_DSPI_TFFF, 0x18, 0,
64 + ISC_DSPI_EOQF, ISC_DSPI_EOQF, 0x18, 0,
0,0,0,0,
};
static struct coldfire_spi_master coldfire_master_info = {
.bus_num = 1,
.num_chipselect = SPI_NUM_CHIPSELECTS,
.irq_list = spi_irq_list,
.irq_source = 0, /* not used */
.irq_vector = 0, /* not used */
.irq_mask = 0, /* not used */
.irq_lp = 0, /* not used */
.par_val = 0, /* not used */
.cs_control = coldfire_spi_cs_control,
};
static struct resource coldfire_spi_resources[] = {
[0] = {
.name = "spi-par",
.start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
.end = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
.flags = IORESOURCE_MEM
},
[1] = {
.name = "spi-module",
.start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */
.end = MCF_MBAR + 0x00008ab8, /* DSPI mem map end */
.flags = IORESOURCE_MEM
},
[2] = {
.name = "spi-int-level",
.start = MCF_MBAR + 0x740, /* ICR start */
.end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */
.flags = IORESOURCE_MEM
},
[3] = {
.name = "spi-int-mask",
.start = MCF_MBAR + 0x70c, /* IMRL */
.end = MCF_MBAR + 0x70c, /* IMRL */
.flags = IORESOURCE_MEM
}
};
static struct platform_device coldfire_spi = {
.name = "spi_coldfire",
.id = -1,
.resource = coldfire_spi_resources,
.num_resources = ARRAY_SIZE(coldfire_spi_resources),
.dev = {
.platform_data = &coldfire_master_info,
}
};
/**
* m547x_8x_spi_init - Initialize SPI
*/
static int __init m547x_8x_spi_init(void)
{
int retval;
/* initialize the DSPI PAR */
MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 |
MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS |
MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS |
MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS |
MCF_GPIO_PAR_DSPI_PAR_SCK_SCK |
MCF_GPIO_PAR_DSPI_PAR_SIN_SIN |
MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT);
/* register device */
retval = platform_device_register(&coldfire_spi);
if (retval < 0) {
goto out;
}
/* register board info */
if (ARRAY_SIZE(spi_board_info))
retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
out:
return retval;
}
#endif
#ifdef CONFIG_I2C_BOARDINFO
static struct i2c_board_info mcf_i2c_devices[] = {
{
I2C_BOARD_INFO("rv5c387a", 0x32),
},
};
#endif
/**
* m547x_8x_init_devices - Initialize M547X_8X devices
*
* Returns 0 on success.
*/
static int __init m547x_8x_init_devices(void)
{
#ifdef CONFIG_SPI
m547x_8x_spi_init();
#endif
#ifdef CONFIG_I2C_BOARDINFO
i2c_register_board_info(0, mcf_i2c_devices,
ARRAY_SIZE(mcf_i2c_devices));
#endif
return 0;
}
arch_initcall(m547x_8x_init_devices);

518
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/dma.c
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@ -1,518 +0,0 @@
/*
* arch/m68k/coldfire/m547x/dma.c
*
* Coldfire M547x/M548x DMA
*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan <kmahan@freescale.com>
* Shrek Wu b16972@freescale.com
*
* This code is based on patches from the Freescale M547x_8x BSP
* release mcf547x_8x-20070107-ltib.iso
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/dma.h>
#include <asm/coldfire.h>
#include <asm/m5485sram.h>
#include <asm/mcfsim.h>
#include <asm/MCD_dma.h>
/*
* This global keeps track of which initiators have been
* used of the available assignments. Initiators 0-15 are
* hardwired. Initiators 16-31 are multiplexed and controlled
* via the Initiatior Mux Control Registe (IMCR). The
* assigned requestor is stored with the associated initiator
* number.
*/
static int used_reqs[32] = {
DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0,
DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1,
DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX,
DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0
};
/*
* This global keeps track of which channels have been assigned
* to tasks. This methology assumes that no single initiator
* will be tied to more than one task/channel
*/
static char used_channel[16] = {
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1
};
unsigned int connected_channel[16] = {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
};
/**
* dma_set_initiator - enable initiator
* @initiator: initiator identifier
*
* Returns 0 of successful, non-zero otherwise
*
* Attempt to enable the provided Initiator in the Initiator
* Mux Control Register.
*/
int dma_set_initiator(int initiator)
{
switch (initiator) {
case DMA_ALWAYS:
case DMA_DSPI_RX:
case DMA_DSPI_TX:
case DMA_DREQ0:
case DMA_PSC0_RX:
case DMA_PSC0_TX:
case DMA_USBEP0:
case DMA_USBEP1:
case DMA_USBEP2:
case DMA_USBEP3:
case DMA_PCI_TX:
case DMA_PCI_RX:
case DMA_PSC1_RX:
case DMA_PSC1_TX:
case DMA_I2C_RX:
case DMA_I2C_TX:
/*
* These initiators are always active
*/
break;
case DMA_FEC0_RX:
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3))
| MCF_DMA_IMCR_SRC16_FEC0RX;
used_reqs[16] = DMA_FEC0_RX;
break;
case DMA_FEC0_TX:
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3))
| MCF_DMA_IMCR_SRC17_FEC0TX;
used_reqs[17] = DMA_FEC0_TX;
break;
case DMA_FEC1_RX:
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3))
| MCF_DMA_IMCR_SRC20_FEC1RX;
used_reqs[20] = DMA_FEC1_RX;
break;
case DMA_FEC1_TX:
if (used_reqs[21] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
| MCF_DMA_IMCR_SRC21_FEC1TX;
used_reqs[21] = DMA_FEC1_TX;
} else if (used_reqs[25] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
| MCF_DMA_IMCR_SRC25_FEC1TX;
used_reqs[25] = DMA_FEC1_TX;
} else if (used_reqs[31] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
| MCF_DMA_IMCR_SRC31_FEC1TX;
used_reqs[31] = DMA_FEC1_TX;
} else /* No empty slots */
return 1;
break;
case DMA_DREQ1:
if (used_reqs[29] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
| MCF_DMA_IMCR_SRC29_DREQ1;
used_reqs[29] = DMA_DREQ1;
} else if (used_reqs[21] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
| MCF_DMA_IMCR_SRC21_DREQ1;
used_reqs[21] = DMA_DREQ1;
} else /* No empty slots */
return 1;
break;
case DMA_CTM0:
if (used_reqs[24] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3))
| MCF_DMA_IMCR_SRC24_CTM0;
used_reqs[24] = DMA_CTM0;
} else /* No empty slots */
return 1;
break;
case DMA_CTM1:
if (used_reqs[25] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
| MCF_DMA_IMCR_SRC25_CTM1;
used_reqs[25] = DMA_CTM1;
} else /* No empty slots */
return 1;
break;
case DMA_CTM2:
if (used_reqs[26] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
| MCF_DMA_IMCR_SRC26_CTM2;
used_reqs[26] = DMA_CTM2;
} else /* No empty slots */
return 1;
break;
case DMA_CTM3:
if (used_reqs[27] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
| MCF_DMA_IMCR_SRC27_CTM3;
used_reqs[27] = DMA_CTM3;
} else /* No empty slots */
return 1;
break;
case DMA_CTM4:
if (used_reqs[28] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
| MCF_DMA_IMCR_SRC28_CTM4;
used_reqs[28] = DMA_CTM4;
} else /* No empty slots */
return 1;
break;
case DMA_CTM5:
if (used_reqs[29] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
| MCF_DMA_IMCR_SRC29_CTM5;
used_reqs[29] = DMA_CTM5;
} else /* No empty slots */
return 1;
break;
case DMA_CTM6:
if (used_reqs[30] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
| MCF_DMA_IMCR_SRC30_CTM6;
used_reqs[30] = DMA_CTM6;
} else /* No empty slots */
return 1;
break;
case DMA_CTM7:
if (used_reqs[31] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
| MCF_DMA_IMCR_SRC31_CTM7;
used_reqs[31] = DMA_CTM7;
} else /* No empty slots */
return 1;
break;
case DMA_USBEP4:
if (used_reqs[26] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
| MCF_DMA_IMCR_SRC26_USBEP4;
used_reqs[26] = DMA_USBEP4;
} else /* No empty slots */
return 1;
break;
case DMA_USBEP5:
if (used_reqs[27] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
| MCF_DMA_IMCR_SRC27_USBEP5;
used_reqs[27] = DMA_USBEP5;
} else /* No empty slots */
return 1;
break;
case DMA_USBEP6:
if (used_reqs[28] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
| MCF_DMA_IMCR_SRC28_USBEP6;
used_reqs[28] = DMA_USBEP6;
} else /* No empty slots */
return 1;
break;
case DMA_PSC2_RX:
if (used_reqs[28] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
| MCF_DMA_IMCR_SRC28_PSC2RX;
used_reqs[28] = DMA_PSC2_RX;
} else /* No empty slots */
return 1;
break;
case DMA_PSC2_TX:
if (used_reqs[29] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
| MCF_DMA_IMCR_SRC29_PSC2TX;
used_reqs[29] = DMA_PSC2_TX;
} else /* No empty slots */
return 1;
break;
case DMA_PSC3_RX:
if (used_reqs[30] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
| MCF_DMA_IMCR_SRC30_PSC3RX;
used_reqs[30] = DMA_PSC3_RX;
} else /* No empty slots */
return 1;
break;
case DMA_PSC3_TX:
if (used_reqs[31] == 0) {
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
| MCF_DMA_IMCR_SRC31_PSC3TX;
used_reqs[31] = DMA_PSC3_TX;
} else /* No empty slots */
return 1;
break;
default:
return 1;
}
return 0;
}
/**
* dma_get_initiator - get the initiator for the given requestor
* @requestor: initiator identifier
*
* Returns initiator number (0-31) if assigned or just 0
*/
unsigned int dma_get_initiator(int requestor)
{
u32 i;
for (i = 0; i < sizeof(used_reqs); ++i) {
if (used_reqs[i] == requestor)
return i;
}
return 0;
}
/**
* dma_remove_initiator - remove the given initiator from active list
* @requestor: requestor to remove
*/
void dma_remove_initiator(int requestor)
{
u32 i;
for (i = 0; i < sizeof(used_reqs); ++i) {
if (used_reqs[i] == requestor) {
used_reqs[i] = -1;
break;
}
}
}
/**
* dma_set_channel_fec: find available channel for fec and mark
* @requestor: initiator/requestor identifier
*
* Returns first avaialble channel (0-5) or -1 if all occupied
*/
int dma_set_channel_fec(int requestor)
{
u32 i, t;
#ifdef CONFIG_FEC_548x_ENABLE_FEC2
t = 4;
#else
t = 2;
#endif
for (i = 0; i < t ; ++i) {
if (used_channel[i] == -1) {
used_channel[i] = requestor;
return i;
}
}
/* All channels taken */
return -1;
}
/**
* dma_set_channel - find an available channel and mark as used
* @requestor: initiator/requestor identifier
*
* Returns first available channel (6-15) or -1 if all occupied
*/
int dma_set_channel(int requestor)
{
u32 i;
#ifdef CONFIG_NET_FEC2
i = 4;
#else
i = 2;
#endif
for (; i < 16; ++i)
if (used_channel[i] == -1) {
used_channel[i] = requestor;
return i;
}
/* All channels taken */
return -1;
}
/**
* dma_get_channel - get the channel being initiated by the requestor
* @requestor: initiator/requestor identifier
*
* Returns Initiator for requestor or -1 if not found
*/
int dma_get_channel(int requestor)
{
u32 i;
for (i = 0; i < sizeof(used_channel); ++i) {
if (used_channel[i] == requestor)
return i;
}
return -1;
}
/**
* dma_connect - connect a channel with reference on data
* @channel: channel number
* @address: reference address of data
*
* Returns 0 if success or -1 if invalid channel
*/
int dma_connect(int channel, int address)
{
if ((channel < 16) && (channel >= 0)) {
connected_channel[channel] = address;
return 0;
}
return -1;
}
/**
* dma_disconnect - disconnect a channel
* @channel: channel number
*
* Returns 0 if success or -1 if invalid channel
*/
int dma_disconnect(int channel)
{
if ((channel < 16) && (channel >= 0)) {
connected_channel[channel] = 0;
return 0;
}
return -1;
}
/**
* dma_remove_channel - remove channel from the active list
* @requestor: initiator/requestor identifier
*/
void dma_remove_channel(int requestor)
{
u32 i;
for (i = 0; i < sizeof(used_channel); ++i) {
if (used_channel[i] == requestor) {
used_channel[i] = -1;
break;
}
}
}
/**
* dma_interrupt_handler - dma interrupt handler
* @irq: interrupt number
* @dev_id: data
*
* Returns IRQ_HANDLED
*/
irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
{
u32 i, interrupts;
/*
* Determine which interrupt(s) triggered by AND'ing the
* pending interrupts with those that aren't masked.
*/
interrupts = MCF_DMA_DIPR;
MCF_DMA_DIPR = interrupts;
for (i = 0; i < 16; ++i, interrupts >>= 1) {
if (interrupts & 0x1)
if (connected_channel[i] != 0)
((void (*)(void)) (connected_channel[i])) ();
}
return IRQ_HANDLED;
}
/**
* dma_remove_channel_by_number - clear dma channel
* @channel: channel number to clear
*/
void dma_remove_channel_by_number(int channel)
{
if ((channel < sizeof(used_channel)) && (channel >= 0))
used_channel[channel] = -1;
}
/**
* dma_init - initialize the dma subsystem
*
* Returns 0 if success non-zero if failure
*
* Handles the DMA initialization during device setup.
*/
int __devinit dma_init()
{
int result;
char *dma_version_str;
MCD_getVersion(&dma_version_str);
printk(KERN_INFO "m547x_8x DMA: Initialize %s\n", dma_version_str);
/* attempt to setup dma interrupt handler */
if (request_irq(64 + ISC_DMA, dma_interrupt_handler, IRQF_DISABLED,
"MCD-DMA", NULL)) {
printk(KERN_ERR "MCD-DMA: Cannot allocate the DMA IRQ(48)\n");
return 1;
}
MCF_DMA_DIMR = 0;
MCF_DMA_DIPR = 0xFFFFFFFF;
MCF_ICR(ISC_DMA) = ILP_DMA;
result = MCD_initDma((dmaRegs *) (MCF_MBAR + 0x8000),
(void *) SYS_SRAM_DMA_START, MCD_RELOC_TASKS);
if (result != MCD_OK) {
printk(KERN_ERR "MCD-DMA: Cannot perform DMA initialization\n");
free_irq(64 + ISC_DMA, NULL);
return 1;
}
return 0;
}
device_initcall(dma_init);

143
target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/mcf548x-devices.c
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/*
* arch/m68k/coldfire/m547x/mcf548x-devices.c
*
* Coldfire M548x Platform Device Configuration
*
* Based on the Freescale MXC devices.c
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* Kurt Mahan <kmahan@freescale.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
static struct resource coldfire_i2c_resources[] = {
{ /* I/O */
.start = MCF_MBAR + 0x008F00,
.end = MCF_MBAR + 0x008F20,
.flags = IORESOURCE_MEM,
},
{ /* IRQ */
.start = 40,
.end = 40,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device coldfire_i2c_device = {
.name = "mcf-i2c",
.id = 0, /*bus number*/
.num_resources = ARRAY_SIZE(coldfire_i2c_resources),
.resource = coldfire_i2c_resources,
};
static struct resource coldfire_sec_resources[] = {
[0] = { /* I/O */
.start = MCF_MBAR + 0x00020000,
.end = MCF_MBAR + 0x00033000,
.flags = IORESOURCE_MEM,
},
[2] = { /* IRQ */
.start = ISC_SEC,
.end = ISC_SEC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device coldfire_sec_device = {
.name = "fsl-sec1",
.id = -1,
.num_resources = ARRAY_SIZE(coldfire_sec_resources),
.resource = coldfire_sec_resources,
};
static struct physmap_flash_data mcf5485_flash_data = {
.width = 2,
};
static struct resource mcf5485_flash_resource = {
.start = 0xff800000,
.end = 0xffbfffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device mcf5485_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &mcf5485_flash_data,
},
.num_resources = 1,
.resource = &mcf5485_flash_resource,
};
static int __init mcf5485_init_devices(void)
{
printk(KERN_INFO "MCF5485x INIT_DEVICES\n");
platform_device_register(&coldfire_i2c_device);
platform_device_register(&coldfire_sec_device);
platform_device_register(&mcf5485_flash_device);
return 0;
}
arch_initcall(mcf5485_init_devices);
static struct mcf_platform_uart m548x_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.irq = MCFINT_VECBASE + MCFINT_UART0,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.irq = MCFINT_VECBASE + MCFINT_UART1,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE3,
.irq = MCFINT_VECBASE + MCFINT_UART2,
},
{ },
};
static struct platform_device m548x_uart = {
.name = "mcfuart",
.id = 0,
.dev.platform_data = m548x_uart_platform,
};
static struct platform_device *m548x_devices[] __initdata = {
&m548x_uart,
};
void m548x_uarts_init(void)
{
const int nrlines = ARRAY_SIZE(m548x_uart_platform);
int line;
/* Set GPIO port register to enable PSC(port) signals */
for (line = 0; (line < nrlines); line++) {
MCF_PAR_PSCn(line) = (0
| MCF_PAR_PSC_TXD
| MCF_PAR_PSC_RXD);
MCF_ICR(m548x_uart_platform[line].irq - 64) = ILP_PSCn(line);
}
}
/***************************************************************************/
static int __init init_BSP(void)
{
m548x_uarts_init();
platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
return 0;
}
arch_initcall(init_BSP);

432
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/MCD_dma.h
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@ -1,432 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2004 Motorola, Inc.
* MOTOROLA, INC. All Rights Reserved.
* Copyright 2009 Freescale Semiconductor, Inc.
* Shrek Wu b16972@freescale.com
*
* You are hereby granted a copyright license to use
* the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Motorola, Inc. This
* software is provided on an "AS IS" basis and without warranty.
*
* To the maximum extent permitted by applicable law, MOTOROLA
* DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
* PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
* SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
* ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
* INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
* LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Motorola assumes no responsibility for the maintenance and support
* of this software
********************************************************************/
/*
* File: MCD_dma.h
* Purpose: Main header file for multi-channel DMA API.
*
* Notes:
*
* Modifications:
*/
#ifndef _MCD_API_H
#define _MCD_API_H
#include <asm/types.h>
/*
* Turn Execution Unit tasks ON (#define) or OFF (#undef)
*/
#undef MCD_INCLUDE_EU
/*
* Number of DMA channels
*/
#define NCHANNELS 16
/*
* Total number of variants
*/
#ifdef MCD_INCLUDE_EU
#define NUMOFVARIANTS 6
#else
#define NUMOFVARIANTS 4
#endif
/*
* Define sizes of the various tables
*/
#define TASK_TABLE_SIZE (NCHANNELS*32)
#define VAR_TAB_SIZE (128)
#define CONTEXT_SAVE_SIZE (128)
#define FUNCDESC_TAB_SIZE (256)
#ifdef MCD_INCLUDE_EU
#define FUNCDESC_TAB_NUM 16
#else
#define FUNCDESC_TAB_NUM 1
#endif
#ifndef DEFINESONLY
/*
* Portability typedefs
*/
/*
#ifndef s32
typedef int s32;
#endif
#ifndef u32
typedef unsigned int u32;
#endif
#ifndef s16
typedef short s16;
#endif
#ifndef u16
typedef unsigned short u16;
#endif
#ifndef s8
typedef char s8;
#endif
#ifndef u8
typedef unsigned char u8;
#endif
*/
/*
* These structures represent the internal registers of the
* multi-channel DMA
*/
struct dmaRegs_s {
u32 taskbar; /* task table base address register */
u32 currPtr;
u32 endPtr;
u32 varTablePtr;
u16 dma_rsvd0;
u16 ptdControl; /* ptd control */
u32 intPending; /* interrupt pending register */
u32 intMask; /* interrupt mask register */
u16 taskControl[16]; /* task control registers */
u8 priority[32]; /* priority registers */
u32 initiatorMux; /* initiator mux control */
u32 taskSize0; /* task size control register 0. */
u32 taskSize1; /* task size control register 1. */
u32 dma_rsvd1; /* reserved */
u32 dma_rsvd2; /* reserved */
u32 debugComp1; /* debug comparator 1 */
u32 debugComp2; /* debug comparator 2 */
u32 debugControl; /* debug control */
u32 debugStatus; /* debug status */
u32 ptdDebug; /* priority task decode debug */
u32 dma_rsvd3[31]; /* reserved */
};
typedef volatile struct dmaRegs_s dmaRegs;
#endif
/*
* PTD contrl reg bits
*/
#define PTD_CTL_TSK_PRI 0x8000
#define PTD_CTL_COMM_PREFETCH 0x0001
/*
* Task Control reg bits and field masks
*/
#define TASK_CTL_EN 0x8000
#define TASK_CTL_VALID 0x4000
#define TASK_CTL_ALWAYS 0x2000
#define TASK_CTL_INIT_MASK 0x1f00
#define TASK_CTL_ASTRT 0x0080
#define TASK_CTL_HIPRITSKEN 0x0040
#define TASK_CTL_HLDINITNUM 0x0020
#define TASK_CTL_ASTSKNUM_MASK 0x000f
/*
* Priority reg bits and field masks
*/
#define PRIORITY_HLD 0x80
#define PRIORITY_PRI_MASK 0x07
/*
* Debug Control reg bits and field masks
*/
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
#define DBG_CTL_AUTO_ARM 0x00008000
#define DBG_CTL_BREAK 0x00004000
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
#define DBG_CTL_EXT_BREAK 0x00000004
#define DBG_CTL_INT_BREAK 0x00000002
/*
* PTD Debug reg selector addresses
* This reg must be written with a value to show the contents of
* one of the desired internal register.
*/
#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
have initiators asserted */
/*
* General return values
*/
#define MCD_OK 0
#define MCD_ERROR -1
#define MCD_TABLE_UNALIGNED -2
#define MCD_CHANNEL_INVALID -3
/*
* MCD_initDma input flags
*/
#define MCD_RELOC_TASKS 0x00000001
#define MCD_NO_RELOC_TASKS 0x00000000
#define MCD_COMM_PREFETCH_EN 0x00000002
/* Commbus Prefetching - MCF547x/548x ONLY */
/*
* MCD_dmaStatus Status Values for each channel
*/
#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
#define MCD_PAUSED 4 /* DMA active but it is currently paused */
#define MCD_HALTED 5
/* the most recent DMA has been killed with MCD_killTask() */
#define MCD_DONE 6 /* the most recent DMA has completed. */
/*
* MCD_startDma parameter defines
*/
/*
* Constants for the funcDesc parameter
*/
/* Byte swapping: */
#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
#define MCD_BYTE_REVERSE 0x00076540
/* to reverse the bytes of each u32 of the DMAed data. */
#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
each 32-bit data value being DMAed.*/
#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
16-bit half of each 32-bit data value DMAed */
#define MCD_NO_BIT_REV 0x00000000
/* do not reverse the bits of each byte DMAed. */
#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
/* CRCing: */
#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
#define MCD_CSUMINET 0xc0400000
/* to perform internet checksums on DMAed data.*/
#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
/*
* Constants for the flags parameter
*/
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
#define MCD_TT_FLAGS_SP 0x00000004
/* Speculative prefetch(XLB) MCF547x/548x ONLY */
#define MCD_TT_FLAGS_MASK 0x000000ff
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
#define MCD_CHAIN_DMA /* TBD */
#define MCD_EU_DMA /* TBD */
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
/* these flags are valid for MCD_startDma and the chained buffer descriptors */
#define MCD_BUF_READY 0x80000000
/* indicates that this buffer is now under the DMA's control */
#define MCD_WRAP 0x20000000
/* to tell the FEC Dmas to wrap to the first BD */
#define MCD_INTERRUPT 0x10000000
/* to generate an interrupt after completion of the DMA. */
#define MCD_END_FRAME 0x08000000
/* tell the DMA to end the frame when transferring
last byte of data in buffer */
#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
prior to performing the DMA. */
/* Defines for the FEC buffer descriptor control/status word*/
#define MCD_FEC_BUF_READY 0x8000
#define MCD_FEC_WRAP 0x2000
#define MCD_FEC_INTERRUPT 0x1000
#define MCD_FEC_END_FRAME 0x0800
/*
* Defines for general intuitiveness
*/
#define MCD_TRUE 1
#define MCD_FALSE 0
/*
* Three different cases for destination and source.
*/
#define MINUS1 -1
#define ZERO 0
#define PLUS1 1
#ifndef DEFINESONLY
/* Task Table Entry struct*/
typedef struct {
u32 TDTstart; /* task descriptor table start */
u32 TDTend; /* task descriptor table end */
u32 varTab; /* variable table start */
u32 FDTandFlags; /* function descriptor table start and flags */
volatile u32 descAddrAndStatus;
volatile u32 modifiedVarTab;
u32 contextSaveSpace; /* context save space start */
u32 literalBases;
} TaskTableEntry;
/* Chained buffer descriptor */
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
u32 flags; /* flags describing the DMA */
u32 csumResult;
/* checksum from checksumming performed since last checksum reset */
s8 *srcAddr; /* the address to move data from */
s8 *destAddr; /* the address to move data to */
s8 *lastDestAddr; /* the last address written to */
u32 dmaSize;
/* the number of bytes to transfer independent of the transfer size */
MCD_bufDesc *next; /* next buffer descriptor in chain */
u32 info;
/* private information about this descriptor; DMA does not affect it */
};
/* Progress Query struct */
typedef volatile struct MCD_XferProg_struct {
s8 *lastSrcAddr;
/* the most-recent or last, post-increment source address */
s8 *lastDestAddr;
/* the most-recent or last, post-increment destination address */
u32 dmaSize;
/* the amount of data transferred for the current buffer */
MCD_bufDesc *currBufDesc;
/* pointer to the current buffer descriptor being DMAed */
} MCD_XferProg;
/* FEC buffer descriptor */
typedef volatile struct MCD_bufDescFec_struct {
u16 statCtrl;
u16 length;
u32 dataPointer;
} MCD_bufDescFec;
/*************************************************************************/
/*
* API function Prototypes - see MCD_dmaApi.c for further notes
*/
/*
* MCD_startDma starts a particular kind of DMA .
*/
int MCD_startDma(
int channel, /* the channel on which to run the DMA */
s8 *srcAddr,
/* the address to move data from, or buffer-descriptor address */
s16 srcIncr, /* the amount to increment the source address per transfer */
s8 *destAddr, /* the address to move data to */
s16 destIncr,
/* the amount to increment the destination address per transfer */
u32 dmaSize,
/* the number of bytes to transfer independent of the transfer size */
u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
u32 initiator, /* what device initiates the DMA */
int priority, /* priority of the DMA */
u32 flags, /* flags describing the DMA */
u32 funcDesc
/* a description of byte swapping, bit swapping, and CRC actions */
);
/*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and
* setting up some global settings
*/
int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
/*
* MCD_dmaStatus() returns the status of the DMA on the requested channel.
*/
int MCD_dmaStatus(int channel);
/*
* MCD_XferProgrQuery() returns progress of DMA on requested channel
*/
int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep);
/*
* MCD_killDma() halts the DMA on the requested channel, without any
* intention of resuming the DMA.
*/
int MCD_killDma(int channel);
/*
* MCD_continDma() continues a DMA which as stopped due to encountering an
* unready buffer descriptor.
*/
int MCD_continDma(int channel);
/*
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
* running on that channel).
*/
int MCD_pauseDma(int channel);
/*
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
* running on that channel).
*/
int MCD_resumeDma(int channel);
/*
* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
*/
int MCD_csumQuery(int channel, u32 *csum);
/*
* MCD_getCodeSize provides the packed size required by the microcoded task
* and structures.
*/
int MCD_getCodeSize(void);
/*
* MCD_getVersion provides a pointer to a version string and returns a
* version number.
*/
int MCD_getVersion(char **longVersion);
/* macro for setting a location in the variable table */
#define MCD_SET_VAR(taskTab, idx, value) ((u32 *)(taskTab)->varTab)[idx] = value
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
so I'm avoiding surrounding it with "do {} while(0)" */
#endif /* DEFINESONLY */
#endif /* _MCD_API_H */

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target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/asm-offsets.h
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@ -1,73 +0,0 @@
#ifndef __ASM_OFFSETS_H__
#define __ASM_OFFSETS_H__
/*
* DO NOT MODIFY.
*
* This file was generated by Kbuild
*
*/
#define TASK_STATE 0 /* offsetof(struct task_struct, state) | */
#define TASK_FLAGS 12 /* offsetof(struct task_struct, flags) | */
#define TASK_PTRACE 16 /* offsetof(struct task_struct, ptrace) | */
#define TASK_THREAD 476 /* offsetof(struct task_struct, thread) | */
#define TASK_INFO 638 /* offsetof(struct task_struct, thread.info) | */
#define TASK_MM 178 /* offsetof(struct task_struct, mm) | */
#define TASK_ACTIVE_MM 182 /* offsetof(struct task_struct, active_mm) | */
#define THREAD_KSP 0 /* offsetof(struct thread_struct, ksp) | */
#define THREAD_USP 4 /* offsetof(struct thread_struct, usp) | */
#define THREAD_SR 8 /* offsetof(struct thread_struct, sr) | */
#define THREAD_FS 10 /* offsetof(struct thread_struct, fs) | */
#define THREAD_CRP 14 /* offsetof(struct thread_struct, crp) | */
#define THREAD_ESP0 22 /* offsetof(struct thread_struct, esp0) | */
#define THREAD_FPREG 38 /* offsetof(struct thread_struct, fp) | */
#define THREAD_FPCNTL 134 /* offsetof(struct thread_struct, fpcntl) | */
#define THREAD_FPSTATE 146 /* offsetof(struct thread_struct, fpstate) | */
#define TINFO_PREEMPT 12 /* offsetof(struct thread_info, preempt_count) | */
#define TINFO_FLAGS 4 /* offsetof(struct thread_info, flags) | */
#define PT_D0 32 /* offsetof(struct pt_regs, d0) | */
#define PT_ORIG_D0 36 /* offsetof(struct pt_regs, orig_d0) | */
#define PT_D1 0 /* offsetof(struct pt_regs, d1) | */
#define PT_D2 4 /* offsetof(struct pt_regs, d2) | */
#define PT_D3 8 /* offsetof(struct pt_regs, d3) | */
#define PT_D4 12 /* offsetof(struct pt_regs, d4) | */
#define PT_D5 16 /* offsetof(struct pt_regs, d5) | */
#define PT_A0 20 /* offsetof(struct pt_regs, a0) | */
#define PT_A1 24 /* offsetof(struct pt_regs, a1) | */
#define PT_A2 28 /* offsetof(struct pt_regs, a2) | */
#define PT_PC 56 /* offsetof(struct pt_regs, pc) | */
#define PT_SR 54 /* offsetof(struct pt_regs, sr) | */
#define MM_CONTEXT 328 /* offsetof(struct mm_struct, context) | */
#define PT_VECTOR 52 /* offsetof(struct pt_regs, pc) - 4 | */
#define IRQ_HANDLER 0 /* offsetof(struct irq_node, handler) | */
#define IRQ_DEVID 4 /* offsetof(struct irq_node, dev_id) | */
#define IRQ_NEXT 8 /* offsetof(struct irq_node, next) | */
#define STAT_IRQ 72 /* offsetof(struct kernel_stat, irqs) | */
#define CPUSTAT_SOFTIRQ_PENDING 0 /* offsetof(irq_cpustat_t, __softirq_pending) | */
#define BIR_TAG 0 /* offsetof(struct bi_record, tag) | */
#define BIR_SIZE 2 /* offsetof(struct bi_record, size) | */
#define BIR_DATA 4 /* offsetof(struct bi_record, data) | */
#define FONT_DESC_IDX 0 /* offsetof(struct font_desc, idx) | */
#define FONT_DESC_NAME 4 /* offsetof(struct font_desc, name) | */
#define FONT_DESC_WIDTH 8 /* offsetof(struct font_desc, width) | */
#define FONT_DESC_HEIGHT 12 /* offsetof(struct font_desc, height) | */
#define FONT_DESC_DATA 16 /* offsetof(struct font_desc, data) | */
#define FONT_DESC_PREF 20 /* offsetof(struct font_desc, pref) | */
#define SIGSEGV 11 /* SIGSEGV | */
#define SEGV_MAPERR 196609 /* SEGV_MAPERR | */
#define SIGTRAP 5 /* SIGTRAP | */
#define TRAP_TRACE 196610 /* TRAP_TRACE | */
#define CUSTOMBASE -2132807680 /* &amiga_custom | */
#define C_INTENAR 28 /* offsetof(struct CUSTOM, intenar) | */
#define C_INTREQR 30 /* offsetof(struct CUSTOM, intreqr) | */
#define C_INTENA 154 /* offsetof(struct CUSTOM, intena) | */
#define C_INTREQ 156 /* offsetof(struct CUSTOM, intreq) | */
#define C_SERDATR 24 /* offsetof(struct CUSTOM, serdatr) | */
#define C_SERDAT 48 /* offsetof(struct CUSTOM, serdat) | */
#define C_SERPER 50 /* offsetof(struct CUSTOM, serper) | */
#define CIAABASE -2134908927 /* &ciaa | */
#define CIABBASE -2134913024 /* &ciab | */
#define C_PRA 0 /* offsetof(struct CIA, pra) | */
#define ZTWOBASE -2147483648 /* zTwoBase | */
#endif

262
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_548x_cacheflush.h
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/*
* arch/m68k/include/asm/cf_548x_cacheflush.h - Coldfire 547x/548x Cache
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Kurt Mahan kmahan@freescale.com
* Shrek Wu b16972@freescale.com
*
* Based on include/asm-m68k/cacheflush.h
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef M68K_CF_548x_CACHEFLUSH_H
#define M68K_CF_548x_CACHEFLUSH_H
#include <asm/cfcache.h>
/*
* Cache handling functions
*/
#define flush_icache() \
({ \
unsigned long set; \
unsigned long start_set; \
unsigned long end_set; \
\
start_set = 0; \
end_set = (unsigned long)LAST_DCACHE_ADDR; \
\
for (set = start_set; set <= end_set; set += (0x10 - 3)) {\
asm volatile("cpushl %%ic,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%ic,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%ic,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \
} \
})
#define flush_dcache() \
({ \
unsigned long set; \
unsigned long start_set; \
unsigned long end_set; \
\
start_set = 0; \
end_set = (unsigned long)LAST_DCACHE_ADDR; \
\
for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
asm volatile("cpushl %%dc,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%dc,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%dc,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \
} \
})
#define flush_bcache() \
({ \
unsigned long set; \
unsigned long start_set; \
unsigned long end_set; \
\
start_set = 0; \
end_set = (unsigned long)LAST_DCACHE_ADDR; \
\
for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
asm volatile("cpushl %%bc,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%bc,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%bc,(%0)\n" \
"\taddq%.l #1,%0\n" \
"\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \
} \
})
/*
* invalidate the cache for the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_clear(unsigned long paddr, int len);
/*
* push any dirty cache in the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_push(unsigned long paddr, int len);
/*
* push and invalidate pages in the specified user virtual
* memory range.
*/
extern void cache_push_v(unsigned long vaddr, int len);
/* This is needed whenever the virtual mapping of the current
process changes. */
/**
* flush_cache_mm - Flush an mm_struct
* @mm: mm_struct to flush
*/
static inline void flush_cache_mm(struct mm_struct *mm)
{
if (mm == current->mm)
flush_bcache();
}
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
#define flush_cache_all() flush_bcache()
/**
* flush_cache_range - Flush a cache range
* @vma: vma struct
* @start: Starting address
* @end: Ending address
*
* flush_cache_range must be a macro to avoid a dependency on
* linux/mm.h which includes this file.
*/
static inline void flush_cache_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
if (vma->vm_mm == current->mm)
flush_bcache();
/*cf_cache_flush_range(start, end);*/
}
/**
* flush_cache_page - Flush a page of the cache
* @vma: vma struct
* @vmaddr:
* @pfn: page numer
*
* flush_cache_page must be a macro to avoid a dependency on
* linux/mm.h which includes this file.
*/
static inline void flush_cache_page(struct vm_area_struct *vma,
unsigned long vmaddr, unsigned long pfn)
{
if (vma->vm_mm == current->mm)
flush_bcache();
/*cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);*/
}
/* Push the page at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
extern inline void __flush_page_to_ram(void *address)
{
unsigned long set;
unsigned long start_set;
unsigned long end_set;
unsigned long addr = (unsigned long) address;
addr &= ~(PAGE_SIZE - 1);
/* round down to page start address */
start_set = addr & _ICACHE_SET_MASK;
end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3)) {
asm volatile("cpushl %%bc,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%bc,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%bc,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_ICACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3)) {
asm volatile("cpushl %%bc,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%bc,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%bc,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
}
}
/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */
#define flush_dcache_page(page) \
__flush_page_to_ram((void *) page_address(page))
#define flush_icache_page(vma, pg) \
__flush_page_to_ram((void *) page_address(pg))
#define flush_icache_user_range(adr, len) \
do { } while (0)
/* NL */
#define flush_icache_user_page(vma, page, addr, len) \
do { } while (0)
/* Push n pages at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
extern inline void flush_icache_range(unsigned long address,
unsigned long endaddr)
{
unsigned long set;
unsigned long start_set;
unsigned long end_set;
start_set = address & _ICACHE_SET_MASK;
end_set = endaddr & _ICACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3)) {
asm volatile("cpushl %%ic,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%ic,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%ic,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_ICACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3)) {
asm volatile("cpushl %%ic,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%ic,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%ic,(%0)\n"
"\taddq%.l #1,%0\n"
"\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
}
}
static inline void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
memcpy(dst, src, len);
flush_icache_user_page(vma, page, vaddr, len);
}
static inline void copy_from_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
memcpy(dst, src, len);
}
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#endif /* M68K_CF_548x_CACHEFLUSH_H */

443
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_bitops.h
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@ -1,443 +0,0 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef __CF_BITOPS__
#define __CF_BITOPS__
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <linux/compiler.h>
#define test_and_set_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_coldfire_test_and_set_bit(nr, vaddr) : \
__generic_coldfire_test_and_set_bit(nr, vaddr))
static __inline__ int __constant_coldfire_test_and_set_bit(int nr,
volatile void *vaddr)
{
char retval;
volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
__asm__ __volatile__ ("bset %2,(%4); sne %0"
: "=d" (retval), "=m" (*p)
: "di" (nr & 7), "m" (*p), "a" (p));
return retval;
}
static __inline__ int __generic_coldfire_test_and_set_bit(int nr,
volatile void *vaddr)
{
char retval;
__asm__ __volatile__ ("bset %2,%1; sne %0"
: "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
: "d" (nr)
: "memory");
return retval;
}
#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr)
#define set_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_coldfire_set_bit(nr, vaddr) : \
__generic_coldfire_set_bit(nr, vaddr))
static __inline__ void __constant_coldfire_set_bit(int nr,
volatile void *vaddr)
{
volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
__asm__ __volatile__ ("bset %1,(%3)"
: "=m" (*p) : "di" (nr & 7), "m" (*p), "a" (p));
}
static __inline__ void __generic_coldfire_set_bit(int nr,
volatile void *vaddr)
{
__asm__ __volatile__ ("bset %1,%0"
: "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
: "d" (nr)
: "memory");
}
#define __set_bit(nr, vaddr) set_bit(nr, vaddr)
#define test_and_clear_bit(nr, vaddr) \
(__builtin_constant_p(nr) ? \
__constant_coldfire_test_and_clear_bit(nr, vaddr) : \
__generic_coldfire_test_and_clear_bit(nr, vaddr))
static __inline__ int __constant_coldfire_test_and_clear_bit(int nr,
volatile void *vaddr)
{
char retval;
volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
__asm__ __volatile__ ("bclr %2,(%4); sne %0"
: "=d" (retval), "=m" (*p)
: "id" (nr & 7), "m" (*p), "a" (p));
return retval;
}
static __inline__ int __generic_coldfire_test_and_clear_bit(int nr,
volatile void *vaddr)
{
char retval;
__asm__ __volatile__ ("bclr %2,%1; sne %0"
: "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
: "d" (nr & 7)
: "memory");
return retval;
}
#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr)
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
#define clear_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_coldfire_clear_bit(nr, vaddr) : \
__generic_coldfire_clear_bit(nr, vaddr))
static __inline__ void __constant_coldfire_clear_bit(int nr,
volatile void *vaddr)
{
volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
__asm__ __volatile__ ("bclr %1,(%3)"
: "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p));
}
static __inline__ void __generic_coldfire_clear_bit(int nr,
volatile void *vaddr)
{
__asm__ __volatile__ ("bclr %1,%0"
: "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
: "d" (nr)
: "memory");
}
#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr)
#define test_and_change_bit(nr, vaddr) \
(__builtin_constant_p(nr) ? \
__constant_coldfire_test_and_change_bit(nr, vaddr) : \
__generic_coldfire_test_and_change_bit(nr, vaddr))
static __inline__ int __constant_coldfire_test_and_change_bit(int nr,
volatile void *vaddr)
{
char retval;
volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
__asm__ __volatile__ ("bchg %2,(%4); sne %0"
: "=d" (retval), "=m" (*p)
: "id" (nr & 7), "m" (*p), "a" (p));
return retval;
}
static __inline__ int __generic_coldfire_test_and_change_bit(int nr,
volatile void *vaddr)
{
char retval;
__asm__ __volatile__ ("bchg %2,%1; sne %0"
: "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
: "id" (nr)
: "memory");
return retval;
}
#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)
#define __change_bit(nr, vaddr) change_bit(nr, vaddr)
#define change_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_coldfire_change_bit(nr, vaddr) : \
__generic_coldfire_change_bit(nr, vaddr))
static __inline__ void __constant_coldfire_change_bit(int nr,
volatile void *vaddr)
{
volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
__asm__ __volatile__ ("bchg %1,(%3)"
: "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p));
}
static __inline__ void __generic_coldfire_change_bit(int nr,
volatile void *vaddr)
{
__asm__ __volatile__ ("bchg %1,%0"
: "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
: "d" (nr)
: "memory");
}
static inline int test_bit(int nr, const unsigned long *vaddr)
{
return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
}
static __inline__ unsigned long ffz(unsigned long word)
{
unsigned long result = 0;
while (word & 1) {
result++;
word >>= 1;
}
return result;
}
/* find_next_zero_bit() finds the first zero bit in a bit string of length
* 'size' bits, starting the search at bit 'offset'. This is largely based
* on Linus's ALPHA routines.
*/
static __inline__ unsigned long find_next_zero_bit(void *addr,
unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size & ~31UL) {
tmp = *(p++);
if (~tmp)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp |= ~0UL >> size;
found_middle:
return result + ffz(tmp);
}
#define find_first_zero_bit(addr, size) find_next_zero_bit(((void *)addr), \
(size), 0)
/* Ported from included/linux/bitops.h */
static __inline__ int ffs(int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
#define __ffs(x) (ffs(x) - 1)
/* find_next_bit - find the next set bit in a memory region
* (from asm-ppc/bitops.h)
*/
static __inline__ unsigned long find_next_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *p++;
tmp &= ~0UL << offset;
if (size < 32)
goto found_first;
if (tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size >= 32) {
tmp = *p++;
if (tmp != 0)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp &= ~0UL >> (32 - size);
if (tmp == 0UL) /* Are any bits set? */
return result + size; /* Nope. */
found_middle:
return result + __ffs(tmp);
}
#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
#ifdef __KERNEL__
/* Ported from include/linux/bitops.h */
static __inline__ int fls(int x)
{
int r = 32;
if (!x)
return 0;
if (!(x & 0xffff0000u)) {
x <<= 16;
r -= 16;
}
if (!(x & 0xff000000u)) {
x <<= 8;
r -= 8;
}
if (!(x & 0xf0000000u)) {
x <<= 4;
r -= 4;
}
if (!(x & 0xc0000000u)) {
x <<= 2;
r -= 2;
}
if (!(x & 0x80000000u)) {
x <<= 1;
r -= 1;
}
return r;
}
static inline int __fls(int x)
{
return fls(x) - 1;
}
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#define minix_find_first_zero_bit(addr, size) find_next_zero_bit((addr), \
(size), 0)
#define minix_test_and_set_bit(nr, addr) test_and_set_bit((nr), \
(unsigned long *)(addr))
#define minix_set_bit(nr, addr) set_bit((nr), \
(unsigned long *)(addr))
#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit((nr), \
(unsigned long *)(addr))
static inline int minix_test_bit(int nr, const volatile unsigned long *vaddr)
{
int *a = (int *)vaddr;
int mask;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
return ((mask & *a) != 0);
}
#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 24, \
(unsigned long *)(addr))
#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, \
(unsigned long *)(addr))
#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 24, \
(unsigned long *)(addr))
#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, \
(unsigned long *)(addr))
static inline int ext2_test_bit(int nr, const void *vaddr)
{
const unsigned char *p = vaddr;
return (p[nr >> 3] & (1U << (nr & 7))) != 0;
}
static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
{
const unsigned long *p = vaddr, *addr = vaddr;
int res;
if (!size)
return 0;
size = (size >> 5) + ((size & 31) > 0);
while (*p++ == ~0UL) {
if (--size == 0)
return (p - addr) << 5;
}
--p;
for (res = 0; res < 32; res++)
if (!ext2_test_bit (res, p))
break;
return (p - addr) * 32 + res;
}
static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
unsigned offset)
{
const unsigned long *addr = vaddr;
const unsigned long *p = addr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
/* Look for zero in first longword */
for (res = bit; res < 32; res++)
if (!ext2_test_bit (res, p))
return (p - addr) * 32 + res;
p++;
}
/* No zero yet, search remaining full bytes for a zero */
res = ext2_find_first_zero_bit(p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
#endif /* KERNEL */
#endif /* __CF_BITOPS__ */

10
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_cacheflush.h
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@ -1,10 +0,0 @@
#ifndef M68K_CF_CACHEFLUSH_H
#define M68K_CF_CACHEFLUSH_H
#ifdef CONFIG_M5445X
#include "cf_5445x_cacheflush.h"
#else
#include "cf_548x_cacheflush.h"
#endif
#endif /* M68K_CF_CACHEFLUSH_H */

146
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_entry.h
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#ifndef __CF_M68K_ENTRY_H
#define __CF_M68K_ENTRY_H
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/coldfire.h>
#include <asm/cfmmu.h>
#include <asm/asm-offsets.h>
/*
* Stack layout in 'ret_from_exception':
*
* This allows access to the syscall arguments in registers d1-d5
*
* 0(sp) - d1
* 4(sp) - d2
* 8(sp) - d3
* C(sp) - d4
* 10(sp) - d5
* 14(sp) - a0
* 18(sp) - a1
* 1C(sp) - a2
* 20(sp) - d0
* 24(sp) - orig_d0
* 28(sp) - stack adjustment
* 2C(sp) - sr
* 2E(sp) - pc
* 32(sp) - format & vector
* 36(sp) - MMUSR
* 3A(sp) - MMUAR
*/
/*
* 97/05/14 Andreas: Register %a2 is now set to the current task throughout
* the whole kernel.
*/
/* the following macro is used when enabling interrupts */
/* portable version */
#define ALLOWINT (~0x700)
#define MAX_NOINT_IPL 0
#ifdef __ASSEMBLY__
#define curptr a2
LFLUSH_I_AND_D = 0x00000808
LSIGTRAP = 5
/* process bits for task_struct.ptrace */
PT_TRACESYS_OFF = 3
PT_TRACESYS_BIT = 1
PT_PTRACED_OFF = 3
PT_PTRACED_BIT = 0
PT_DTRACE_OFF = 3
PT_DTRACE_BIT = 2
#define SAVE_ALL_INT save_all_int
#define SAVE_ALL_SYS save_all_sys
#define RESTORE_ALL restore_all
/*
* This defines the normal kernel pt-regs layout.
*
* regs a3-a6 and d6-d7 are preserved by C code
* the kernel doesn't mess with usp unless it needs to
*/
/*
* a -1 in the orig_d0 field signifies
* that the stack frame is NOT for syscall
*/
.macro save_all_int
movel MMUSR,%sp@-
movel MMUAR,%sp@-
clrl %sp@- | stk_adj
pea -1:w | orig d0
movel %d0,%sp@- | d0
subal #(8*4), %sp
moveml %d1-%d5/%a0-%a1/%curptr,%sp@
.endm
.macro save_all_sys
movel MMUSR,%sp@-
movel MMUAR,%sp@-
clrl %sp@- | stk_adj
movel %d0,%sp@- | orig d0
movel %d0,%sp@- | d0
subal #(8*4), %sp
moveml %d1-%d5/%a0-%a1/%curptr,%sp@
.endm
.macro restore_all
moveml %sp@,%a0-%a1/%curptr/%d1-%d5
addal #(8*4), %sp
movel %sp@+,%d0 | d0
addql #4,%sp | orig d0
addl %sp@+,%sp | stk_adj
addql #8,%sp | MMUAR & MMUSR
rte
.endm
#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
#define SAVE_SWITCH_STACK save_switch_stack
#define RESTORE_SWITCH_STACK restore_switch_stack
#define GET_CURRENT(tmp) get_current tmp
.macro save_switch_stack
subal #(6*4), %sp
moveml %a3-%a6/%d6-%d7,%sp@
.endm
.macro restore_switch_stack
moveml %sp@,%a3-%a6/%d6-%d7
addal #(6*4), %sp
.endm
.macro get_current reg=%d0
movel %sp,\reg
andl #-THREAD_SIZE,\reg
movel \reg,%curptr
movel %curptr@,%curptr
.endm
#else /* C source */
#define STR(X) STR1(X)
#define STR1(X) #X
#define PT_OFF_ORIG_D0 0x24
#define PT_OFF_FORMATVEC 0x32
#define PT_OFF_SR 0x2C
#define SAVE_ALL_INT \
"clrl %%sp@-;" /* stk_adj */ \
"pea -1:w;" /* orig d0 = -1 */ \
"movel %%d0,%%sp@-;" /* d0 */ \
"subal #(8*4),%sp" \
"moveml %%d1-%%d5/%%a0-%%a2,%%sp@"
#define GET_CURRENT(tmp) \
"movel %%sp,"#tmp"\n\t" \
"andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
"movel "#tmp",%%a2\n\t"
#endif
#endif /* __CF_M68K_ENTRY_H */

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/*
* linux/include/asm-m68k/cf_io.h
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* 9/30/08 JKM - Separated Coldfire pieces out from m68k.
*/
#ifndef __CF_IO__
#define __CF_IO__
#ifdef __KERNEL__
#include <linux/compiler.h>
#include <asm/raw_io.h>
#include <asm/virtconvert.h>
#include <asm-generic/iomap.h>
/*
* These should be valid on any ioremap()ed region
*/
#define readb(addr) in_8(addr)
#define writeb(val,addr) out_8((addr),(val))
#define readw(addr) in_le16(addr)
#define writew(val,addr) out_le16((addr),(val))
#define readl(addr) in_le32(addr)
#define writel(val,addr) out_le32((addr),(val))
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#ifdef CONFIG_PCI
/*
* IO space in Coldfire
*/
/*#define HAVE_ARCH_PIO_SIZE 1
#define PIO_OFFSET 0x00000000UL
#define PIO_RESERVED 0x100000000UL
#define PIO_MASK (PIO_RESERVED - 1)
*/
#define inb_p inb
#define inw_p inw
#define inl_p inl
#define outb_p outb
#define outw_p outw
#define outl_p outl
#ifndef CONFIG_COLDFIRE
#define inb(port) in_8(port)
#define outb(val,port) out_8((port),(val))
#define inw(port) in_le16(port)
#define outw(val,port) out_le16((port),(val))
#define inl(port) in_le32(port)
#define outl(val,port) out_le32((port),(val))
#define insb(port, buf, nr) \
raw_insb((u8 *)(port), (u8 *)(buf), (nr))
#define outsb(port, buf, nr) \
raw_outsb((u8 *)(port), (u8 *)(buf), (nr))
#define insw(port, buf, nr) \
raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr))
#define outsw(port, buf, nr) \
raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr))
#define insl(port, buf, nr) \
raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1)
#define outsl(port, buf, nr) \
raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1)
#else
#define inb(port) pci_inb(port)
#define outb(val, port) pci_outb((val), (port))
#define inw(port) pci_inw(port)
#define outw(val, port) pci_outw((val), (port))
#define insb(a, b, c) \
pci_insb((volatile unsigned char *)a, (unsigned char *)b, c)
#define insw(a, b, c) \
pci_insw((volatile unsigned short *)a, (const unsigned short *)b, c)
#define insl(a, b, c) \
pci_insl((volatile unsigned long *)a, (const unsigned long *)b, c)
#define outsb(a, b, c) \
pci_outsb((volatile unsigned char *)a, (const unsigned char *)b, c)
#define outsw(a, b, c) \
pci_outsw((volatile unsigned short *)a, (const unsigned short *)b, c)
#define outsl(a, b, c) \
pci_outsl((volatile unsigned long *)a, (const unsigned long *)b, c)
#define inl(port) pci_inl(port)
#define outl(val, port) pci_outl((val), (port))
#endif
#else
/* no pci */
#define inb(port) in_8(port)
#define outb(val, port) out_8((port), (val))
#define inw(port) in_le16(port)
#define outw(val, port) out_le16((port), (val))
#define inl(port) in_le32(port)
#define outl(val, port) out_le32((port), (val))
#define insb(port, buf, nr) \
raw_insb((u8 *)(port), (u8 *)(buf), (nr))
#define outsb(port, buf, nr) \
raw_outsb((u8 *)(port), (u8 *)(buf), (nr))
#define insw(port, buf, nr) \
raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr))
#define outsw(port, buf, nr) \
raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr))
#define insl(port, buf, nr) \
raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1)
#define outsl(port, buf, nr) \
raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1)
#endif /* CONFIG_PCI */
#define mmiowb()
static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_writethrough(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
__builtin_memset((void __force *) addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
{
__builtin_memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
__builtin_memcpy((void __force *) dst, src, count);
}
#define IO_SPACE_LIMIT 0xffffffff
#endif /* __KERNEL__ */
#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
#define __raw_readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define __raw_readw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define __raw_readl(addr) \
({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; })
#define __raw_writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define __raw_writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define __raw_writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
#if !defined(readb)
#define readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define readw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define readl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#endif /* readb */
#endif /* _IO_H */

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/*
* linux/include/asm-m68k/cf_page.h
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Based on linux/include/asm-m68k/page.h
*
* 10/09/08 JKM: split Coldfire pieces into separate file
*/
#ifndef __CF_PAGE__
#define __CF_PAGE__
#include <linux/const.h>
#include <asm/setup.h>
#include <asm/page_offset.h>
/* Virtual base page location */
#define PAGE_OFFSET (PAGE_OFFSET_RAW)
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT (13) /* 8K pages */
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#define THREAD_SIZE PAGE_SIZE
#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <asm/module.h>
#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
#define free_user_page(page, addr) free_page(addr)
#define clear_page(page) memset((page), 0, PAGE_SIZE)
#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
#define clear_user_page(addr, vaddr, page) \
do { clear_page(addr); \
flush_dcache_page(page); \
} while (0)
#define copy_user_page(to, from, vaddr, page) \
do { copy_page(to, from); \
flush_dcache_page(page); \
} while (0)
/*
* These are used to make use of C type-checking..
*/
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pmd[16]; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
typedef struct page *pgtable_t;
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((&x)->pmd[0])
#define pgd_val(x) ((x).pgd)
#define pgprot_val(x) ((x).pgprot)
#define __pte(x) ((pte_t) { (x) } )
#define __pmd(x) ((pmd_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
/* to align the pointer to the (next) page boundary */
/*Defined in linux/mm.h*/
/*#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)*/
extern unsigned long m68k_memoffset;
#define WANT_PAGE_VIRTUAL
extern unsigned long cf_dma_base;
extern unsigned long cf_dma_end;
/*
* Convert a virt to a phys
*/
static inline unsigned long ___pa(void *vaddr)
{
#if CONFIG_SDRAM_BASE != PAGE_OFFSET
return (((unsigned long)vaddr & 0x0fffffff) + CONFIG_SDRAM_BASE);
#else
if ((unsigned long)vaddr >= CONFIG_DMA_BASE &&
(unsigned long)vaddr < (CONFIG_DMA_BASE + CONFIG_DMA_SIZE)) {
/* address is in carved out DMA range */
return ((unsigned long)vaddr - CONFIG_DMA_BASE) + CONFIG_SDRAM_BASE;
}
else if ((unsigned long)vaddr >= PAGE_OFFSET &&
(unsigned long)vaddr < (PAGE_OFFSET + CONFIG_SDRAM_SIZE)) {
/* normal mapping */
return ((unsigned long)vaddr - PAGE_OFFSET) + CONFIG_SDRAM_BASE;
}
return (unsigned long)vaddr;
#endif
}
#define __pa(vaddr) ___pa((void *)(vaddr))
/*
* Convert a phys to a virt
*/
static inline void *__va(unsigned long paddr)
{
#if CONFIG_SDRAM_BASE != PAGE_OFFSET
return (void *)((paddr & 0x0fffffff) + PAGE_OFFSET);
#else
if (paddr >= cf_dma_base && paddr <= cf_dma_end) {
/* mapped address for DMA */
return (void *)((paddr - CONFIG_SDRAM_BASE) + CONFIG_DMA_BASE);
}
else if (paddr >= cf_dma_end &&
paddr < (CONFIG_SDRAM_BASE + CONFIG_SDRAM_SIZE)) {
/* normal mapping */
return (void *)((paddr - CONFIG_SDRAM_BASE) + PAGE_OFFSET);
}
return (void *)paddr;
#endif
}
/*
* NOTE: virtual isn't really correct, actually it should be the offset into the
* memory node, but we have no highmem, so that works for now.
*
* TODO: implement (fast) pfn<->pgdat_idx conversion functions, this makes lots
* of the shifts unnecessary.
*
* PFNs are used to map physical pages. So PFN[0] maps to the base phys addr.
*/
#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
extern int m68k_virt_to_node_shift;
#ifdef CONFIG_SINGLE_MEMORY_CHUNK
#define __virt_to_node(addr) (&pg_data_map[0])
#else
extern struct pglist_data *pg_data_table[];
static inline __attribute_const__ int __virt_to_node_shift(void)
{
return m68k_virt_to_node_shift;
}
#define __virt_to_node(addr) (pg_data_table[(unsigned long)(addr) >> __virt_to_node_shift()])
#endif /* !CONFIG_SINGLE_MEMORY_CHUNK */
#define virt_to_page(addr) ({ \
pfn_to_page(virt_to_pfn(addr)); \
})
#define page_to_virt(page) ({ \
pfn_to_virt(page_to_pfn(page)); \
})
#define pfn_to_page(pfn) ({ \
unsigned long __pfn = (pfn); \
struct pglist_data *pgdat; \
pgdat = __virt_to_node((unsigned long)pfn_to_virt(__pfn)); \
pgdat->node_mem_map + (__pfn - pgdat->node_start_pfn); \
})
#define page_to_pfn(_page) ({ \
struct page *__p = (_page); \
struct pglist_data *pgdat; \
pgdat = &pg_data_map[page_to_nid(__p)]; \
((__p) - pgdat->node_mem_map) + pgdat->node_start_pfn; \
})
#define virt_addr_valid(kaddr) ( ((void *)(kaddr) >= (void *)PAGE_OFFSET && \
(void *)(kaddr) < high_memory) || \
((void *)(kaddr) >= (void*)CONFIG_DMA_BASE && \
(void *)(kaddr) < (void*)(CONFIG_DMA_BASE+CONFIG_DMA_SIZE)))
#define pfn_valid(pfn) virt_addr_valid(pfn_to_virt(pfn))
#endif /* __ASSEMBLY__ */
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#include <asm-generic/getorder.h>
#ifdef CONFIG_VDSO
#define __HAVE_ARCH_GATE_AREA
#endif
#endif /* __CF_PAGE__ */

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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef M68K_CF_PGALLOC_H
#define M68K_CF_PGALLOC_H
#include <linux/highmem.h>
#include <asm/coldfire.h>
#include <asm/page.h>
#include <asm/cf_tlbflush.h>
#include <asm/cf_cacheflush.h>
extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
free_page((unsigned long) pte);
}
extern const char bad_pmd_string[];
extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
unsigned long address)
{
unsigned long page = __get_free_page(GFP_KERNEL|__GFP_REPEAT);
if (!page)
return NULL;
memset((void *)page, 0, PAGE_SIZE);
return (pte_t *) (page);
}
extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address)
{
return (pmd_t *) pgd;
}
#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); })
#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); })
#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr)
#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \
(unsigned long)(page_address(page)))
#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte))
#define pmd_pgtable(pmd) pmd_page(pmd)
static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page, unsigned long address)
{
__free_page(page);
}
#define __pmd_free_tlb(tlb, pmd, addr) do { } while (0)
static inline struct page *pte_alloc_one(struct mm_struct *mm,
unsigned long address)
{
struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0);
pte_t *pte;
if (!page)
return NULL;
pte = kmap(page);
// if (pte) {
clear_page(pte);
__flush_page_to_ram(pte);
flush_tlb_kernel_page(pte);
nocache_page(pte);
// }
kunmap(page);
return page;
}
extern inline void pte_free(struct mm_struct *mm, struct page *page)
{
__free_page(page);
}
/*
* In our implementation, each pgd entry contains 1 pmd that is never allocated
* or freed. pgd_present is always 1, so this should never be called. -NL
*/
#define pmd_free(mm, pmd) BUG()
extern inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
{
free_page((unsigned long) pgd);
}
extern inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
pgd_t *new_pgd;
new_pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_NOWARN);
if (!new_pgd)
return NULL;
memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE);
memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT);
return new_pgd;
}
#define pgd_populate(mm, pmd, pte) BUG()
#endif /* M68K_CF_PGALLOC_H */

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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef _CF_PGTABLE_H
#define _CF_PGTABLE_H
#include <asm/cfmmu.h>
#include <asm/page.h>
#ifndef __ASSEMBLY__
#include <asm/virtconvert.h>
#include <linux/linkage.h>
/* For virtual address to physical address conversion */
#define VTOP(addr) __pa(addr)
#define PTOV(addr) __va(addr)
#endif /* !__ASSEMBLY__ */
/* Page protection values within PTE. */
/* MMUDR bits, in proper place. */
#define CF_PAGE_LOCKED (0x00000002)
#define CF_PAGE_EXEC (0x00000004)
#define CF_PAGE_WRITABLE (0x00000008)
#define CF_PAGE_READABLE (0x00000010)
#define CF_PAGE_SYSTEM (0x00000020)
#define CF_PAGE_COPYBACK (0x00000040)
#define CF_PAGE_NOCACHE (0x00000080)
#define CF_CACHEMASK (~0x00000040)
#define CF_PAGE_MMUDR_MASK (0x000000fe)
#define _PAGE_NOCACHE030 (CF_PAGE_NOCACHE)
/* MMUTR bits, need shifting down. */
#define CF_PAGE_VALID (0x00000400)
#define CF_PAGE_SHARED (0x00000800)
#define CF_PAGE_MMUTR_MASK (0x00000c00)
#define CF_PAGE_MMUTR_SHIFT (10)
#define CF_ASID_MMU_SHIFT (2)
/* Fake bits, not implemented in CF, will get masked out before
hitting hardware, and might go away altogether once this port is
complete. */
#if PAGE_SHIFT < 13
#error COLDFIRE Error: Pages must be at least 8k in size
#endif
#define CF_PAGE_ACCESSED (0x00001000)
#define CF_PAGE_FILE (0x00000200)
#define CF_PAGE_DIRTY (0x00000001)
#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
#define _DESCTYPE_MASK 0x003
#define _CACHEMASK040 (~0x060)
#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
/* Externally used page protection values. */
#define _PAGE_PRESENT (CF_PAGE_VALID)
#define _PAGE_ACCESSED (CF_PAGE_ACCESSED)
#define _PAGE_DIRTY (CF_PAGE_DIRTY)
#define _PAGE_READWRITE (CF_PAGE_WRITABLE \
| CF_PAGE_READABLE \
| CF_PAGE_SHARED \
| CF_PAGE_SYSTEM)
/* Compound page protection values. */
#define PAGE_NONE __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED)
#define PAGE_SHARED __pgprot(CF_PAGE_VALID \
| CF_PAGE_READABLE \
| CF_PAGE_WRITABLE \
| CF_PAGE_ACCESSED)
#define PAGE_INIT __pgprot(CF_PAGE_VALID \
| CF_PAGE_WRITABLE \
| CF_PAGE_READABLE \
| CF_PAGE_EXEC \
| CF_PAGE_SYSTEM \
| CF_PAGE_SHARED)
#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \
| CF_PAGE_WRITABLE \
| CF_PAGE_READABLE \
| CF_PAGE_EXEC \
| CF_PAGE_SYSTEM \
| CF_PAGE_SHARED \
| CF_PAGE_ACCESSED)
#define PAGE_COPY __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_READABLE)
/*
* Page protections for initialising protection_map. See mm/mmap.c
* for use. In general, the bit positions are xwr, and P-items are
* private, the S-items are shared.
*/
#define __P000 PAGE_NONE
#define __P100 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_EXEC)
#define __P010 __pgprot(CF_PAGE_VALID \
| CF_PAGE_WRITABLE \
| CF_PAGE_ACCESSED)
#define __P110 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_WRITABLE \
| CF_PAGE_EXEC)
#define __P001 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_READABLE)
#define __P101 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_READABLE \
| CF_PAGE_EXEC)
#define __P011 __pgprot(CF_PAGE_VALID \
| CF_PAGE_READABLE \
| CF_PAGE_WRITABLE \
| CF_PAGE_ACCESSED)
#define __P111 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_WRITABLE \
| CF_PAGE_READABLE \
| CF_PAGE_EXEC)
#define __S000 PAGE_NONE
#define __S100 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_EXEC)
#define __S010 PAGE_SHARED
#define __S110 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_WRITABLE \
| CF_PAGE_EXEC)
#define __S001 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_READABLE)
#define __S101 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_READABLE \
| CF_PAGE_EXEC)
#define __S011 PAGE_SHARED
#define __S111 __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \
| CF_PAGE_READABLE \
| CF_PAGE_WRITABLE \
| CF_PAGE_EXEC)
#define PTE_MASK PAGE_MASK
#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY)
#ifndef __ASSEMBLY__
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot);
return pte;
}
#define pmd_set(pmdp, ptep) do {} while (0)
static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
{
pgd_val(*pgdp) = virt_to_phys(pmdp);
}
#define __pte_page(pte) \
((unsigned long) ((pte_val(pte) & CF_PAGE_PGNUM_MASK) + PAGE_OFFSET))
#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd)))
extern inline int pte_none(pte_t pte)
{
return !pte_val(pte);
}
extern inline int pte_present(pte_t pte)
{
return pte_val(pte) & CF_PAGE_VALID;
}
extern inline void pte_clear(struct mm_struct *mm, unsigned long addr,
pte_t *ptep)
{
pte_val(*ptep) = 0;
}
#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
#define pte_page(pte) virt_to_page(__pte_page(pte))
extern inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); }
#define pmd_none(pmd) pmd_none2(&(pmd))
extern inline int pmd_bad2(pmd_t *pmd) { return 0; }
#define pmd_bad(pmd) pmd_bad2(&(pmd))
#define pmd_present(pmd) (!pmd_none2(&(pmd)))
extern inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; }
extern inline int pgd_none(pgd_t pgd) { return 0; }
extern inline int pgd_bad(pgd_t pgd) { return 0; }
extern inline int pgd_present(pgd_t pgd) { return 1; }
extern inline void pgd_clear(pgd_t *pgdp) {}
#define pte_ERROR(e) \
printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
__FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \
__FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
__FILE__, __LINE__, pgd_val(e))
/*
* The following only work if pte_present() is true.
* Undefined behaviour if not...
* [we have the full set here even if they don't change from m68k]
*/
extern inline int pte_read(pte_t pte) \
{ return pte_val(pte) & CF_PAGE_READABLE; }
extern inline int pte_write(pte_t pte) \
{ return pte_val(pte) & CF_PAGE_WRITABLE; }
extern inline int pte_exec(pte_t pte) \
{ return pte_val(pte) & CF_PAGE_EXEC; }
extern inline int pte_dirty(pte_t pte) \
{ return pte_val(pte) & CF_PAGE_DIRTY; }
extern inline int pte_young(pte_t pte) \
{ return pte_val(pte) & CF_PAGE_ACCESSED; }
extern inline int pte_file(pte_t pte) \
{ return pte_val(pte) & CF_PAGE_FILE; }
static inline int pte_special(pte_t pte) { return 0; }
extern inline pte_t pte_wrprotect(pte_t pte) \
{ pte_val(pte) &= ~CF_PAGE_WRITABLE; return pte; }
extern inline pte_t pte_rdprotect(pte_t pte) \
{ pte_val(pte) &= ~CF_PAGE_READABLE; return pte; }
extern inline pte_t pte_exprotect(pte_t pte) \
{ pte_val(pte) &= ~CF_PAGE_EXEC; return pte; }
extern inline pte_t pte_mkclean(pte_t pte) \
{ pte_val(pte) &= ~CF_PAGE_DIRTY; return pte; }
extern inline pte_t pte_mkold(pte_t pte) \
{ pte_val(pte) &= ~CF_PAGE_ACCESSED; return pte; }
extern inline pte_t pte_mkwrite(pte_t pte) \
{ pte_val(pte) |= CF_PAGE_WRITABLE; return pte; }
extern inline pte_t pte_mkread(pte_t pte) \
{ pte_val(pte) |= CF_PAGE_READABLE; return pte; }
extern inline pte_t pte_mkexec(pte_t pte) \
{ pte_val(pte) |= CF_PAGE_EXEC; return pte; }
extern inline pte_t pte_mkdirty(pte_t pte) \
{ pte_val(pte) |= CF_PAGE_DIRTY; return pte; }
extern inline pte_t pte_mkyoung(pte_t pte) \
{ pte_val(pte) |= CF_PAGE_ACCESSED; return pte; }
extern inline pte_t pte_mknocache(pte_t pte) \
{ pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40); return pte; }
extern inline pte_t pte_mkcache(pte_t pte) \
{ pte_val(pte) &= ~CF_PAGE_NOCACHE; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
#define swapper_pg_dir kernel_pg_dir
extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
/* Find an entry in a pagetable directory. */
#define pgd_index(address) ((address) >> PGDIR_SHIFT)
#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
/* Find an entry in a kernel pagetable directory. */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
/* Find an entry in the second-level pagetable. */
extern inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address)
{
return (pmd_t *) pgd;
}
/* Find an entry in the third-level pagetable. */
#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir, address) ((pte_t *) __pmd_page(*(dir)) + \
__pte_offset(address))
/* Disable caching for page at given kernel virtual address. */
static inline void nocache_page(void *vaddr)
{
pgd_t *dir;
pmd_t *pmdp;
pte_t *ptep;
unsigned long addr = (unsigned long)vaddr;
dir = pgd_offset_k(addr);
pmdp = pmd_offset(dir, addr);
ptep = pte_offset_kernel(pmdp, addr);
*ptep = pte_mknocache(*ptep);
}
/* Enable caching for page at given kernel virtual address. */
static inline void cache_page(void *vaddr)
{
pgd_t *dir;
pmd_t *pmdp;
pte_t *ptep;
unsigned long addr = (unsigned long)vaddr;
dir = pgd_offset_k(addr);
pmdp = pmd_offset(dir, addr);
ptep = pte_offset_kernel(pmdp, addr);
*ptep = pte_mkcache(*ptep);
}
#define PTE_FILE_MAX_BITS 21
#define PTE_FILE_SHIFT 11
static inline unsigned long pte_to_pgoff(pte_t pte)
{
return pte_val(pte) >> PTE_FILE_SHIFT;
}
static inline pte_t pgoff_to_pte(unsigned pgoff)
{
pte_t pte = __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE);
return pte;
}
/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
(offset << PTE_FILE_SHIFT) })
#define __swp_type(x) ((x).val & 0xFF)
#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) (__pte((x).val))
#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
#define pte_offset_map(pmdp, address) ((pte_t *)__pmd_page(*pmdp) + \
__pte_offset(address))
#define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address)
#define pte_unmap(pte) kunmap(pte)
#define pte_unmap_nested(pte) kunmap(pte)
#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
#endif /* !__ASSEMBLY__ */
#endif /* !_CF_PGTABLE_H */

181
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_raw_io.h
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@ -1,181 +0,0 @@
/*
* linux/include/asm-m68k/cf_raw_io.h
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* 09/30/08 JKM: split Coldfire pieces into separate file
*/
#ifndef __CF_RAW_IO__
#define __CF_RAW_IO__
#ifdef __KERNEL__
#include <asm/types.h>
/* Values for nocacheflag and cmode */
#define IOMAP_FULL_CACHING 0
#define IOMAP_NOCACHE_SER 1
#define IOMAP_NOCACHE_NONSER 2
#define IOMAP_WRITETHROUGH 3
extern void iounmap(void __iomem *addr);
extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
int cacheflag);
extern void __iounmap(void *addr, unsigned long size);
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesirable for some devices.
*/
#define in_8(addr) \
({ u8 __v = (*(__force volatile u8 *) (addr)); __v; })
#define in_be16(addr) \
({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
#define in_be32(addr) \
({ u32 __v = (*(__force volatile u32 *) (addr)); __v; })
#define in_le16(addr) \
({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; })
#define in_le32(addr) \
({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; })
#define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b))
#define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w))
#define out_be32(addr,l) (void)((*(__force volatile u32 *) (addr)) = (l))
#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w))
#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l))
#ifdef CONFIG_PCI
/* pci */
unsigned char pci_inb(long addr);
unsigned short pci_inw(long addr);
unsigned long pci_inl(long addr);
void pci_outb(unsigned char val, long addr);
void pci_outw(unsigned short val, long addr);
void pci_outl(unsigned long val, long addr);
void pci_insb(volatile unsigned char *addr,
unsigned char *buf, int len);
void pci_insw(volatile unsigned short *addr,
unsigned short *buf, int len);
void pci_insl(volatile unsigned long *addr,
unsigned long *buf, int len);
void pci_outsb(volatile unsigned char *addr,
const unsigned char *buf, int len);
void pci_outsw(volatile unsigned short *addr,
const unsigned short *buf, int len);
void pci_outsl(volatile unsigned long *addr,
const unsigned long *buf, int len);
unsigned short pci_raw_inw(long addr);
unsigned long pci_raw_inl(long addr);
void pci_raw_outw(unsigned short val, long addr);
void pci_raw_outl(unsigned long val, long addr);
#define raw_inb(port) pci_inb((long)((volatile unsigned char *)(port)))
#define raw_inw(port) pci_raw_inw((long)((volatile unsigned short *)(port)))
#define raw_inl(port) pci_raw_inl((long)((volatile unsigned long *)(port)))
#define raw_outb(val, port) \
pci_outb((val), (long)((volatile unsigned char *)(port)))
#define raw_outw(val, port) \
pci_raw_outw((val), (long)((volatile unsigned short *)(port)))
#define raw_outl(val, port) \
pci_raw_outl((val), (long)((volatile unsigned long *)(port)))
#define swap_inw(port) pci_inw((long)((volatile unsigned short *)(port)))
#define swap_outw(val, port) \
pci_outw((val), (long)((volatile unsigned short *)(port)))
#else
/* non-pci */
#define raw_inb in_8
#define raw_inw in_be16
#define raw_inl in_be32
#define raw_outb(val,port) out_8((port),(val))
#define raw_outw(val,port) out_be16((port),(val))
#define raw_outl(val,port) out_be32((port),(val))
#define swap_inw(port) in_le16((port))
#define swap_outw(val,port) out_le16((port),(val))
#endif
static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len)
{
unsigned int i;
for (i = 0; i < len; i++)
*buf++ = in_8(port);
}
static inline void raw_outsb(volatile u8 __iomem *port, const u8 *buf,
unsigned int len)
{
unsigned int i;
for (i = 0; i < len; i++)
out_8(port, *buf++);
}
static inline void raw_insw(volatile u16 *port, u16 *buf, unsigned int nr)
{
unsigned int i;
for (i = 0; i < nr; i++)
*buf++ = raw_inw(port);
}
static inline void raw_outsw(volatile u16 *port, const u16 *buf,
unsigned int nr)
{
unsigned int i;
for (i = 0; i < nr; i++, buf++)
raw_outw(*buf, port);
}
static inline void raw_insl(volatile u32 *port, u32 *buf, unsigned int nr)
{
unsigned int i;
for (i = 0; i < nr; i++)
*buf++ = raw_inl(port);
}
static inline void raw_outsl(volatile u32 *port, const u32 *buf,
unsigned int nr)
{
unsigned int i;
for (i = 0; i < nr; i++, buf++)
raw_outl(*buf, port);
}
static inline void raw_insw_swapw(volatile u16 *port, u16 *buf,
unsigned int nr)
{
#ifdef UNDEF
unsigned int i;
for (i = 0; i < nr; i++)
*buf++ = in_le16(port);
#endif
}
static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf,
unsigned int nr)
{
#ifdef UNDEF
unsigned int i;
for (i = 0; i < nr; i++, buf++)
out_le16(port, *buf);
#endif
}
#endif /* __KERNEL__ */
#endif /* __CF_RAW_IO__ */

62
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_tlbflush.h
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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef M68K_CF_TLBFLUSH_H
#define M68K_CF_TLBFLUSH_H
#include <asm/coldfire.h>
/* Flush all userspace mappings. */
static inline void flush_tlb_all(void)
{
preempt_disable();
*MMUOR = MMUOR_CNL;
preempt_enable();
}
/* Clear user TLB entries within the context named in mm */
static inline void flush_tlb_mm(struct mm_struct *mm)
{
preempt_disable();
*MMUOR = MMUOR_CNL;
preempt_enable();
}
/* Flush a single TLB page. */
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long addr)
{
preempt_disable();
*MMUOR = MMUOR_CNL;
preempt_enable();
}
/* Flush a range of pages from TLB. */
static inline void flush_tlb_range(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
preempt_disable();
*MMUOR = MMUOR_CNL;
preempt_enable();
}
/* Flush kernel page from TLB. */
static inline void flush_tlb_kernel_page(void *addr)
{
preempt_disable();
*MMUOR = MMUOR_CNL;
preempt_enable();
}
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
flush_tlb_all();
}
extern inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
}
#endif /* M68K_CF_TLBFLUSH_H */

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target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_uaccess.h
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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef __M68K_CF_UACCESS_H
#define __M68K_CF_UACCESS_H
/*
* User space memory access functions
*/
/* The "moves" command is not available in the CF instruction set. */
#include <linux/compiler.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <asm/segment.h>
#define VERIFY_READ 0
#define VERIFY_WRITE 1
/* We let the MMU do all checking */
#define access_ok(type, addr, size) 1
/*
* The exception table consists of pairs of addresses: the first is the
* address of an instruction that is allowed to fault, and the second is
* the address at which the program should continue. No registers are
* modified, so it is entirely up to the continuation code to figure out
* what to do.
*
* All the routines below use bits of fixup code that are out of line
* with the main instruction path. This means when everything is well,
* we don't even have to jump over them. Further, they do not intrude
* on our cache or tlb entries.
*/
struct exception_table_entry
{
unsigned long insn, fixup;
};
extern int __put_user_bad(void);
extern int __get_user_bad(void);
#define __put_user_asm(res, x, ptr, bwl, reg, err) \
asm volatile ("\n" \
"1: move."#bwl" %2,%1\n" \
"2:\n" \
" .section .fixup,\"ax\"\n" \
" .even\n" \
"10: moveq.l %3,%0\n" \
" jra 2b\n" \
" .previous\n" \
"\n" \
" .section __ex_table,\"a\"\n" \
" .align 4\n" \
" .long 1b,10b\n" \
" .long 2b,10b\n" \
" .previous" \
: "+d" (res), "=m" (*(ptr)) \
: #reg (x), "i" (err))
/*
* These are the main single-value transfer routines. They automatically
* use the right size if we just have the right pointer type.
*/
#define __put_user(x, ptr) \
({ \
typeof(*(ptr)) __pu_val = (x); \
int __pu_err = 0; \
__chk_user_ptr(ptr); \
switch (sizeof (*(ptr))) { \
case 1: \
__put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \
break; \
case 2: \
__put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \
break; \
case 4: \
__put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \
break; \
case 8: \
{ \
const void __user *__pu_ptr = (ptr); \
asm volatile ("\n" \
"1: move.l %2,(%1)+\n" \
"2: move.l %R2,(%1)\n" \
"3:\n" \
" .section .fixup,\"ax\"\n" \
" .even\n" \
"10: movel %3,%0\n" \
" jra 3b\n" \
" .previous\n" \
"\n" \
" .section __ex_table,\"a\"\n" \
" .align 4\n" \
" .long 1b,10b\n" \
" .long 2b,10b\n" \
" .long 3b,10b\n" \
" .previous" \
: "+d" (__pu_err), "+a" (__pu_ptr) \
: "r" (__pu_val), "i" (-EFAULT) \
: "memory"); \
break; \
} \
default: \
__pu_err = __put_user_bad(); \
break; \
} \
__pu_err; \
})
#define put_user(x, ptr) __put_user(x, ptr)
#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \
type __gu_val; \
asm volatile ("\n" \
"1: move."#bwl" %2,%1\n" \
"2:\n" \
" .section .fixup,\"ax\"\n" \
" .even\n" \
"10: move.l %3,%0\n" \
" subl %1,%1\n" \
" jra 2b\n" \
" .previous\n" \
"\n" \
" .section __ex_table,\"a\"\n" \
" .align 4\n" \
" .long 1b,10b\n" \
" .previous" \
: "+d" (res), "=&" #reg (__gu_val) \
: "m" (*(ptr)), "i" (err)); \
(x) = (typeof(*(ptr)))(unsigned long)__gu_val; \
})
#define __get_user(x, ptr) \
({ \
int __gu_err = 0; \
__chk_user_ptr(ptr); \
switch (sizeof(*(ptr))) { \
case 1: \
__get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \
break; \
case 2: \
__get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT); \
break; \
case 4: \
__get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \
break; \
/* case 8: disabled because gcc-4.1 has a broken typeof \
{ \
const void *__gu_ptr = (ptr); \
u64 __gu_val; \
asm volatile ("\n" \
"1: move.l (%2)+,%1\n" \
"2: move.l (%2),%R1\n" \
"3:\n" \
" .section .fixup,\"ax\"\n" \
" .even\n" \
"10: move.l %3,%0\n" \
" subl %1,%1\n" \
" subl %R1,%R1\n" \
" jra 3b\n" \
" .previous\n" \
"\n" \
" .section __ex_table,\"a\"\n" \
" .align 4\n" \
" .long 1b,10b\n" \
" .long 2b,10b\n" \
" .previous" \
: "+d" (__gu_err), "=&r" (__gu_val), \
"+a" (__gu_ptr) \
: "i" (-EFAULT) \
: "memory"); \
(x) = (typeof(*(ptr)))__gu_val; \
break; \
} */ \
default: \
__gu_err = __get_user_bad(); \
break; \
} \
__gu_err; \
})
#define get_user(x, ptr) __get_user(x, ptr)
unsigned long __generic_copy_from_user(void *to, const void __user *from,
unsigned long n);
unsigned long __generic_copy_to_user(void __user *to, const void *from,
unsigned long n);
#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\
asm volatile ("\n" \
"1: move."#s1" (%2)+,%3\n" \
" move."#s1" %3,(%1)+\n" \
"2: move."#s2" (%2)+,%3\n" \
" move."#s2" %3,(%1)+\n" \
" .ifnc \""#s3"\",\"\"\n" \
"3: move."#s3" (%2)+,%3\n" \
" move."#s3" %3,(%1)+\n" \
" .endif\n" \
"4:\n" \
" .section __ex_table,\"a\"\n" \
" .align 4\n" \
" .long 1b,10f\n" \
" .long 2b,20f\n" \
" .ifnc \""#s3"\",\"\"\n" \
" .long 3b,30f\n" \
" .endif\n" \
" .previous\n" \
"\n" \
" .section .fixup,\"ax\"\n" \
" .even\n" \
"10: clr."#s1" (%1)+\n" \
"20: clr."#s2" (%1)+\n" \
" .ifnc \""#s3"\",\"\"\n" \
"30: clr."#s3" (%1)+\n" \
" .endif\n" \
" moveq.l #"#n",%0\n" \
" jra 4b\n" \
" .previous\n" \
: "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \
: : "memory")
static __always_inline unsigned long
__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
{
unsigned long res = 0, tmp;
switch (n) {
case 1:
__get_user_asm(res, *(u8 *)to, (u8 __user *)from, u8, b, d, 1);
break;
case 2:
__get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w,
d, 2);
break;
case 3:
__constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,);
break;
case 4:
__get_user_asm(res, *(u32 *)to, (u32 __user *)from, u32, l,
r, 4);
break;
case 5:
__constant_copy_from_user_asm(res, to, from, tmp, 5, l, b,);
break;
case 6:
__constant_copy_from_user_asm(res, to, from, tmp, 6, l, w,);
break;
case 7:
__constant_copy_from_user_asm(res, to, from, tmp, 7, l, w, b);
break;
case 8:
__constant_copy_from_user_asm(res, to, from, tmp, 8, l, l,);
break;
case 9:
__constant_copy_from_user_asm(res, to, from, tmp, 9, l, l, b);
break;
case 10:
__constant_copy_from_user_asm(res, to, from, tmp, 10, l, l, w);
break;
case 12:
__constant_copy_from_user_asm(res, to, from, tmp, 12, l, l, l);
break;
default:
/* we limit the inlined version to 3 moves */
return __generic_copy_from_user(to, from, n);
}
return res;
}
#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \
asm volatile ("\n" \
" move."#s1" (%2)+,%3\n" \
"11: move."#s1" %3,(%1)+\n" \
"12: move."#s2" (%2)+,%3\n" \
"21: move."#s2" %3,(%1)+\n" \
"22:\n" \
" .ifnc \""#s3"\",\"\"\n" \
" move."#s3" (%2)+,%3\n" \
"31: move."#s3" %3,(%1)+\n" \
"32:\n" \
" .endif\n" \
"4:\n" \
"\n" \
" .section __ex_table,\"a\"\n" \
" .align 4\n" \
" .long 11b,5f\n" \
" .long 12b,5f\n" \
" .long 21b,5f\n" \
" .long 22b,5f\n" \
" .ifnc \""#s3"\",\"\"\n" \
" .long 31b,5f\n" \
" .long 32b,5f\n" \
" .endif\n" \
" .previous\n" \
"\n" \
" .section .fixup,\"ax\"\n" \
" .even\n" \
"5: moveq.l #"#n",%0\n" \
" jra 4b\n" \
" .previous\n" \
: "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \
: : "memory")
static __always_inline unsigned long
__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
{
unsigned long res = 0, tmp;
switch (n) {
case 1:
__put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1);
break;
case 2:
__put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, d, 2);
break;
case 3:
__constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,);
break;
case 4:
__put_user_asm(res, *(u32 *)from, (u32 __user *)to, l, r, 4);
break;
case 5:
__constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,);
break;
case 6:
__constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,);
break;
case 7:
__constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b);
break;
case 8:
__constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,);
break;
case 9:
__constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b);
break;
case 10:
__constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w);
break;
case 12:
__constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l);
break;
default:
/* limit the inlined version to 3 moves */
return __generic_copy_to_user(to, from, n);
}
return res;
}
#define __copy_from_user(to, from, n) \
(__builtin_constant_p(n) ? \
__constant_copy_from_user(to, from, n) : \
__generic_copy_from_user(to, from, n))
#define __copy_to_user(to, from, n) \
(__builtin_constant_p(n) ? \
__constant_copy_to_user(to, from, n) : \
__generic_copy_to_user(to, from, n))
#define __copy_to_user_inatomic __copy_to_user
#define __copy_from_user_inatomic __copy_from_user
#define copy_from_user(to, from, n) __copy_from_user(to, from, n)
#define copy_to_user(to, from, n) __copy_to_user(to, from, n)
long strncpy_from_user(char *dst, const char __user *src, long count);
long strnlen_user(const char __user *src, long n);
unsigned long __clear_user(void __user *to, unsigned long n);
#define clear_user __clear_user
#define strlen_user(str) strnlen_user(str, 32767)
#endif /* _M68K_CF_UACCESS_H */

58
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_virtconvert.h
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@ -1,58 +0,0 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef __CF_VIRTCONVERT__
#define __CF_VIRTCONVERT__
/*
* Macros used for converting between virtual and physical mappings.
*
* Coldfire Specific
*/
#ifdef __KERNEL__
#include <linux/compiler.h>
#include <linux/mmzone.h>
#include <asm/setup.h>
#include <asm/page.h>
/*
* Change virtual addresses to physical addresses and vv.
*/
static inline unsigned long virt_to_phys(void *address)
{
return __pa(address);
}
static inline void *phys_to_virt(unsigned long address)
{
return __va(address);
}
/* Permanent address of a page. */
#ifdef CONFIG_SINGLE_MEMORY_CHUNK
#define page_to_phys(page) \
__pa(PAGE_OFFSET + (((page) - pg_data_map[0].node_mem_map) << PAGE_SHIFT))
#else
#define page_to_phys(_page) ({ \
struct page *__page = _page; \
struct pglist_data *pgdat; \
pgdat = pg_data_table[page_to_nid(__page)]; \
page_to_pfn(__page) << PAGE_SHIFT; \
})
#endif
/*
* IO bus memory addresses are 1:1 with the physical address,
*/
#ifdef CONFIG_PCI
#define virt_to_bus(a) (a + PCI_DMA_BASE)
#define bus_to_virt(a) (a - PCI_DMA_BASE)
#else
#define virt_to_bus(a) (a)
#define bus_to_virt(a) (a)
#endif
#endif /* __KERNEL__ */
#endif /* __CF_VIRTCONVERT__ */

114
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfcache.h
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@ -1,114 +0,0 @@
/*
* include/asm-m68k/cfcache.h - Coldfire Cache Controller
*
* Kurt Mahan kmahan@freescale.com
*
* Copyright Freescale Semiconductor, Inc. 2007
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef CF_CFCACHE_H
#define CF_CFCACHE_H
/*
* CACR Cache Control Register
*/
#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
#define CF_CACR_DW (0x40000000) /* Data default Write-protect */
#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */
#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */
#define CF_CACR_IVO (0x00100000) /* Invalidate only */
#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */
#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */
#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */
#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */
#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
#ifdef CONFIG_M5445X
/*
* M5445x Cache Configuration
* - cache line size is 16 bytes
* - cache is 4-way set associative
* - each cache has 256 sets (64k / 16bytes / 4way)
* - I-Cache size is 16KB
* - D-Cache size is 16KB
*/
#define ICACHE_SIZE 0x4000 /* instruction - 16k */
#define DCACHE_SIZE 0x4000 /* data - 16k */
#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
#define CACHE_SETS 0x0100 /* 256 sets */
#define CACHE_WAYS 0x0004 /* 4 way */
#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \
CF_CACR_BCINVA+ \
CF_CACR_ICINVA)
#ifndef CONFIG_M5445X_DISABLE_CACHE
#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \
CF_CACR_BEC+ \
CF_CACR_IEC+ \
CF_CACR_DESB+ \
CF_CACR_EUSP)
#else
/* cache disabled for testing */
#define CACHE_INITIAL_MODE (CF_CACR_EUSP)
#endif /* CONFIG_M5445X_DISABLE_CACHE */
#elif defined(CONFIG_M547X_8X)
/*
* * M547x/M548x Cache Configuration
* * - cache line size is 16 bytes
* * - cache is 4-way set associative
* * - each cache has 512 sets (128k / 16bytes / 4way)
* * - I-Cache size is 32KB
* * - D-Cache size is 32KB
* */
#define ICACHE_SIZE 0x8000 /* instruction - 32k */
#define DCACHE_SIZE 0x8000 /* data - 32k */
#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
#define CACHE_SETS 0x0200 /* 512 sets */
#define CACHE_WAYS 0x0004 /* 4 way */
/* in for the old cpushl caching code */
#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \
CF_CACR_BCINVA+ \
CF_CACR_ICINVA)
#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \
CF_CACR_BEC+ \
CF_CACR_IEC+ \
CF_CACR_DESB+ \
CF_CACR_EUSP)
#endif /* CONFIG_M547X_8X */
#ifndef __ASSEMBLY__
extern unsigned long shadow_cacr;
extern void cacr_set(unsigned long x);
#endif /* !__ASSEMBLY__ */
#endif /* CF_CACHE_H */

105
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfmmu.h
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@ -1,105 +0,0 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Definitions for Coldfire V4e MMU
*/
#include <asm/movs.h>
#ifndef __CF_MMU_H__
#define __CF_MMU_H__
#define MMU_BASE 0xE8000000
#define MMUCR (MMU_BASE+0x00)
#define MMUCR_ASMN 1
#define MMUCR_ASM (1<<MMUCR_ASMN)
#define MMUCR_ENN 0
#define MMUCR_EN (1<<MMUCR_ENN)
#define MMUOR REG16(MMU_BASE+0x04+0x02)
#define MMUOR_AAN 16
#define MMUOR_AA (0xffff<<MMUOR_AAN)
#define MMUOR_STLBN 8
#define MMUOR_STLB (1<<MMUOR_STLBN)
#define MMUOR_CAN 7
#define MMUOR_CA (1<<MMUOR_CAN)
#define MMUOR_CNLN 6
#define MMUOR_CNL (1<<MMUOR_CNLN)
#define MMUOR_CASN 5
#define MMUOR_CAS (1<<MMUOR_CASN)
#define MMUOR_ITLBN 4
#define MMUOR_ITLB (1<<MMUOR_ITLBN)
#define MMUOR_ADRN 3
#define MMUOR_ADR (1<<MMUOR_ADRN)
#define MMUOR_RWN 2
#define MMUOR_RW (1<<MMUOR_RWN)
#define MMUOR_ACCN 1
#define MMUOR_ACC (1<<MMUOR_ACCN)
#define MMUOR_UAAN 0
#define MMUOR_UAA (1<<MMUOR_UAAN)
#define MMUSR REG32(MMU_BASE+0x08)
#define MMUSR_SPFN 5
#define MMUSR_SPF (1<<MMUSR_SPFN)
#define MMUSR_RFN 4
#define MMUSR_RF (1<<MMUSR_RFN)
#define MMUSR_WFN 3
#define MMUSR_WF (1<<MMUSR_WFN)
#define MMUSR_HITN 1
#define MMUSR_HIT (1<<MMUSR_HITN)
#define MMUAR REG32(MMU_BASE+0x10)
#define MMUAR_VPN 1
#define MMUAR_VP (0xfffffffe)
#define MMUAR_SN 0
#define MMUAR_S (1<<MMUAR_SN)
#define MMUTR REG32(MMU_BASE+0x14)
#define MMUTR_VAN 10
#define MMUTR_VA (0xfffffc00)
#define MMUTR_IDN 2
#define MMUTR_ID (0xff<<MMUTR_IDN)
#define MMUTR_SGN 1
#define MMUTR_SG (1<<MMUTR_SGN)
#define MMUTR_VN 0
#define MMUTR_V (1<<MMUTR_VN)
#define MMUDR REG32(MMU_BASE+0x18)
#define MMUDR_PAN 10
#define MMUDR_PA (0xfffffc00)
#define MMUDR_SZN 8
#define MMUDR_SZ_MASK (0x2<<MMUDR_SZN)
#define MMUDR_SZ1M (0<<MMUDR_SZN)
#define MMUDR_SZ4K (1<<MMUDR_SZN)
#define MMUDR_SZ8K (2<<MMUDR_SZN)
#define MMUDR_SZ16M (3<<MMUDR_SZN)
#define MMUDR_CMN 6
#define MMUDR_INC (2<<MMUDR_CMN)
#define MMUDR_IC (0<<MMUDR_CMN)
#define MMUDR_DWT (0<<MMUDR_CMN)
#define MMUDR_DCB (1<<MMUDR_CMN)
#define MMUDR_DNCP (2<<MMUDR_CMN)
#define MMUDR_DNCIP (3<<MMUDR_CMN)
#define MMUDR_SPN 5
#define MMUDR_SP (1<<MMUDR_SPN)
#define MMUDR_RN 4
#define MMUDR_R (1<<MMUDR_RN)
#define MMUDR_WN 3
#define MMUDR_W (1<<MMUDR_WN)
#define MMUDR_XN 2
#define MMUDR_X (1<<MMUDR_XN)
#define MMUDR_LKN 1
#define MMUDR_LK (1<<MMUDR_LKN)
#ifndef __ASSEMBLY__
#define CF_PMEGS_NUM 256
#define CF_INVALID_CONTEXT 255
#define CF_PAGE_PGNUM_MASK (PAGE_MASK)
extern int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb,
int extension_word);
#endif /* __ASSEMBLY__*/
#endif /* !__CF_MMU_H__ */

98
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dma.h
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@ -1,98 +0,0 @@
/*
* m5485dma.h -- ColdFire 547x/548x DMA controller support.
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef __MCF548X_DMA_H__
#define __MCF548X_DMA_H__
/* Register read/write macros */
#define MCF_DMA_DIPR MCF_REG32(0x008014)
#define MCF_DMA_DIMR MCF_REG32(0x008018)
#define MCF_DMA_IMCR MCF_REG32(0x00805C)
/* Bit definitions and macros for MCF_DMA_DIPR */
#define MCF_DMA_DIPR_TASK0 (0x00000001)
#define MCF_DMA_DIPR_TASK1 (0x00000002)
#define MCF_DMA_DIPR_TASK2 (0x00000004)
#define MCF_DMA_DIPR_TASK3 (0x00000008)
#define MCF_DMA_DIPR_TASK4 (0x00000010)
#define MCF_DMA_DIPR_TASK5 (0x00000020)
#define MCF_DMA_DIPR_TASK6 (0x00000040)
#define MCF_DMA_DIPR_TASK7 (0x00000080)
#define MCF_DMA_DIPR_TASK8 (0x00000100)
#define MCF_DMA_DIPR_TASK9 (0x00000200)
#define MCF_DMA_DIPR_TASK10 (0x00000400)
#define MCF_DMA_DIPR_TASK11 (0x00000800)
#define MCF_DMA_DIPR_TASK12 (0x00001000)
#define MCF_DMA_DIPR_TASK13 (0x00002000)
#define MCF_DMA_DIPR_TASK14 (0x00004000)
#define MCF_DMA_DIPR_TASK15 (0x00008000)
/* Bit definitions and macros for MCF_DMA_DIMR */
#define MCF_DMA_DIMR_TASK0 (0x00000001)
#define MCF_DMA_DIMR_TASK1 (0x00000002)
#define MCF_DMA_DIMR_TASK2 (0x00000004)
#define MCF_DMA_DIMR_TASK3 (0x00000008)
#define MCF_DMA_DIMR_TASK4 (0x00000010)
#define MCF_DMA_DIMR_TASK5 (0x00000020)
#define MCF_DMA_DIMR_TASK6 (0x00000040)
#define MCF_DMA_DIMR_TASK7 (0x00000080)
#define MCF_DMA_DIMR_TASK8 (0x00000100)
#define MCF_DMA_DIMR_TASK9 (0x00000200)
#define MCF_DMA_DIMR_TASK10 (0x00000400)
#define MCF_DMA_DIMR_TASK11 (0x00000800)
#define MCF_DMA_DIMR_TASK12 (0x00001000)
#define MCF_DMA_DIMR_TASK13 (0x00002000)
#define MCF_DMA_DIMR_TASK14 (0x00004000)
#define MCF_DMA_DIMR_TASK15 (0x00008000)
/* Bit definitions and macros for MCF_DMA_IMCR */
#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0)
#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2)
#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4)
#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6)
#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8)
#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10)
#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12)
#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14)
#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16)
#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18)
#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20)
#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22)
#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24)
#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26)
#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28)
#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30)
#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000)
#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000)
#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020)
#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080)
#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100)
#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000)
#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400)
#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000)
#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000)
#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000)
#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000)
#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000)
#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000)
#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000)
#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000)
#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000)
#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000)
#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000)
#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000)
#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000)
#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000)
#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000)
#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000)
#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000)
#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000)
#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000)
#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000)
#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000)
#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000)
#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000)
#endif /* __MCF548X_DMA_H__ */

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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* File: mcf548x_dspi.h
* Purpose: Register and bit definitions for the MCF548X
*
* Notes:
*
*/
#ifndef _M5485DSPI_H_
#define _M5485DSPI_H_
/*
*
* DMA Serial Peripheral Interface (DSPI)
*
*/
/* Register read/write macros */
#define MCF_DSPI_DMCR MCF_REG32(0x008A00)
#define MCF_DSPI_DTCR MCF_REG32(0x008A08)
#define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C)
#define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10)
#define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14)
#define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18)
#define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C)
#define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20)
#define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24)
#define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28)
#define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4))
#define MCF_DSPI_DSR MCF_REG32(0x008A2C)
#define MCF_DSPI_DRSER MCF_REG32(0x008A30)
#define MCF_DSPI_DTFR MCF_REG32(0x008A34)
#define MCF_DSPI_DRFR MCF_REG32(0x008A38)
#define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C)
#define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40)
#define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44)
#define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48)
#define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4))
#define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C)
#define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80)
#define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84)
#define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88)
#define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4))
/* Bit definitions and macros for MCF_DSPI_DMCR */
#define MCF_DSPI_DMCR_HALT (0x00000001)
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
#define MCF_DSPI_DMCR_CRXF (0x00000400)
#define MCF_DSPI_DMCR_CTXF (0x00000800)
#define MCF_DSPI_DMCR_DRXF (0x00001000)
#define MCF_DSPI_DMCR_DTXF (0x00002000)
#define MCF_DSPI_DMCR_CSIS0 (0x00010000)
#define MCF_DSPI_DMCR_CSIS2 (0x00040000)
#define MCF_DSPI_DMCR_CSIS3 (0x00080000)
#define MCF_DSPI_DMCR_CSIS5 (0x00200000)
#define MCF_DSPI_DMCR_ROOE (0x01000000)
#define MCF_DSPI_DMCR_PCSSE (0x02000000)
#define MCF_DSPI_DMCR_MTFE (0x04000000)
#define MCF_DSPI_DMCR_FRZ (0x08000000)
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
#define MCF_DSPI_DMCR_CSCK (0x40000000)
#define MCF_DSPI_DMCR_MSTR (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTCR */
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_DSPI_DCTARn */
#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0)
#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
#define MCF_DSPI_DCTAR_LSBFE (0x01000000)
#define MCF_DSPI_DCTAR_CPHA (0x02000000)
#define MCF_DSPI_DCTAR_CPOL (0x04000000)
/* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */
#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27)
#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
#define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000)
#define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000)
#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
/* Bit definitions and macros for MCF_DSPI_DSR */
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0)
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
#define MCF_DSPI_DSR_RFDF (0x00020000)
#define MCF_DSPI_DSR_RFOF (0x00080000)
#define MCF_DSPI_DSR_TFFF (0x02000000)
#define MCF_DSPI_DSR_TFUF (0x08000000)
#define MCF_DSPI_DSR_EOQF (0x10000000)
#define MCF_DSPI_DSR_TXRXS (0x40000000)
#define MCF_DSPI_DSR_TCF (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DRSER */
#define MCF_DSPI_DRSER_RFDFS (0x00010000)
#define MCF_DSPI_DRSER_RFDFE (0x00020000)
#define MCF_DSPI_DRSER_RFOFE (0x00080000)
#define MCF_DSPI_DRSER_TFFFS (0x01000000)
#define MCF_DSPI_DRSER_TFFFE (0x02000000)
#define MCF_DSPI_DRSER_TFUFE (0x08000000)
#define MCF_DSPI_DRSER_EOQFE (0x10000000)
#define MCF_DSPI_DRSER_TCFE (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTFR */
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0)
#define MCF_DSPI_DTFR_CS0 (0x00010000)
#define MCF_DSPI_DTFR_CS2 (0x00040000)
#define MCF_DSPI_DTFR_CS3 (0x00080000)
#define MCF_DSPI_DTFR_CS5 (0x00200000)
#define MCF_DSPI_DTFR_CTCNT (0x04000000)
#define MCF_DSPI_DTFR_EOQ (0x08000000)
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
#define MCF_DSPI_DTFR_CONT (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DRFR */
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0)
/* Bit definitions and macros for MCF_DSPI_DTFDRn */
#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0)
#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_DSPI_DRFDRn */
#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0)
/********************************************************************/
#endif /* _M5485DSPI_H_ */

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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* File: mcf548x_gpio.h
* Purpose: Register and bit definitions for the MCF548X
*
* Notes:
*
*/
#ifndef _M5485GPIO_H_
#define _M5485GPIO_H_
/*********************************************************************
*
* General Purpose I/O (GPIO)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00)
#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01)
#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02)
#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04)
#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05)
#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06)
#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07)
#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08)
#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09)
#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A)
#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C)
#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D)
#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E)
#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10)
#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11)
#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12)
#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14)
#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15)
#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16)
#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17)
#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18)
#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19)
#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A)
#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C)
#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D)
#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E)
#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20)
#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21)
#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22)
#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24)
#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25)
#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26)
#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27)
#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28)
#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29)
#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A)
#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C)
#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D)
#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E)
#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30)
#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31)
#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32)
#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34)
#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35)
#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36)
#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37)
#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38)
#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39)
#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A)
#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C)
#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D)
#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E)
#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40)
#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42)
#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43)
#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44)
#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48)
#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A)
#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C)
#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D)
#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E)
#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F)
#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50)
#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52)
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01)
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02)
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04)
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08)
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10)
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20)
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40)
#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02)
#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04)
#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08)
#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10)
#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01)
#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02)
#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04)
#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01)
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02)
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04)
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08)
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10)
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20)
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40)
#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01)
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02)
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04)
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08)
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10)
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20)
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40)
#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01)
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02)
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04)
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08)
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10)
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20)
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40)
#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01)
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02)
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04)
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08)
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10)
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20)
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40)
#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01)
#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02)
#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04)
#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01)
#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02)
#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04)
#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08)
#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01)
#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02)
#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04)
#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08)
#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01)
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02)
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04)
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08)
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10)
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20)
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40)
#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01)
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02)
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04)
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08)
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10)
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20)
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40)
#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01)
#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02)
#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04)
#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08)
#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10)
#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20)
#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01)
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02)
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04)
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08)
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10)
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20)
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40)
#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02)
#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04)
#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08)
#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10)
#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01)
#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02)
#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04)
#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01)
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02)
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04)
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08)
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10)
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20)
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40)
#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01)
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02)
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04)
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08)
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10)
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20)
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40)
#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01)
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02)
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04)
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08)
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10)
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20)
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40)
#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01)
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02)
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04)
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08)
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10)
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20)
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40)
#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01)
#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02)
#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04)
#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01)
#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02)
#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04)
#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08)
#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01)
#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02)
#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04)
#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08)
#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01)
#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02)
#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04)
#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08)
#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10)
#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20)
#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01)
#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02)
#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04)
#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08)
#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01)
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02)
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04)
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08)
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10)
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20)
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40)
#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02)
#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04)
#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08)
#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10)
#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01)
#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02)
#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04)
#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01)
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02)
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04)
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08)
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10)
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20)
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40)
#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01)
#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02)
#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04)
#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08)
#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10)
#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20)
#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40)
#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01)
#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02)
#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04)
#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08)
#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10)
#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20)
#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40)
#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01)
#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02)
#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04)
#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08)
#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10)
#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20)
#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40)
#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01)
#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02)
#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04)
#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01)
#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02)
#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04)
#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08)
#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01)
#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02)
#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04)
#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08)
#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */
#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01)
#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10)
#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20)
#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20)
#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01)
#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02)
#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04)
#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08)
#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10)
#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20)
#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */
#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004)
#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010)
#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000)
#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0)
#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2)
#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3)
/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */
#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02)
#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04)
#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08)
#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10)
#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PAR_DMA */
#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0)
#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2)
#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0)
#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2)
#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3)
#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0)
#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2)
#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3)
/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0)
/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */
#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04)
#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30)
#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */
#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04)
#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */
#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04)
#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */
#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04)
#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30)
/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */
#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2)
#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10)
#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030)
#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008)
#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C)
#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002)
#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003)
/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1)
#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06)
/********************************************************************/
#endif /* _M5485GPIO_H_ */

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target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485gpt.h
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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* File: mcf548x_gpt.h
* Purpose: Register and bit definitions for the MCF548X
*
* Notes:
*
*/
#ifndef __MCF548X_GPT_H__
#define __MCF548X_GPT_H__
/*********************************************************************
*
* General Purpose Timers (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPT_GMS0 MCF_REG32(0x000800)
#define MCF_GPT_GCIR0 MCF_REG32(0x000804)
#define MCF_GPT_GPWM0 MCF_REG32(0x000808)
#define MCF_GPT_GSR0 MCF_REG32(0x00080C)
#define MCF_GPT_GMS1 MCF_REG32(0x000810)
#define MCF_GPT_GCIR1 MCF_REG32(0x000814)
#define MCF_GPT_GPWM1 MCF_REG32(0x000818)
#define MCF_GPT_GSR1 MCF_REG32(0x00081C)
#define MCF_GPT_GMS2 MCF_REG32(0x000820)
#define MCF_GPT_GCIR2 MCF_REG32(0x000824)
#define MCF_GPT_GPWM2 MCF_REG32(0x000828)
#define MCF_GPT_GSR2 MCF_REG32(0x00082C)
#define MCF_GPT_GMS3 MCF_REG32(0x000830)
#define MCF_GPT_GCIR3 MCF_REG32(0x000834)
#define MCF_GPT_GPWM3 MCF_REG32(0x000838)
#define MCF_GPT_GSR3 MCF_REG32(0x00083C)
#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010))
#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010))
#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010))
#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
#define MCF_GPT_GMS_IEN (0x00000100)
#define MCF_GPT_GMS_OD (0x00000200)
#define MCF_GPT_GMS_SC (0x00000400)
#define MCF_GPT_GMS_CE (0x00001000)
#define MCF_GPT_GMS_WDEN (0x00008000)
#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
#define MCF_GPT_GMS_ICT_ANY (0x00000000)
#define MCF_GPT_GMS_ICT_RISE (0x00010000)
#define MCF_GPT_GMS_ICT_FALL (0x00020000)
#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
#define MCF_GPT_GMS_TMS_PWM (0x00000003)
#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
/* Bit definitions and macros for MCF_GPT_GCIR */
#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GPWM */
#define MCF_GPT_GPWM_LOAD (0x00000001)
#define MCF_GPT_GPWM_PWMOP (0x00000100)
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GSR */
#define MCF_GPT_GSR_CAPT (0x00000001)
#define MCF_GPT_GSR_COMP (0x00000002)
#define MCF_GPT_GSR_PWMP (0x00000004)
#define MCF_GPT_GSR_TEXP (0x00000008)
#define MCF_GPT_GSR_PIN (0x00000100)
#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
#define MCF_GPT_MAX_TIMEOUT 30
/********************************************************************/
#endif /* __MCF548X_GPT_H__ */

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target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485pci.h
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/*
* m5485pci.h -- ColdFire 547x/548x PCI controller support.
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef __MCF548X_PCI_H__
#define __MCF548X_PCI_H__
/* PCI Type 0 Configuration Registers */
#define MCF_PCIIDR MCF_REG32(0x000B00)
/* PCI Device ID/Vendor ID */
#define MCF_PCISCR MCF_REG32(0x000B04)
/* PCI Status/Command */
#define MCF_PCICCRIR MCF_REG32(0x000B08)
/* PCI Class Code / Revision ID */
#define MCF_PCICR1 MCF_REG32(0x000B0C)
/* PCI Configuration 1 Register */
#define MCF_PCIBAR0 MCF_REG32(0x000B10)
/* PCI Base Address Register 0 */
#define MCF_PCIBAR1 MCF_REG32(0x000B14)
/* PCI Base Address Register 1 */
#define MCF_PCICCPR MCF_REG32(0x000B28)
/* PCI Cardbus CIS Pointer */
#define MCF_PCISID MCF_REG32(0x000B2C)
/* Subsystem ID/Subsystem Vendor ID*/
#define MCF_PCIERBAR MCF_REG32(0x000B30)
/* PCI Expansion ROM */
#define MCF_PCICPR MCF_REG32(0x000B30)
/* PCI Capabilities Pointer */
#define MCF_PCICR2 MCF_REG32(0x000B3C)
/* PCI Configuration Register 2 */
/* General Control/Status Registers */
#define MCF_PCIGSCR MCF_REG32(0x000B60)
/* Global Status/Control Register */
#define MCF_PCITBATR0 MCF_REG32(0x000B64)
/* Target Base Address Translation 0*/
#define MCF_PCITBATR1 MCF_REG32(0x000B68)
/* Target Base Address Translation 1*/
#define MCF_PCITCR MCF_REG32(0x000B6C)
/* Target Control Register */
#define MCF_PCIIW0BTAR MCF_REG32(0x000B70)
/* Initiator Window 0 Base Address */
#define MCF_PCIIW1BTAR MCF_REG32(0x000B74)
/* Initiator Window 1 Base Address */
#define MCF_PCIIW2BTAR MCF_REG32(0x000B78)
/* Initiator Window 2 Base Address */
#define MCF_PCIIWCR MCF_REG32(0x000B80)
/* Initiator Window Configuration */
#define MCF_PCIICR MCF_REG32(0x000B84)
/* Initiator Control Register */
#define MCF_PCIISR MCF_REG32(0x000B88)
/* Initiator Status Register */
#define MCF_PCICAR MCF_REG32(0x000BF8)
/* Configuration Address Register */
/* CommBus FIFO Transmit Interface Registers */
#define MCF_PCITPSR MCF_REG32(0x008400)
/* Tx Packet Size Register */
#define MCF_PCITSAR MCF_REG32(0x008404)
/* Tx Start Address Register */
#define MCF_PCITTCR MCF_REG32(0x008408)
/* Tx Transaction Control Register */
#define MCF_PCITER MCF_REG32(0x00840C)
/* Tx Enables Register */
#define MCF_PCITNAR MCF_REG32(0x008410)
/* Tx Next Address Register */
#define MCF_PCITLWR MCF_REG32(0x008414)
/* Tx Last Word Register */
#define MCF_PCITDCR MCF_REG32(0x008418)
/* Tx Done Counts Register */
#define MCF_PCITSR MCF_REG32(0x00841C)
/* Tx Status Register */
#define MCF_PCITFDR MCF_REG32(0x008440)
/* Tx FIFO Data Register */
#define MCF_PCITFSR MCF_REG32(0x008444)
/* Tx FIFO Status Register */
#define MCF_PCITFCR MCF_REG32(0x008448)
/* Tx FIFO Control Register */
#define MCF_PCITFAR MCF_REG32(0x00844C)
/* Tx FIFO Alarm Register */
#define MCF_PCITFRPR MCF_REG32(0x008450)
/* Tx FIFO Read Pointer Register */
#define MCF_PCITFWPR MCF_REG32(0x008454)
/* Tx FIFO Write Pointer Register */
/* CommBus FIFO Receive Interface Registers */
#define MCF_PCIRPSR MCF_REG32(0x008480)
/* Tx Packet Size Register */
#define MCF_PCIRSAR MCF_REG32(0x008484)
/* Tx Start Address Register */
#define MCF_PCIRTCR MCF_REG32(0x008488)
/* Tx Transaction Control Register */
#define MCF_PCIRER MCF_REG32(0x00848C)
/* Tx Enables Register */
#define MCF_PCIRNAR MCF_REG32(0x008490)
/* Tx Next Address Register */
#define MCF_PCIRDCR MCF_REG32(0x008498)
/* Tx Done Counts Register */
#define MCF_PCIRSR MCF_REG32(0x00849C)
/* Tx Status Register */
#define MCF_PCIRFDR MCF_REG32(0x0084C0)
/* Tx FIFO Data Register */
#define MCF_PCIRFSR MCF_REG32(0x0084C4)
/* Tx FIFO Status Register */
#define MCF_PCIRFCR MCF_REG32(0x0084C8)
/* Tx FIFO Control Register */
#define MCF_PCIRFAR MCF_REG32(0x0084CC)
/* Tx FIFO Alarm Register */
#define MCF_PCIRFRPR MCF_REG32(0x0084D0)
/* Tx FIFO Read Pointer Register */
#define MCF_PCIRFWPR MCF_REG32(0x0084D4)
/* Tx FIFO Write Pointer Register */
/* PCI Arbiter Registers */
#define MCF_PCIARB_PACR MCF_REG32(0x000C00)
#define MCF_PCIARB_PASR MCF_REG32(0x000C04)
/* Bit definitions and macros for MCF_PCIIDR */
#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0)
#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCISCR */
#define MCF_PCISCR_M (0x00000002)
#define MCF_PCISCR_B (0x00000004)
#define MCF_PCISCR_SP (0x00000008)
#define MCF_PCISCR_MW (0x00000010)
#define MCF_PCISCR_PER (0x00000040)
#define MCF_PCISCR_S (0x00000100)
#define MCF_PCISCR_F (0x00000200)
#define MCF_PCISCR_C (0x00100000)
#define MCF_PCISCR_66M (0x00200000)
#define MCF_PCISCR_R (0x00400000)
#define MCF_PCISCR_FC (0x00800000)
#define MCF_PCISCR_DP (0x01000000)
#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25)
#define MCF_PCISCR_TS (0x08000000)
#define MCF_PCISCR_TR (0x10000000)
#define MCF_PCISCR_MA (0x20000000)
#define MCF_PCISCR_SE (0x40000000)
#define MCF_PCISCR_PE (0x80000000)
/* Bit definitions and macros for MCF_PCICCRIR */
#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0)
#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
/* Bit definitions and macros for MCF_PCICR1 */
#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0)
#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCIBAR# */
#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18)
#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30)
/* Bit definitions and macros for MCF_PCICR2 */
#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0)
#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCIGSCR */
#define MCF_PCIGSCR_PR (0x00000001)
#define MCF_PCIGSCR_SEE (0x00001000)
#define MCF_PCIGSCR_PEE (0x00002000)
#define MCF_PCIGSCR_SE (0x10000000)
#define MCF_PCIGSCR_PE (0x20000000)
/* Bit definitions and macros for MCF_PCITBATR0 */
#define MCF_PCITBATR0_EN (0x00000001)
#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
/* Bit definitions and macros for MCF_PCITBATR1 */
#define MCF_PCITBATR1_EN (0x00000001)
#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30)
/* Bit definitions and macros for MCF_PCITCR */
#define MCF_PCITCR_P (0x00010000)
#define MCF_PCITCR_LD (0x01000000)
/* Bit definitions and macros for MCF_PCIIW0BTAR */
#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8)
#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16)
#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCIIW1BTAR */
#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8)
#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16)
#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCIIW2BTAR */
#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8)
#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16)
#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCIIWCR */
#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000)
#define MCF_PCIIWCR_WINCTRL0_E (0x01000000)
#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000)
#define MCF_PCIIWCR_WINCTRL1_E (0x00010000)
#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900)
#define MCF_PCIIWCR_WINCTRL2_E (0x00000100)
/* Bit definitions and macros for MCF_PCIICR */
#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0)
#define MCF_PCIICR_TAE (0x01000000)
#define MCF_PCIICR_IAE (0x02000000)
#define MCF_PCIICR_REE (0x04000000)
/* Bit definitions and macros for MCF_PCIISR */
#define MCF_PCIISR_TA (0x01000000)
#define MCF_PCIISR_IA (0x02000000)
#define MCF_PCIISR_RE (0x04000000)
/* Bit definitions and macros for MCF_PCICAR */
#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2)
#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
#define MCF_PCICAR_E (0x80000000)
/* Bit definitions and macros for MCF_PCITPSR */
#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCITTCR */
#define MCF_PCITTCR_DI (0x00000001)
#define MCF_PCITTCR_W (0x00000010)
#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_PCITER */
#define MCF_PCITER_NE (0x00010000)
#define MCF_PCITER_IAE (0x00020000)
#define MCF_PCITER_TAE (0x00040000)
#define MCF_PCITER_RE (0x00080000)
#define MCF_PCITER_SE (0x00100000)
#define MCF_PCITER_FEE (0x00200000)
#define MCF_PCITER_ME (0x01000000)
#define MCF_PCITER_BE (0x08000000)
#define MCF_PCITER_CM (0x10000000)
#define MCF_PCITER_RF (0x40000000)
#define MCF_PCITER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCITDCR */
#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCITSR */
#define MCF_PCITSR_IA (0x00010000)
#define MCF_PCITSR_TA (0x00020000)
#define MCF_PCITSR_RE (0x00040000)
#define MCF_PCITSR_SE (0x00080000)
#define MCF_PCITSR_FE (0x00100000)
#define MCF_PCITSR_BE1 (0x00200000)
#define MCF_PCITSR_BE2 (0x00400000)
#define MCF_PCITSR_BE3 (0x00800000)
#define MCF_PCITSR_NT (0x01000000)
/* Bit definitions and macros for MCF_PCITFSR */
#define MCF_PCITFSR_EMT (0x00010000)
#define MCF_PCITFSR_ALARM (0x00020000)
#define MCF_PCITFSR_FU (0x00040000)
#define MCF_PCITFSR_FR (0x00080000)
#define MCF_PCITFSR_OF (0x00100000)
#define MCF_PCITFSR_UF (0x00200000)
#define MCF_PCITFSR_RXW (0x00400000)
/* Bit definitions and macros for MCF_PCITFCR */
#define MCF_PCITFCR_OF_MSK (0x00080000)
#define MCF_PCITFCR_UF_MSK (0x00100000)
#define MCF_PCITFCR_RXW_MSK (0x00200000)
#define MCF_PCITFCR_FAE_MSK (0x00400000)
#define MCF_PCITFCR_IP_MSK (0x00800000)
#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24)
/* Bit definitions and macros for MCF_PCITFAR */
#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0)
/* Bit definitions and macros for MCF_PCITFRPR */
#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_PCITFWPR */
#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_PCIRPSR */
#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCIRTCR */
#define MCF_PCIRTCR_DI (0x00000001)
#define MCF_PCIRTCR_W (0x00000010)
#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
#define MCF_PCIRTCR_FB (0x00001000)
#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_PCIRER */
#define MCF_PCIRER_NE (0x00010000)
#define MCF_PCIRER_IAE (0x00020000)
#define MCF_PCIRER_TAE (0x00040000)
#define MCF_PCIRER_RE (0x00080000)
#define MCF_PCIRER_SE (0x00100000)
#define MCF_PCIRER_FEE (0x00200000)
#define MCF_PCIRER_ME (0x01000000)
#define MCF_PCIRER_BE (0x08000000)
#define MCF_PCIRER_CM (0x10000000)
#define MCF_PCIRER_FE (0x20000000)
#define MCF_PCIRER_RF (0x40000000)
#define MCF_PCIRER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCIRDCR */
#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCIRSR */
#define MCF_PCIRSR_IA (0x00010000)
#define MCF_PCIRSR_TA (0x00020000)
#define MCF_PCIRSR_RE (0x00040000)
#define MCF_PCIRSR_SE (0x00080000)
#define MCF_PCIRSR_FE (0x00100000)
#define MCF_PCIRSR_BE1 (0x00200000)
#define MCF_PCIRSR_BE2 (0x00400000)
#define MCF_PCIRSR_BE3 (0x00800000)
#define MCF_PCIRSR_NT (0x01000000)
/* Bit definitions and macros for MCF_PCIRFSR */
#define MCF_PCIRFSR_EMT (0x00010000)
#define MCF_PCIRFSR_ALARM (0x00020000)
#define MCF_PCIRFSR_FU (0x00040000)
#define MCF_PCIRFSR_FR (0x00080000)
#define MCF_PCIRFSR_OF (0x00100000)
#define MCF_PCIRFSR_UF (0x00200000)
#define MCF_PCIRFSR_RXW (0x00400000)
/* Bit definitions and macros for MCF_PCIRFCR */
#define MCF_PCIRFCR_OF_MSK (0x00080000)
#define MCF_PCIRFCR_UF_MSK (0x00100000)
#define MCF_PCIRFCR_RXW_MSK (0x00200000)
#define MCF_PCIRFCR_FAE_MSK (0x00400000)
#define MCF_PCIRFCR_IP_MSK (0x00800000)
#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24)
/* Bit definitions and macros for MCF_PCIRFAR */
#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0)
/* Bit definitions and macros for MCF_PCIRFRPR */
#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_PCIRFWPR */
#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_PCIARB_PACR */
#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
#define MCF_PCIARB_PACR_PKMD (0x40000000)
#define MCF_PCIARB_PACR_DS (0x80000000)
/* Bit definitions and macros for MCF_PCIARB_PASR */
#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
#endif /* __MCF548X_PCI_H__ */

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target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485psc.h
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@ -1,475 +0,0 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* File: mcf548x_psc.h
* Purpose: Register and bit definitions for the MCF548X
*
* Notes
*
*/
#ifndef __MCF548X_PSC_H__
#define __MCF548X_PSC_H__
/*********************************************************************
*
* Programmable Serial Controller (PSC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PSC_MR0 MCF_REG08(0x008600)
#define MCF_PSC_SR0 MCF_REG16(0x008604)
#define MCF_PSC_CSR0 MCF_REG08(0x008604)
#define MCF_PSC_CR0 MCF_REG08(0x008608)
#define MCF_PSC_RB0 MCF_REG32(0x00860C)
#define MCF_PSC_TB0 MCF_REG32(0x00860C)
#define MCF_PSC_TB_8BIT0 MCF_REG32(0x00860C)
#define MCF_PSC_TB_16BIT0 MCF_REG32(0x00860C)
#define MCF_PSC_TB_AC970 MCF_REG32(0x00860C)
#define MCF_PSC_IPCR0 MCF_REG08(0x008610)
#define MCF_PSC_ACR0 MCF_REG08(0x008610)
#define MCF_PSC_ISR0 MCF_REG16(0x008614)
#define MCF_PSC_IMR0 MCF_REG16(0x008614)
#define MCF_PSC_CTUR0 MCF_REG08(0x008618)
#define MCF_PSC_CTLR0 MCF_REG08(0x00861C)
#define MCF_PSC_IP0 MCF_REG08(0x008634)
#define MCF_PSC_OPSET0 MCF_REG08(0x008638)
#define MCF_PSC_OPRESET0 MCF_REG08(0x00863C)
#define MCF_PSC_SICR0 MCF_REG08(0x008640)
#define MCF_PSC_IRCR10 MCF_REG08(0x008644)
#define MCF_PSC_IRCR20 MCF_REG08(0x008648)
#define MCF_PSC_IRSDR0 MCF_REG08(0x00864C)
#define MCF_PSC_IRMDR0 MCF_REG08(0x008650)
#define MCF_PSC_IRFDR0 MCF_REG08(0x008654)
#define MCF_PSC_RFCNT0 MCF_REG16(0x008658)
#define MCF_PSC_TFCNT0 MCF_REG16(0x00865C)
#define MCF_PSC_RFSR0 MCF_REG16(0x008664)
#define MCF_PSC_TFSR0 MCF_REG16(0x008684)
#define MCF_PSC_RFCR0 MCF_REG32(0x008668)
#define MCF_PSC_TFCR0 MCF_REG32(0x008688)
#define MCF_PSC_RFAR0 MCF_REG16(0x00866E)
#define MCF_PSC_TFAR0 MCF_REG16(0x00868E)
#define MCF_PSC_RFRP0 MCF_REG16(0x008672)
#define MCF_PSC_TFRP0 MCF_REG16(0x008692)
#define MCF_PSC_RFWP0 MCF_REG16(0x008676)
#define MCF_PSC_TFWP0 MCF_REG16(0x008696)
#define MCF_PSC_RLRFP0 MCF_REG16(0x00867A)
#define MCF_PSC_TLRFP0 MCF_REG16(0x00869A)
#define MCF_PSC_RLWFP0 MCF_REG16(0x00867E)
#define MCF_PSC_TLWFP0 MCF_REG16(0x00869E)
#define MCF_PSC_MR1 MCF_REG08(0x008700)
#define MCF_PSC_SR1 MCF_REG16(0x008704)
#define MCF_PSC_CSR1 MCF_REG08(0x008704)
#define MCF_PSC_CR1 MCF_REG08(0x008708)
#define MCF_PSC_RB1 MCF_REG32(0x00870C)
#define MCF_PSC_TB1 MCF_REG32(0x00870C)
#define MCF_PSC_TB_8BIT1 MCF_REG32(0x00870C)
#define MCF_PSC_TB_16BIT1 MCF_REG32(0x00870C)
#define MCF_PSC_TB_AC971 MCF_REG32(0x00870C)
#define MCF_PSC_IPCR1 MCF_REG08(0x008710)
#define MCF_PSC_ACR1 MCF_REG08(0x008710)
#define MCF_PSC_ISR1 MCF_REG16(0x008714)
#define MCF_PSC_IMR1 MCF_REG16(0x008714)
#define MCF_PSC_CTUR1 MCF_REG08(0x008718)
#define MCF_PSC_CTLR1 MCF_REG08(0x00871C)
#define MCF_PSC_IP1 MCF_REG08(0x008734)
#define MCF_PSC_OPSET1 MCF_REG08(0x008738)
#define MCF_PSC_OPRESET1 MCF_REG08(0x00873C)
#define MCF_PSC_SICR1 MCF_REG08(0x008740)
#define MCF_PSC_IRCR11 MCF_REG08(0x008744)
#define MCF_PSC_IRCR21 MCF_REG08(0x008748)
#define MCF_PSC_IRSDR1 MCF_REG08(0x00874C)
#define MCF_PSC_IRMDR1 MCF_REG08(0x008750)
#define MCF_PSC_IRFDR1 MCF_REG08(0x008754)
#define MCF_PSC_RFCNT1 MCF_REG16(0x008758)
#define MCF_PSC_TFCNT1 MCF_REG16(0x00875C)
#define MCF_PSC_RFSR1 MCF_REG16(0x008764)
#define MCF_PSC_TFSR1 MCF_REG16(0x008784)
#define MCF_PSC_RFCR1 MCF_REG32(0x008768)
#define MCF_PSC_TFCR1 MCF_REG32(0x008788)
#define MCF_PSC_RFAR1 MCF_REG16(0x00876E)
#define MCF_PSC_TFAR1 MCF_REG16(0x00878E)
#define MCF_PSC_RFRP1 MCF_REG16(0x008772)
#define MCF_PSC_TFRP1 MCF_REG16(0x008792)
#define MCF_PSC_RFWP1 MCF_REG16(0x008776)
#define MCF_PSC_TFWP1 MCF_REG16(0x008796)
#define MCF_PSC_RLRFP1 MCF_REG16(0x00877A)
#define MCF_PSC_TLRFP1 MCF_REG16(0x00879A)
#define MCF_PSC_RLWFP1 MCF_REG16(0x00877E)
#define MCF_PSC_TLWFP1 MCF_REG16(0x00879E)
#define MCF_PSC_MR2 MCF_REG08(0x008800)
#define MCF_PSC_SR2 MCF_REG16(0x008804)
#define MCF_PSC_CSR2 MCF_REG08(0x008804)
#define MCF_PSC_CR2 MCF_REG08(0x008808)
#define MCF_PSC_RB2 MCF_REG32(0x00880C)
#define MCF_PSC_TB2 MCF_REG32(0x00880C)
#define MCF_PSC_TB_8BIT2 MCF_REG32(0x00880C)
#define MCF_PSC_TB_16BIT2 MCF_REG32(0x00880C)
#define MCF_PSC_TB_AC972 MCF_REG32(0x00880C)
#define MCF_PSC_IPCR2 MCF_REG08(0x008810)
#define MCF_PSC_ACR2 MCF_REG08(0x008810)
#define MCF_PSC_ISR2 MCF_REG16(0x008814)
#define MCF_PSC_IMR2 MCF_REG16(0x008814)
#define MCF_PSC_CTUR2 MCF_REG08(0x008818)
#define MCF_PSC_CTLR2 MCF_REG08(0x00881C)
#define MCF_PSC_IP2 MCF_REG08(0x008834)
#define MCF_PSC_OPSET2 MCF_REG08(0x008838)
#define MCF_PSC_OPRESET2 MCF_REG08(0x00883C)
#define MCF_PSC_SICR2 MCF_REG08(0x008840)
#define MCF_PSC_IRCR12 MCF_REG08(0x008844)
#define MCF_PSC_IRCR22 MCF_REG08(0x008848)
#define MCF_PSC_IRSDR2 MCF_REG08(0x00884C)
#define MCF_PSC_IRMDR2 MCF_REG08(0x008850)
#define MCF_PSC_IRFDR2 MCF_REG08(0x008854)
#define MCF_PSC_RFCNT2 MCF_REG16(0x008858)
#define MCF_PSC_TFCNT2 MCF_REG16(0x00885C)
#define MCF_PSC_RFSR2 MCF_REG16(0x008864)
#define MCF_PSC_TFSR2 MCF_REG16(0x008884)
#define MCF_PSC_RFCR2 MCF_REG32(0x008868)
#define MCF_PSC_TFCR2 MCF_REG32(0x008888)
#define MCF_PSC_RFAR2 MCF_REG16(0x00886E)
#define MCF_PSC_TFAR2 MCF_REG16(0x00888E)
#define MCF_PSC_RFRP2 MCF_REG16(0x008872)
#define MCF_PSC_TFRP2 MCF_REG16(0x008892)
#define MCF_PSC_RFWP2 MCF_REG16(0x008876)
#define MCF_PSC_TFWP2 MCF_REG16(0x008896)
#define MCF_PSC_RLRFP2 MCF_REG16(0x00887A)
#define MCF_PSC_TLRFP2 MCF_REG16(0x00889A)
#define MCF_PSC_RLWFP2 MCF_REG16(0x00887E)
#define MCF_PSC_TLWFP2 MCF_REG16(0x00889E)
#define MCF_PSC_MR3 MCF_REG08(0x008900)
#define MCF_PSC_SR3 MCF_REG16(0x008904)
#define MCF_PSC_CSR3 MCF_REG08(0x008904)
#define MCF_PSC_CR3 MCF_REG08(0x008908)
#define MCF_PSC_RB3 MCF_REG32(0x00890C)
#define MCF_PSC_TB3 MCF_REG32(0x00890C)
#define MCF_PSC_TB_8BIT3 MCF_REG32(0x00890C)
#define MCF_PSC_TB_16BIT3 MCF_REG32(0x00890C)
#define MCF_PSC_TB_AC973 MCF_REG32(0x00890C)
#define MCF_PSC_IPCR3 MCF_REG08(0x008910)
#define MCF_PSC_ACR3 MCF_REG08(0x008910)
#define MCF_PSC_ISR3 MCF_REG16(0x008914)
#define MCF_PSC_IMR3 MCF_REG16(0x008914)
#define MCF_PSC_CTUR3 MCF_REG08(0x008918)
#define MCF_PSC_CTLR3 MCF_REG08(0x00891C)
#define MCF_PSC_IP3 MCF_REG08(0x008934)
#define MCF_PSC_OPSET3 MCF_REG08(0x008938)
#define MCF_PSC_OPRESET3 MCF_REG08(0x00893C)
#define MCF_PSC_SICR3 MCF_REG08(0x008940)
#define MCF_PSC_IRCR13 MCF_REG08(0x008944)
#define MCF_PSC_IRCR23 MCF_REG08(0x008948)
#define MCF_PSC_IRSDR3 MCF_REG08(0x00894C)
#define MCF_PSC_IRMDR3 MCF_REG08(0x008950)
#define MCF_PSC_IRFDR3 MCF_REG08(0x008954)
#define MCF_PSC_RFCNT3 MCF_REG16(0x008958)
#define MCF_PSC_TFCNT3 MCF_REG16(0x00895C)
#define MCF_PSC_RFSR3 MCF_REG16(0x008964)
#define MCF_PSC_TFSR3 MCF_REG16(0x008984)
#define MCF_PSC_RFCR3 MCF_REG32(0x008968)
#define MCF_PSC_TFCR3 MCF_REG32(0x008988)
#define MCF_PSC_RFAR3 MCF_REG16(0x00896E)
#define MCF_PSC_TFAR3 MCF_REG16(0x00898E)
#define MCF_PSC_RFRP3 MCF_REG16(0x008972)
#define MCF_PSC_TFRP3 MCF_REG16(0x008992)
#define MCF_PSC_RFWP3 MCF_REG16(0x008976)
#define MCF_PSC_TFWP3 MCF_REG16(0x008996)
#define MCF_PSC_RLRFP3 MCF_REG16(0x00897A)
#define MCF_PSC_TLRFP3 MCF_REG16(0x00899A)
#define MCF_PSC_RLWFP3 MCF_REG16(0x00897E)
#define MCF_PSC_TLWFP3 MCF_REG16(0x00899E)
#define MCF_PSC_MR(x) MCF_REG08(0x008600+((x)*0x100))
#define MCF_PSC_SR(x) MCF_REG16(0x008604+((x)*0x100))
#define MCF_PSC_CSR(x) MCF_REG08(0x008604+((x)*0x100))
#define MCF_PSC_CR(x) MCF_REG08(0x008608+((x)*0x100))
#define MCF_PSC_RB(x) MCF_REG32(0x00860C+((x)*0x100))
#define MCF_PSC_TB(x) MCF_REG32(0x00860C+((x)*0x100))
#define MCF_PSC_TB_8BIT(x) MCF_REG32(0x00860C+((x)*0x100))
#define MCF_PSC_TB_16BIT(x) MCF_REG32(0x00860C+((x)*0x100))
#define MCF_PSC_TB_AC97(x) MCF_REG32(0x00860C+((x)*0x100))
#define MCF_PSC_IPCR(x) MCF_REG08(0x008610+((x)*0x100))
#define MCF_PSC_ACR(x) MCF_REG08(0x008610+((x)*0x100))
#define MCF_PSC_ISR(x) MCF_REG16(0x008614+((x)*0x100))
#define MCF_PSC_IMR(x) MCF_REG16(0x008614+((x)*0x100))
#define MCF_PSC_CTUR(x) MCF_REG08(0x008618+((x)*0x100))
#define MCF_PSC_CTLR(x) MCF_REG08(0x00861C+((x)*0x100))
#define MCF_PSC_IP(x) MCF_REG08(0x008634+((x)*0x100))
#define MCF_PSC_OPSET(x) MCF_REG08(0x008638+((x)*0x100))
#define MCF_PSC_OPRESET(x) MCF_REG08(0x00863C+((x)*0x100))
#define MCF_PSC_SICR(x) MCF_REG08(0x008640+((x)*0x100))
#define MCF_PSC_IRCR1(x) MCF_REG08(0x008644+((x)*0x100))
#define MCF_PSC_IRCR2(x) MCF_REG08(0x008648+((x)*0x100))
#define MCF_PSC_IRSDR(x) MCF_REG08(0x00864C+((x)*0x100))
#define MCF_PSC_IRMDR(x) MCF_REG08(0x008650+((x)*0x100))
#define MCF_PSC_IRFDR(x) MCF_REG08(0x008654+((x)*0x100))
#define MCF_PSC_RFCNT(x) MCF_REG16(0x008658+((x)*0x100))
#define MCF_PSC_TFCNT(x) MCF_REG16(0x00865C+((x)*0x100))
#define MCF_PSC_RFSR(x) MCF_REG16(0x008664+((x)*0x100))
#define MCF_PSC_TFSR(x) MCF_REG16(0x008684+((x)*0x100))
#define MCF_PSC_RFCR(x) MCF_REG32(0x008668+((x)*0x100))
#define MCF_PSC_TFCR(x) MCF_REG32(0x008688+((x)*0x100))
#define MCF_PSC_RFAR(x) MCF_REG16((0x00866E)+((x)*0x100))
#define MCF_PSC_TFAR(x) MCF_REG16((0x00868E)+((x)*0x100))
#define MCF_PSC_RFRP(x) MCF_REG16(0x008672+((x)*0x100))
#define MCF_PSC_TFRP(x) MCF_REG16(0x008692+((x)*0x100))
#define MCF_PSC_RFWP(x) MCF_REG16(0x008676+((x)*0x100))
#define MCF_PSC_TFWP(x) MCF_REG16(0x008696+((x)*0x100))
#define MCF_PSC_RLRFP(x) MCF_REG16(0x00867A+((x)*0x100))
#define MCF_PSC_TLRFP(x) MCF_REG16(0x00869A+((x)*0x100))
#define MCF_PSC_RLWFP(x) MCF_REG16(0x00867E+((x)*0x100))
#define MCF_PSC_TLWFP(x) MCF_REG16(0x00869E+((x)*0x100))
/* Bit definitions and macros for MCF_PSC_MR */
#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0)
#define MCF_PSC_MR_PT (0x04)
#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3)
#define MCF_PSC_MR_ERR (0x20)
#define MCF_PSC_MR_RXIRQ (0x40)
#define MCF_PSC_MR_RXRTS (0x80)
#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0)
#define MCF_PSC_MR_TXCTS (0x10)
#define MCF_PSC_MR_TXRTS (0x20)
#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6)
#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C)
#define MCF_PSC_MR_PM_MULTI_DATA (0x18)
#define MCF_PSC_MR_PM_NONE (0x10)
#define MCF_PSC_MR_PM_FORCE_HI (0x0C)
#define MCF_PSC_MR_PM_FORCE_LO (0x08)
#define MCF_PSC_MR_PM_ODD (0x04)
#define MCF_PSC_MR_PM_EVEN (0x00)
#define MCF_PSC_MR_BC_5 (0x00)
#define MCF_PSC_MR_BC_6 (0x01)
#define MCF_PSC_MR_BC_7 (0x02)
#define MCF_PSC_MR_BC_8 (0x03)
#define MCF_PSC_MR_CM_NORMAL (0x00)
#define MCF_PSC_MR_CM_ECHO (0x40)
#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80)
#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0)
#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07)
#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08)
#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F)
/* Bit definitions and macros for MCF_PSC_SR */
#define MCF_PSC_SR_ERR (0x0040)
#define MCF_PSC_SR_CDE_DEOF (0x0080)
#define MCF_PSC_SR_RXRDY (0x0100)
#define MCF_PSC_SR_FU (0x0200)
#define MCF_PSC_SR_TXRDY (0x0400)
#define MCF_PSC_SR_TXEMP_URERR (0x0800)
#define MCF_PSC_SR_OE (0x1000)
#define MCF_PSC_SR_PE_CRCERR (0x2000)
#define MCF_PSC_SR_FE_PHYERR (0x4000)
#define MCF_PSC_SR_RB_NEOF (0x8000)
/* Bit definitions and macros for MCF_PSC_CSR */
#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0)
#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4)
#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0)
#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0)
#define MCF_PSC_CSR_RCSEL_CTM (0xF0)
#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D)
#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E)
#define MCF_PSC_CSR_TCSEL_CTM (0x0F)
/* Bit definitions and macros for MCF_PSC_CR */
#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0)
#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2)
#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4)
#define MCF_PSC_CR_NONE (0x00)
#define MCF_PSC_CR_STOP_BREAK (0x70)
#define MCF_PSC_CR_START_BREAK (0x60)
#define MCF_PSC_CR_BKCHGINT (0x50)
#define MCF_PSC_CR_RESET_ERROR (0x40)
#define MCF_PSC_CR_RESET_TX (0x30)
#define MCF_PSC_CR_RESET_RX (0x20)
#define MCF_PSC_CR_RESET_MR (0x10)
#define MCF_PSC_CR_TX_DISABLED (0x08)
#define MCF_PSC_CR_TX_ENABLED (0x04)
#define MCF_PSC_CR_RX_DISABLED (0x02)
#define MCF_PSC_CR_RX_ENABLED (0x01)
/* Bit definitions and macros for MCF_PSC_TB_8BIT */
#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0)
#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8)
#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16)
#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PSC_TB_16BIT */
#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0)
#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PSC_TB_AC97 */
#define MCF_PSC_TB_AC97_SOF (0x00000800)
#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12)
/* Bit definitions and macros for MCF_PSC_IPCR */
#define MCF_PSC_IPCR_RESERVED (0x0C)
#define MCF_PSC_IPCR_CTS (0x0D)
#define MCF_PSC_IPCR_D_CTS (0x1C)
#define MCF_PSC_IPCR_SYNC (0x8C)
/* Bit definitions and macros for MCF_PSC_ACR */
#define MCF_PSC_ACR_IEC0 (0x01)
#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4)
#define MCF_PSC_ACR_BRG (0x80)
/* Bit definitions and macros for MCF_PSC_ISR */
#define MCF_PSC_ISR_ERR (0x0040)
#define MCF_PSC_ISR_DEOF (0x0080)
#define MCF_PSC_ISR_TXRDY (0x0100)
#define MCF_PSC_ISR_RXRDY_FU (0x0200)
#define MCF_PSC_ISR_DB (0x0400)
#define MCF_PSC_ISR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_IMR */
#define MCF_PSC_IMR_ERR (0x0040)
#define MCF_PSC_IMR_DEOF (0x0080)
#define MCF_PSC_IMR_TXRDY (0x0100)
#define MCF_PSC_IMR_RXRDY_FU (0x0200)
#define MCF_PSC_IMR_DB (0x0400)
#define MCF_PSC_IMR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_IP */
#define MCF_PSC_IP_CTS (0x01)
#define MCF_PSC_IP_TGL (0x40)
#define MCF_PSC_IP_LWPR_B (0x80)
/* Bit definitions and macros for MCF_PSC_OPSET */
#define MCF_PSC_OPSET_RTS (0x01)
/* Bit definitions and macros for MCF_PSC_OPRESET */
#define MCF_PSC_OPRESET_RTS (0x01)
/* Bit definitions and macros for MCF_PSC_SICR */
#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0)
#define MCF_PSC_SICR_SHDIR (0x10)
#define MCF_PSC_SICR_DTS (0x20)
#define MCF_PSC_SICR_AWR (0x40)
#define MCF_PSC_SICR_ACRB (0x80)
#define MCF_PSC_SICR_SIM_UART (0x00)
#define MCF_PSC_SICR_SIM_MODEM8 (0x01)
#define MCF_PSC_SICR_SIM_MODEM16 (0x02)
#define MCF_PSC_SICR_SIM_AC97 (0x03)
#define MCF_PSC_SICR_SIM_SIR (0x04)
#define MCF_PSC_SICR_SIM_MIR (0x05)
#define MCF_PSC_SICR_SIM_FIR (0x06)
/* Bit definitions and macros for MCF_PSC_IRCR1 */
#define MCF_PSC_IRCR1_SPUL (0x01)
#define MCF_PSC_IRCR1_SIPEN (0x02)
#define MCF_PSC_IRCR1_FD (0x04)
/* Bit definitions and macros for MCF_PSC_IRCR2 */
#define MCF_PSC_IRCR2_NXTEOF (0x01)
#define MCF_PSC_IRCR2_ABORT (0x02)
#define MCF_PSC_IRCR2_SIPREQ (0x04)
/* Bit definitions and macros for MCF_PSC_IRMDR */
#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0)
#define MCF_PSC_IRMDR_FREQ (0x80)
/* Bit definitions and macros for MCF_PSC_IRFDR */
#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0)
/* Bit definitions and macros for MCF_PSC_RFCNT */
#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFCNT */
#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RFSR */
#define MCF_PSC_RFSR_EMT (0x0001)
#define MCF_PSC_RFSR_ALARM (0x0002)
#define MCF_PSC_RFSR_FU (0x0004)
#define MCF_PSC_RFSR_FRMRY (0x0008)
#define MCF_PSC_RFSR_OF (0x0010)
#define MCF_PSC_RFSR_UF (0x0020)
#define MCF_PSC_RFSR_RXW (0x0040)
#define MCF_PSC_RFSR_FAE (0x0080)
#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8)
#define MCF_PSC_RFSR_TAG (0x1000)
#define MCF_PSC_RFSR_TXW (0x4000)
#define MCF_PSC_RFSR_IP (0x8000)
#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800)
#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400)
#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200)
#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100)
/* Bit definitions and macros for MCF_PSC_TFSR */
#define MCF_PSC_TFSR_EMT (0x0001)
#define MCF_PSC_TFSR_ALARM (0x0002)
#define MCF_PSC_TFSR_FU (0x0004)
#define MCF_PSC_TFSR_FRMRY (0x0008)
#define MCF_PSC_TFSR_OF (0x0010)
#define MCF_PSC_TFSR_UF (0x0020)
#define MCF_PSC_TFSR_RXW (0x0040)
#define MCF_PSC_TFSR_FAE (0x0080)
#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8)
#define MCF_PSC_TFSR_TAG (0x1000)
#define MCF_PSC_TFSR_TXW (0x4000)
#define MCF_PSC_TFSR_IP (0x8000)
#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800)
#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400)
#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200)
#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100)
/* Bit definitions and macros for MCF_PSC_RFCR */
#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
#define MCF_PSC_RFCR_TXW_MSK (0x00040000)
#define MCF_PSC_RFCR_OF_MSK (0x00080000)
#define MCF_PSC_RFCR_UF_MSK (0x00100000)
#define MCF_PSC_RFCR_RXW_MSK (0x00200000)
#define MCF_PSC_RFCR_FAE_MSK (0x00400000)
#define MCF_PSC_RFCR_IP_MSK (0x00800000)
#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24)
#define MCF_PSC_RFCR_FRMEN (0x08000000)
#define MCF_PSC_RFCR_TIMER (0x10000000)
#define MCF_PSC_RFCR_WRITETAG (0x20000000)
#define MCF_PSC_RFCR_SHADOW (0x80000000)
/* Bit definitions and macros for MCF_PSC_TFCR */
#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
#define MCF_PSC_TFCR_TXW_MSK (0x00040000)
#define MCF_PSC_TFCR_OF_MSK (0x00080000)
#define MCF_PSC_TFCR_UF_MSK (0x00100000)
#define MCF_PSC_TFCR_RXW_MSK (0x00200000)
#define MCF_PSC_TFCR_FAE_MSK (0x00400000)
#define MCF_PSC_TFCR_IP_MSK (0x00800000)
#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24)
#define MCF_PSC_TFCR_FRMEN (0x08000000)
#define MCF_PSC_TFCR_TIMER (0x10000000)
#define MCF_PSC_TFCR_WRITETAG (0x20000000)
#define MCF_PSC_TFCR_SHADOW (0x80000000)
/* Bit definitions and macros for MCF_PSC_RFAR */
#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFAR */
#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RFRP */
#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFRP */
#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RFWP */
#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFWP */
#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RLRFP */
#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TLRFP */
#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RLWFP */
#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TLWFP */
#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0)
/********************************************************************/
#endif /* __MCF548X_PSC_H__ */

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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef M5485SEC_H
#define M5484SEC_H
#define SEC_EUACR_U MCF_REG32(0x21000)
#define SEC_EUACR_L MCF_REG32(0x21004)
#define SEC_EUASR_U MCF_REG32(0x21028)
#define SEC_EUASR_L MCF_REG32(0x2102C)
#define SEC_SMCR MCF_REG32(0x21030)
#define SEC_SISR_U MCF_REG32(0x21010)
#define SEC_SISR_L MCF_REG32(0x21014)
#define SEC_SICR_U MCF_REG32(0x21018)
#define SEC_SICR_L MCF_REG32(0x2101C)
#define SEC_SIMR_U MCF_REG32(0x21008)
#define SEC_SIMR_L MCF_REG32(0x2100C)
#define SEC_SID MCF_REG32(0x21020)
#define SEC_SMCR_RESET 0x01000000
#define SEC_SIMR_MASK_U 0x00000000
#define SEC_SIMR_MASK_L 0x03333340
#define SEC_CC0_FR MCF_REG32(0x2204C)
#define SEC_CC0_CR MCF_REG32(0x2200C)
#define SEC_CC0_CDPR MCF_REG32(0x22044)
#define SEC_CC0_PSR_U MCF_REG32(0x22010)
#define SEC_CC0_PSR_L MCF_REG32(0x22014)
#define SEC_CC1_FR MCF_REG32(0x2304C)
#define SEC_CC1_CR MCF_REG32(0x2300C)
#define SEC_CC1_CDPR MCF_REG32(0x23044)
#define SEC_CC1_PSR_U MCF_REG32(0x23010)
#define SEC_CC1_PSR_L MCF_REG32(0x23014)
#define SEC_CC_CR_RESET 0x00000001
#define SEC_CC_CR_CONFIGURATION 0x0000001E
#define SEC_CC_PSR_U_ERR_CH0 0x20000000
#define SEC_CC_PSR_U_ERR_CH1 0x80000000
#define SEC_CC_PSR_U_DN_CH0 0x10000000
#define SEC_CC_PSR_U_DN_CH1 0x40000000
#define SEC_DEU_DRCR MCF_REG32(0x2A018)
#define SEC_DEU_DSR MCF_REG32(0x2A028)
#define SEC_DEU_DISR MCF_REG32(0x2A030)
#define SEC_DEU_DIMR MCF_REG32(0x2A038)
#define SEC_DEU_DRCR_RESET 0x01000000
#define SEC_DEU_DSR_RD 0x01000000
#define SEC_DEU_DIMR_MASK 0xF63F0000
#define SEC_AFEU_AFRCR MCF_REG32(0x28018)
#define SEC_AFEU_AFSR MCF_REG32(0x28028)
#define SEC_AFEU_AFISR MCF_REG32(0x28030)
#define SEC_AFEU_AFIMR MCF_REG32(0x28038)
#define SEC_AFEU_AFRCR_RESET 0x01000000
#define SEC_AFEU_AFSR_RD 0x01000000
#define SEC_AFEU_AFIMR_MASK 0xF61F0000
#define SEC_MDEU_MDRCR MCF_REG32(0x2C018)
#define SEC_MDEU_MDSR MCF_REG32(0x2C028)
#define SEC_MDEU_MDISR MCF_REG32(0x2C030)
#define SEC_MDEU_MDIMR MCF_REG32(0x2C038)
#define SEC_MDEU_MDRCR_RESET 0x01000000
#define SEC_MDEU_MDSR_RD 0x01000000
#define SEC_MDEU_MDIMR_MASK 0xC41F0000
#define SEC_RNG_RNGRCR MCF_REG32(0x2E018)
#define SEC_RNG_RNGSR MCF_REG32(0x2E028)
#define SEC_RNG_RNGISR MCF_REG32(0x2E030)
#define SEC_RNG_RNGIMR MCF_REG32(0x2E038)
#define SEC_RNG_RNGRCR_RESET 0x01000000
#define SEC_RNG_RNGSR_RD 0x01000000
#define SEC_RNG_RNGIMR_MASK 0xC2100000
#define SEC_AESU_AESRCR MCF_REG32(0x32018)
#define SEC_AESU_AESSR MCF_REG32(0x32028)
#define SEC_AESU_AESISR MCF_REG32(0x32030)
#define SEC_AESU_AESIMR MCF_REG32(0x32038)
#define SEC_AESU_AESRCR_RESET 0x01000000
#define SEC_AESU_AESSR_RD 0x01000000
#define SEC_AESU_AESIMR_MASK 0xF61F0000
#define SEC_DESC_NUM 20
#define SEC_CHANNEL_NUMBER 2
#define SEC_MAX_BUF_SIZE 32*1024
#define SEC_INIT_TIMEOUT 1*HZ
#define SEC_INTERRUPT 37
/* Header descriptor values*/
#define SEC_ALG_ENCR_DES_ECB_SINGLE 0x20100010
#define SEC_ALG_DECR_DES_ECB_SINGLE 0x20000010
#define SEC_ALG_ENCR_DES_ECB_TRIPLE 0x20300010
#define SEC_ALG_DECR_DES_ECB_TRIPLE 0x20200010
#define SEC_ALG_ENCR_DES_CBC_SINGLE 0x20500010
#define SEC_ALG_DECR_DES_CBC_SINGLE 0x20400010
#define SEC_ALG_ENCR_DES_CBC_TRIPLE 0x20700010
#define SEC_ALG_DECR_DES_CBC_TRIPLE 0x20600010
#define SEC_ALG_MDEU_SHA256 0x30500010
#define SEC_ALG_MDEU_MD5 0x30600010
#define SEC_ALG_MDEU_SHA 0x30400010
#define SEC_ALG_MDEU_SHA256_HMAC 0x31D00010
#define SEC_ALG_MDEU_MD5_HMAC 0x31E00010
#define SEC_ALG_MDEU_SHA_HMAC 0x31C00010
#define SEC_ALG_RNG 0x40000010
#define SEC_ALG_AFEU_KEY 0x10200050
#define SEC_ALG_AFEU_CONTEXT 0x10700050
#define SEC_ALG_ENCR_AESU_CBC 0x60300010
#define SEC_ALG_DECR_AESU_CBC 0x60200010
#define SEC_ALG_ENCR_AESU_ECB 0x60100010
#define SEC_ALG_DECR_AESU_ECB 0x60000010
#define SEC_ALG_AESU_CTR 0x60600010
#define SEC_DESCHEAD_ERROR 0xFE000000
#define SEC_DESCHEAD_COMPLETED 0xFF000000
#define SEC_DEVICE_NAME "cfsec"
/*!!! This number must be changed*/
#define SEC_MAJOR 130
#define SEC_DEV_BUF 1024
#define SEC_DEV_KEY_LEN 64
#define SEC_DEV_VECTOR_LEN 259
#define SEC_AES_BLCK_LEN 16
#define SEC_DES_BLCK_LEN 8
/* Descriptor structure of SEC*/
struct sec_descriptor {
volatile unsigned long secdesc_header;
unsigned long secdesc_len1;
void *secdesc_ptr1;
unsigned long secdesc_iv_in_len;
void *secdesc_iv_in_ptr;
unsigned long secdesc_key_len;
void *secdesc_key_ptr;
unsigned long secdesc_data_in_len;
void *secdesc_data_in_ptr;
unsigned long secdesc_data_out_len;
void *secdesc_data_out_ptr;
unsigned long secdesc_iv_out_len;
void *secdesc_iv_out_ptr;
unsigned long secdesc_len7;
void *secdesc_ptr7;
void *secdesc_ptrnext;
};
struct sec_device_data {
unsigned char secdev_inbuf[SEC_DEV_BUF];
unsigned char secdev_outbuf[SEC_DEV_BUF];
unsigned char secdev_key[SEC_DEV_KEY_LEN];
unsigned char secdev_iv[SEC_DEV_VECTOR_LEN];
unsigned char secdev_ov[SEC_DEV_VECTOR_LEN];
struct sec_descriptor *secdev_desc;
};
struct sec_descriptor *sec_desc_alloc(void);
inline void sec_desc_free(struct sec_descriptor *desc);
int sec_execute(int channel, struct sec_descriptor *desc, int timeout);
int sec_nonblock_execute(struct sec_descriptor *desc);
#endif

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/*
* m5485sim.h -- ColdFire 547x/548x System Integration Unit support.
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef m5485sim_h
#define m5485sim_h
/*
* System Integration Unit Registers
*/
#define MCF_SDRAMDS MCF_REG32(0x000004)
/* SDRAM Drive Strength */
#define MCF_SBCR MCF_REG32(0x000010)
/* System Breakpoint Control */
#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4))
/* SDRAM Chip Select X */
#define MCF_SECSACR MCF_REG32(0x000038)
/* Sequential Access Control */
#define MCF_RSR MCF_REG32(0x000044)
/* Reset Status */
#define MCF_JTAGID MCF_REG32(0x000050)
/* JTAG Device Identification */
#define MCF_XARB_PRIEN MCF_REG32(0x000264)
/* Arbiter master pri enable */
#define MCF_XARB_PRI MCF_REG32(0x000268)
/* Arbiter master pri levels */
/*
* FlexBus Chip Selects Registers
*/
#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC))
#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC))
#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC))
/*
* Interrupt Controller Registers
*/
#define MCF_IPRH MCF_REG32(0x000700)
#define MCF_IPRL MCF_REG32(0x000704)
#define MCF_IMRH MCF_REG32(0x000708)
#define MCF_IMRL MCF_REG32(0x00070C)
#define MCF_INTFRCH MCF_REG32(0x000710)
#define MCF_INTFRCL MCF_REG32(0x000714)
#define MCF_IRLR MCF_REG08(0x000718)
#define MCF_IACKLPR MCF_REG08(0x000719)
#define MCF_SWIACK MCF_REG08(0x0007E0)
#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004))
#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001))
/*
* Slice Timers Registers
*/
#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010))
#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010))
#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010))
#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010))
/*
* Interrupt sources
*/
#define ISC_EPORT_Fn(x) (x)
/* EPORT Interrupts */
#define ISC_USB_EPn(x) (15+(x))
/* USB Endopint */
#define ISC_USB_ISR (22)
/* USB General source */
#define ISC_USB_AISR (22)
/* USB core source */
#define ISC_DSPI_OVRFW (25)
/* DSPI overflow */
#define ISC_DSPI_RFOF (26)
#define ISC_DSPI_RFDF (27)
#define ISC_DSPI_TFUF (28)
#define ISC_DSPI_TCF (29)
#define ISC_DSPI_TFFF (30)
#define ISC_DSPI_EOQF (31)
#define ISC_PSCn(x) (35-(x))
#define ISC_COMM_TIM (36)
#define ISC_SEC (37)
#define ISC_FEC1 (38)
#define ISC_FEC0 (39)
#define ISC_I2C (40)
#define ISC_PCI_ARB (41)
#define ISC_PCI_CB (42)
#define ISC_PCI_XLB (43)
#define ISC_DMA (48)
#define ISC_CANn_ERR(x) (49+(6*(x)))
#define ISC_CANn_BUSOFF(x) (50+(6*(x)))
#define ISC_CANn_MBOR(x) (51+(6*(x)))
#define ISC_CAN0_WAKEIN (52)
#define ISC_SLTn(x) (54-(x))
#define ISC_GPTn(x) (62-(x))
/*
* Interrupt level and priorities
*/
#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3))
#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2))
#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1))
#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0))
#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7))
#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6))
#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5))
#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4))
#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3))
#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2))
#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1))
#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x)))
#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7))
#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6))
#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5))
#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4))
#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3))
#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2))
#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1))
#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0))
#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7))
#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6))
#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5))
#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4))
#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3))
#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2))
#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1))
#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0))
#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7))
#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3)))
#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3))
#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2))
#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1))
#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0))
/********************************************************************/
/*
* System Integration Unit Bitfields
*/
/* SBCR */
#define MCF_SBCR_PIN2DSPI (0x08000000)
#define MCF_SBCR_DMA2CPU (0x10000000)
#define MCF_SBCR_CPU2DMA (0x20000000)
#define MCF_SBCR_PIN2DMA (0x40000000)
#define MCF_SBCR_PIN2CPU (0x80000000)
/* SECSACR */
#define MCF_SECSACR_SEQEN (0x00000001)
/* RSR */
#define MCF_RSR_RST (0x00000001)
#define MCF_RSR_RSTWD (0x00000002)
#define MCF_RSR_RSTJTG (0x00000008)
/* JTAGID */
#define MCF_JTAGID_REV (0xF0000000)
#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF)
#define MCF_JTAGID_MCF5485 (0x0800C01D)
#define MCF_JTAGID_MCF5484 (0x0800D01D)
#define MCF_JTAGID_MCF5483 (0x0800E01D)
#define MCF_JTAGID_MCF5482 (0x0800F01D)
#define MCF_JTAGID_MCF5481 (0x0801001D)
#define MCF_JTAGID_MCF5480 (0x0801101D)
#define MCF_JTAGID_MCF5475 (0x0801201D)
#define MCF_JTAGID_MCF5474 (0x0801301D)
#define MCF_JTAGID_MCF5473 (0x0801401D)
#define MCF_JTAGID_MCF5472 (0x0801501D)
#define MCF_JTAGID_MCF5471 (0x0801601D)
#define MCF_JTAGID_MCF5470 (0x0801701D)
/*
* Interrupt Controller Bitfields
*/
#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1)
#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0)
#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
#define MCF_ICR_IP(x) (((x)&0x07)<<0)
#define MCF_ICR_IL(x) (((x)&0x07)<<3)
/*
* Slice Timers Bitfields
*/
#define MCF_SCR_TEN (0x01000000)
#define MCF_SCR_IEN (0x02000000)
#define MCF_SCR_RUN (0x04000000)
#define MCF_SSR_ST (0x01000000)
#define MCF_SSR_BE (0x02000000)
/*
* Some needed coldfire registers
*/
#define MCF_PAR_PCIBG MCF_REG16(0x000A48)
#define MCF_PAR_PCIBR MCF_REG16(0x000A4A)
#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3))
#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44)
#define MCF_PAR_DSPI MCF_REG16(0x000A50)
#define MCF_PAR_TIMER MCF_REG08(0X000A52)
#define MCF_EPPAR MCF_REG16(0x000F00)
#define MCF_EPDDR MCF_REG08(0x000F04)
#define MCF_EPIER MCF_REG08(0x000F05)
#define MCF_EPFR MCF_REG08(0x000F0C)
/*
* Some GPIO bitfields
*/
#define MCF_PAR_SDA (0x0008)
#define MCF_PAR_SCL (0x0004)
#define MCF_PAR_PSC_TXD (0x04)
#define MCF_PAR_PSC_RXD (0x08)
#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
#define MCF_PAR_PSC_CTS_GPIO (0x00)
#define MCF_PAR_PSC_CTS_BCLK (0x80)
#define MCF_PAR_PSC_CTS_CTS (0xC0)
#define MCF_PAR_PSC_RTS_GPIO (0x00)
#define MCF_PAR_PSC_RTS_FSYNC (0x20)
#define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40)
/*
* FlexCAN Module Configuration Register
*/
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_NOTRDY (0x08000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_MAXMB (0x0F)
/*
* FlexCAN Control Register
*/
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SAMP(x) (((x)&0x01)<<7)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) ((x)&0x07)
/*
* FlexCAN Error Counter Register
*/
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
#define ERRCNT_TXECTR(x) ((x)&0xFF)
/*
* FlexCAN Error and Status Register
*/
#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
/*
* Interrupt Mask Register
*/
#define IMASK_BUF15M (0x8000)
#define IMASK_BUF14M (0x4000)
#define IMASK_BUF13M (0x2000)
#define IMASK_BUF12M (0x1000)
#define IMASK_BUF11M (0x0800)
#define IMASK_BUF10M (0x0400)
#define IMASK_BUF9M (0x0200)
#define IMASK_BUF8M (0x0100)
#define IMASK_BUF7M (0x0080)
#define IMASK_BUF6M (0x0040)
#define IMASK_BUF5M (0x0020)
#define IMASK_BUF4M (0x0010)
#define IMASK_BUF3M (0x0008)
#define IMASK_BUF2M (0x0004)
#define IMASK_BUF1M (0x0002)
#define IMASK_BUF0M (0x0001)
#define IMASK_BUFnM(x) (0x1<<(x))
#define IMASK_BUFF_ENABLE_ALL (0xFFFF)
#define IMASK_BUFF_DISABLE_ALL (0x0000)
/*
* Interrupt Flag Register
*/
#define IFLAG_BUF15M (0x8000)
#define IFLAG_BUF14M (0x4000)
#define IFLAG_BUF13M (0x2000)
#define IFLAG_BUF12M (0x1000)
#define IFLAG_BUF11M (0x0800)
#define IFLAG_BUF10M (0x0400)
#define IFLAG_BUF9M (0x0200)
#define IFLAG_BUF8M (0x0100)
#define IFLAG_BUF7M (0x0080)
#define IFLAG_BUF6M (0x0040)
#define IFLAG_BUF5M (0x0020)
#define IFLAG_BUF4M (0x0010)
#define IFLAG_BUF3M (0x0008)
#define IFLAG_BUF2M (0x0004)
#define IFLAG_BUF1M (0x0002)
#define IFLAG_BUF0M (0x0001)
#define IFLAG_BUFF_SET_ALL (0xFFFF)
#define IFLAG_BUFF_CLEAR_ALL (0x0000)
#define IFLAG_BUFnM(x) (0x1<<(x))
/*
* Message Buffers
*/
#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
#define MB_CNT_SRR (0x00400000)
#define MB_CNT_IDE (0x00200000)
#define MB_CNT_RTR (0x00100000)
#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
#define MB_ID_STD (0x07FF)
#define MB_ID_EXT (0x1FFFFFFF)
#define MB_CODE_MASK (0xF0FFFFFF)
#define CAN_MB 16
#define PDEV_MAX 2
/*
* Some used coldfire values
*/
#define MCF_EPIER_EPIE(x) (0x01 << (x))
#define MCF_EPPAR_EPPAx_FALLING (2)
#define MCF_EPPAR_EPPA(n, x) (((x)&0x0003) << (2*n))
#endif /* m5485sim_h */

12
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sram.h
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#ifndef SYS_SRAM_H
#define SYS_SRAM_H
#define SYS_SRAM_DMA_START (MCF_MBAR + 0x10000)
#define SYS_SRAM_DMA_SIZE 8192
#define SYS_SRAM_FEC_START (SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE)
#define SYS_SRAM_FEC_SIZE 2048
#define SYS_SRAM_SEC_START (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE)
#define SYS_SRAM_SEC_SIZE 1280
#endif /* SYS_SRAM_H */

204
target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/mcffec.h
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/*
* Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All rights reserved.
* Author: Chenghu Wu <b16972@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __MCFFEC_H__
#define __MCFFEC_H
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <asm/pgtable.h>
/* The FEC stores dest/src/type, data, and checksum for receive packets.
*/
#define PKT_MAXBUF_SIZE 1518
/*
* The 5270/5271/5280/5282/532x RX control register also contains maximum frame
* size bits. Other FEC hardware does not, so we need to take that into
* account when setting it.
*/
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
defined(CONFIG_M537x) || defined(CONFIG_M5301x) || \
defined(CONFIG_M5445X)
#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
#else
#define OPT_FRAME_SIZE 0
#endif
/*
* Some hardware gets it MAC address out of local flash memory.
* if this is non-zero then assume it is the address to get MAC from.
*/
#if defined(CONFIG_NETtel)
#define FEC_FLASHMAC 0xf0006006
#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
#define FEC_FLASHMAC 0xf0006000
#elif defined(CONFIG_CANCam)
#define FEC_FLASHMAC 0xf0020000
#elif defined(CONFIG_M5272C3)
#define FEC_FLASHMAC (0xffe04000 + 4)
#elif defined(CONFIG_MOD5272)
#define FEC_FLASHMAC 0xffc0406b
#else
#define FEC_FLASHMAC 0
#endif
#ifdef CONFIG_FEC_DMA_USE_SRAM
#define TX_RING_SIZE 8 /* Must be power of two */
#define TX_RING_MOD_MASK 7 /* for this to work */
#else
#define TX_RING_SIZE 16 /* Must be power of two */
#define TX_RING_MOD_MASK 15 /* for this to work */
#endif
typedef struct fec {
unsigned long fec_reserved0;
unsigned long fec_ievent; /* Interrupt event reg */
unsigned long fec_imask; /* Interrupt mask reg */
unsigned long fec_reserved1;
unsigned long fec_r_des_active; /* Receive descriptor reg */
unsigned long fec_x_des_active; /* Transmit descriptor reg */
unsigned long fec_reserved2[3];
unsigned long fec_ecntrl; /* Ethernet control reg */
unsigned long fec_reserved3[6];
unsigned long fec_mii_data; /* MII manage frame reg */
unsigned long fec_mii_speed; /* MII speed control reg */
unsigned long fec_reserved4[7];
unsigned long fec_mib_ctrlstat; /* MIB control/status reg */
unsigned long fec_reserved5[7];
unsigned long fec_r_cntrl; /* Receive control reg */
unsigned long fec_reserved6[15];
unsigned long fec_x_cntrl; /* Transmit Control reg */
unsigned long fec_reserved7[7];
unsigned long fec_addr_low; /* Low 32bits MAC address */
unsigned long fec_addr_high; /* High 16bits MAC address */
unsigned long fec_opd; /* Opcode + Pause duration */
unsigned long fec_reserved8[10];
unsigned long fec_hash_table_high; /* High 32bits hash table */
unsigned long fec_hash_table_low; /* Low 32bits hash table */
unsigned long fec_grp_hash_table_high;/* High 32bits hash table */
unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */
unsigned long fec_reserved9[7];
unsigned long fec_x_wmrk; /* FIFO transmit water mark */
unsigned long fec_reserved10;
unsigned long fec_r_bound; /* FIFO receive bound reg */
unsigned long fec_r_fstart; /* FIFO receive start reg */
unsigned long fec_reserved11[11];
unsigned long fec_r_des_start; /* Receive descriptor ring */
unsigned long fec_x_des_start; /* Transmit descriptor ring */
unsigned long fec_r_buff_size; /* Maximum receive buff size */
} fec_t;
/*
* Define the buffer descriptor structure.
*/
typedef struct bufdesc {
unsigned short cbd_sc; /* Control and status info */
unsigned short cbd_datlen; /* Data length */
unsigned long cbd_bufaddr; /* Buffer address */
} cbd_t;
/* Forward declarations of some structures to support different PHYs
*/
typedef struct {
uint mii_data;
void (*funct)(uint mii_reg, struct net_device *dev);
} phy_cmd_t;
typedef struct {
uint id;
char *name;
const phy_cmd_t *config;
const phy_cmd_t *startup;
const phy_cmd_t *ack_int;
const phy_cmd_t *shutdown;
} phy_info_t;
/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
* tx_bd_base always point to the base of the buffer descriptors. The
* cur_rx and cur_tx point to the currently available buffer.
* The dirty_tx tracks the current buffer that is being sent by the
* controller. The cur_tx and dirty_tx are equal under both completely
* empty and completely full conditions. The empty/ready indicator in
* the buffer descriptor determines the actual condition.
*/
struct fec_enet_private {
/* Hardware registers of the FEC device */
volatile fec_t *hwp;
struct net_device *netdev;
struct platform_device *pdev;
/* The saved address of a sent-in-place packet/buffer, for skfree(). */
unsigned char *tx_bounce[TX_RING_SIZE];
struct sk_buff *tx_skbuff[TX_RING_SIZE];
ushort skb_cur;
ushort skb_dirty;
/* CPM dual port RAM relative addresses.
*/
cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
cbd_t *tx_bd_base;
cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
cbd_t *dirty_tx; /* The ring entries to be free()ed. */
uint tx_full;
/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
spinlock_t hw_lock;
/* hold while accessing the mii_list_t() elements */
spinlock_t mii_lock;
struct mii_bus *mdio_bus;
struct phy_device *phydev;
uint phy_id;
uint phy_id_done;
uint phy_status;
uint phy_speed;
phy_info_t const *phy;
struct work_struct phy_task;
volatile fec_t *phy_hwp;
uint sequence_done;
uint mii_phy_task_queued;
uint phy_addr;
int index;
int opened;
int link;
int old_link;
int full_duplex;
int duplex;
int speed;
int msg_enable;
};
struct fec_platform_private {
struct platform_device *pdev;
unsigned long quirks;
int num_slots; /* Slots on controller */
struct fec_enet_private *fep_host[0]; /* Pointers to hosts */
};
#endif

136
target/linux/coldfire/files-2.6.31/arch/m68k/kernel/vmlinux-cf.lds
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/* ld script to make m68k Coldfire Linux kernel
*
* Derived from arch/m68k/kernel/vmlinux-std.lds
*
* Updated 11/26/2007 for new CodeSourcery toolset
* by Kurt Mahan <kmahan@freescale.com>
*
* Copyright Freescale Semiconductor, Inc. 2008-2009
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*/
#define LOAD_OFFSET 0x00000000
#include <asm-generic/vmlinux.lds.h>
#include <asm/page_offset.h>
#define START_OFFSET 0x00020000
#define IMAGE_START PAGE_OFFSET_RAW + START_OFFSET
OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", "elf32-m68k")
OUTPUT_ARCH(m68k)
ENTRY(_stext)
jiffies = jiffies_64 + 4;
SECTIONS
{
. = IMAGE_START;
.text.head : AT(ADDR(.text.head) - LOAD_OFFSET) {
_text = .; /* Text and read-only data */
HEAD_TEXT
} :text = 0x4e75
.text : AT(ADDR(.text) - LOAD_OFFSET) {
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT
*(.fixup)
*(.gnu.warning)
} :text = 0x4e75
_etext = .; /* End of text section */
. = ALIGN(16);
__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
__start___ex_table = .;
*(__ex_table)
__stop___ex_table = .;
}
RODATA
. = ALIGN(8192);
.data : AT(ADDR(.data) - LOAD_OFFSET) { /* Data */
DATA_DATA
CONSTRUCTORS
} :data
. = ALIGN(16);
.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET ) {
*(.data.cacheline_aligned)
} :data
_edata = .; /* End of data section */
. = ALIGN(8192); /* Initrd */
.init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
__init_begin = .;
_sinittext = .;
INIT_TEXT
_einittext = .;
}
.init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
INIT_DATA
}
. = ALIGN(16);
.init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
__setup_start = .;
*(.init.setup)
__setup_end = .;
}
.initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
__initcall_start = .;
INITCALLS
__initcall_end = .;
}
.con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
__con_initcall_start = .;
*(.con_initcall.init)
__con_initcall_end = .;
}
SECURITY_INIT
#ifdef CONFIG_BLK_DEV_INITRD
. = ALIGN(8192);
.init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
__initramfs_start = .;
*(.init.ramfs)
__initramfs_end = .;
}
#endif
NOTES
. = ALIGN(8192);
__init_end = .;
.data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) {
*(.data.init_task) /* The initial task and kernel stack */
}
_sbss = .;
.bss : AT(ADDR(.bss) - LOAD_OFFSET) { /* BSS */
*(.bss)
}
_ebss = .;
_end = . ;
/DISCARD/ : {
EXIT_TEXT
EXIT_DATA
*(.exitcall.exit)
*(.discard)
}
STABS_DEBUG
.comment 0 : { *(.comment) }
/* Sections to be discarded */
/*DISCARDS*/
}

317
target/linux/coldfire/files-2.6.31/arch/m68k/mm/cf-mmu.c
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/*
* linux/arch/m68k/mm/cf-mmu.c
*
* Based upon linux/arch/m68k/mm/sun3mmu.c
* Based upon linux/arch/ppc/mm/mmu_context.c
*
* Implementations of mm routines specific to the Coldfire MMU.
*
* Copyright (c) 2008 Freescale Semiconductor, Inc.
* Copyright Freescale Semiconductor, Inc. 2008-2009
* Jason Jin Jason.Jin@freescale.com
* Shrek Wu B16972@freescale.com
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/init.h>
#ifdef CONFIG_BLK_DEV_RAM
#include <linux/blkdev.h>
#endif
#include <linux/bootmem.h>
#include <asm/setup.h>
#include <asm/uaccess.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
#include <asm/cf_pgalloc.h>
#include <asm/coldfire.h>
#include <asm/tlbflush.h>
#define KMAPAREA(x) ((x >= VMALLOC_START) && (x < KMAP_END))
#undef DEBUG
#ifdef CONFIG_VDSO
unsigned long next_mmu_context;
#else
mm_context_t next_mmu_context;
#endif
unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
atomic_t nr_free_contexts;
struct mm_struct *context_mm[LAST_CONTEXT+1];
void steal_context(void);
#ifdef CONFIG_M5445X
void m68k_setup_node(int);
#endif
const char bad_pmd_string[] = "Bad pmd in pte_alloc: %08lx\n";
extern unsigned long empty_bad_page_table;
extern unsigned long empty_bad_page;
extern unsigned long num_pages;
#ifdef CONFIG_M5445X
extern unsigned long availmem;
#endif
extern char __init_begin, __init_end;
/*
* Free memory used for system initialization.
*/
void free_initmem(void)
{
#if 0
unsigned long addr;
unsigned long start = (unsigned long)&__init_begin;
unsigned long end = (unsigned long)&__init_end;
printk(KERN_INFO "free_initmem: __init_begin = 0x%lx __init_end = 0x%lx\n", start, end);
addr = (unsigned long)&__init_begin;
for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) {
/* not currently used */
virt_to_page(addr)->flags &= ~(1 << PG_reserved);
init_page_count(virt_to_page(addr));
free_page(addr);
totalram_pages++;
}
#endif
}
/*
* Initialize the paging system.
*/
void __init paging_init(void)
{
pgd_t * pg_dir;
pte_t * pg_table;
int i;
unsigned long address;
unsigned long next_pgtable;
unsigned long zones_size[MAX_NR_ZONES];
unsigned long size;
enum zone_type zone;
/* allocate zero page */
empty_zero_page = (void *)alloc_bootmem_pages(PAGE_SIZE);
memset((void *)empty_zero_page, 0, PAGE_SIZE);
/* zero kernel page directory */
pg_dir = swapper_pg_dir;
memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
/*
* setup page tables for PHYSRAM
*/
/* starting loc in page directory */
pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
/* allocate page tables */
size = num_pages * sizeof(pte_t);
size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
next_pgtable = (unsigned long)alloc_bootmem_pages(size);
address = PAGE_OFFSET;
while (address < (unsigned long)high_memory) {
/* setup page table in page directory */
pg_table = (pte_t *)next_pgtable;
next_pgtable += PTRS_PER_PTE * sizeof(pte_t);
pgd_val(*pg_dir) = (unsigned long)pg_table;
pg_dir++;
/* create PTEs in page table */
for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table) {
pte_t pte = pfn_pte(virt_to_pfn(address), PAGE_INIT);
if (address >= (unsigned long)high_memory)
pte_val (pte) = 0;
set_pte(pg_table, pte);
address += PAGE_SIZE;
}
}
/*
* setup page tables for DMA area
*/
/* starting loc in page directory */
pg_dir = swapper_pg_dir;
pg_dir += CONFIG_DMA_BASE >> PGDIR_SHIFT;
/* allocate page tables */
size = (CONFIG_DMA_SIZE >> PAGE_SHIFT) * sizeof(pte_t);
size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
next_pgtable = (unsigned long)alloc_bootmem_pages(size);
address = CONFIG_DMA_BASE;
while (address < (CONFIG_DMA_BASE + CONFIG_DMA_SIZE)) {
/* setup page table in page directory */
pg_table = (pte_t *)next_pgtable;
next_pgtable += PTRS_PER_PTE * sizeof(pte_t);
pgd_val(*pg_dir) = (unsigned long)pg_table;
pg_dir++;
/* create PTEs in page table */
for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table) {
pte_t pte = pfn_pte(virt_to_pfn(address), PAGE_INIT);
if (address >= (CONFIG_DMA_BASE + CONFIG_DMA_SIZE))
pte_val (pte) = 0;
set_pte(pg_table, pte);
address += PAGE_SIZE;
}
}
/*
* setup zones
*/
current->mm = NULL;
/* clear zones */
for (zone = 0; zone < MAX_NR_ZONES; zone++)
zones_size[zone] = 0x0;
zones_size[ZONE_DMA] = CONFIG_DMA_SIZE >> PAGE_SHIFT;
zones_size[ZONE_NORMAL] = (((unsigned long)high_memory -
PAGE_OFFSET) >> PAGE_SHIFT) -
zones_size[ZONE_DMA];
free_area_init(zones_size);
}
/*
* Handle a missed TLB
*/
int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word)
{
struct mm_struct *mm;
pgd_t *pgd;
pmd_t *pmd;
pte_t *pte;
unsigned long mmuar;
int asid;
int flags;
local_save_flags(flags);
local_irq_disable();
mmuar = ( dtlb ) ? regs->mmuar
: regs->pc + (extension_word * sizeof(long));
mm = (!user_mode(regs) && KMAPAREA(mmuar)) ? &init_mm : current->mm;
if (!mm) {
local_irq_restore(flags);
return (-1);
}
pgd = pgd_offset(mm, mmuar);
if (pgd_none(*pgd)) {
local_irq_restore(flags);
return (-1);
}
pmd = pmd_offset(pgd, mmuar);
if (pmd_none(*pmd)) {
local_irq_restore(flags);
return (-1);
}
pte = (KMAPAREA(mmuar)) ? pte_offset_kernel(pmd, mmuar)
: pte_offset_map(pmd, mmuar);
if (pte_none(*pte) || !pte_present(*pte)) {
local_irq_restore(flags);
return (-1);
}
if (write) {
if (!pte_write(*pte)) {
local_irq_restore(flags);
return (-1);
}
set_pte(pte, pte_mkdirty(*pte));
}
set_pte(pte, pte_mkyoung(*pte));
asid = cpu_context(mm) & 0xff;
if (!pte_dirty(*pte) && !KMAPAREA(mmuar))
set_pte(pte, pte_wrprotect(*pte));
*MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT)
| (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT)
| MMUTR_V;
*MMUDR = (pte_val(*pte) & PAGE_MASK)
| ((pte->pte) & CF_PAGE_MMUDR_MASK)
| MMUDR_SZ8K | MMUDR_X;
if ( dtlb )
*MMUOR = MMUOR_ACC | MMUOR_UAA;
else
*MMUOR = MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA;
asm("nop");
#ifdef DEBUG
printk("cf_tlb_miss: va=%lx, pa=%lx\n", (mmuar & PAGE_MASK),
(pte_val(*pte) & PAGE_MASK));
#endif
local_irq_restore(flags);
return (0);
}
/*
* Context Management
*
* Based on arch/ppc/mmu_context.c
*/
/*
* Initialize the context management system.
*/
void __init mmu_context_init(void)
{
/*
* Some processors have too few contexts to reserve one for
* init_mm, and require using context 0 for a normal task.
* Other processors reserve the use of context zero for the kernel.
* This code assumes FIRST_CONTEXT < 32.
*/
context_map[0] = (1 << FIRST_CONTEXT) - 1;
next_mmu_context = FIRST_CONTEXT;
atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
}
/*
* Steal a context from a task that has one at the moment.
* This is only used on 8xx and 4xx and we presently assume that
* they don't do SMP. If they do then thicfpgalloc.hs will have to check
* whether the MM we steal is in use.
* We also assume that this is only used on systems that don't
* use an MMU hash table - this is true for 8xx and 4xx.
* This isn't an LRU system, it just frees up each context in
* turn (sort-of pseudo-random replacement :). This would be the
* place to implement an LRU scheme if anyone was motivated to do it.
* -- paulus
*/
void steal_context(void)
{
struct mm_struct *mm;
/* free up context `next_mmu_context' */
/* if we shouldn't free context 0, don't... */
if (next_mmu_context < FIRST_CONTEXT)
next_mmu_context = FIRST_CONTEXT;
mm = context_mm[next_mmu_context];
flush_tlb_mm(mm);
destroy_context(mm);
}

1561
target/linux/coldfire/files-2.6.31/drivers/net/fec_m547x.c
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242
target/linux/coldfire/files-2.6.31/drivers/net/fec_m547x.h
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@ -1,242 +0,0 @@
#define FEC_BASE_ADDR_FEC0 ((unsigned int)MCF_MBAR + 0x9000)
#define FEC_BASE_ADDR_FEC1 ((unsigned int)MCF_MBAR + 0x9800)
/*
#define FEC_INTC_IMRH_INT_MASK38 (0x00000040)
#define FEC_INTC_IMRH_INT_MASK39 (0x00000080)
#define FEC_INTC_ICR_FEC0 (0x30)
#define FEC_INTC_ICR_FEC1 (0x31)
*/
#define FEC_FECI2CIRQ (0xFFC0)
#define FEC_GPIO_PAR_FECI2CIRQ \
(*(volatile unsigned short *)((unsigned int)MCF_MBAR + 0xA44))
/*
#define FEC_INTC_ICRn(x) \
(*(volatile unsigned char *)(void*)
((unsigned int) MCF_MBAR + 0x000740+((x)*0x001)))
#define FEC_INTC_IMRH \
*(volatile unsigned int*)((unsigned int)MCF_MBAR + 0x000708)
*/
#define FEC_ECR_DISABLE (0x00000000)
#define FEC_ECR(x) \
(*(volatile unsigned int *)(x + 0x024))
#define FEC_EIR(x) \
(*(volatile unsigned int *)(x + 0x004))
#define FEC_PALR(x) \
(*(volatile unsigned int *)(x + 0x0E4))
#define FEC_PAUR(x) \
(*(volatile unsigned int *)(x + 0x0E8))
#define FEC_IALR(x) \
(*(volatile unsigned int *)(x + 0x11C))
#define FEC_IAUR(x) \
(*(volatile unsigned int *)(x + 0x118))
#define FEC_GALR(x) \
(*(volatile unsigned int *)(x + 0x124))
#define FEC_GAUR(x) \
(*(volatile unsigned int *)(x + 0x120))
#define FEC_RCR(x) \
(*(volatile unsigned int *)(x + 0x084))
#define FEC_FECRFCR(x) \
(*(volatile unsigned int *)(x + 0x18C))
#define FEC_FECRFAR(x) \
(*(volatile unsigned int *)(x + 0x198))
#define FEC_FECTFCR(x) \
(*(volatile unsigned int *)(x + 0x1AC))
#define FEC_FECTFAR(x) \
(*(volatile unsigned int *)(x + 0x1B8))
#define FEC_FECTFWR(x) \
(*(volatile unsigned int *)(x + 0x144))
#define FEC_CTCWR(x) \
(*(volatile unsigned int *)(x + 0x1C8))
#define FEC_EIMR(x) \
(*(volatile unsigned int *)(x + 0x008))
#define FEC_TCR(x) \
(*(volatile unsigned int *)(x + 0x0C4))
#define FEC_MIBC(x) \
(*(volatile unsigned int *)(x + 0x064))
#define FEC_MSCR(x) \
(*(volatile unsigned int *)(x + 0x044))
#define FEC_FECTFDR(x) \
(*(volatile unsigned int *)(x + 0x1A4))
#define FEC_FECRFDR(x) \
(*(volatile unsigned int *)(x + 0x184))
#define FEC_FECTFSR(x) \
(*(volatile unsigned int *)(x + 0x1A8))
#define FEC_FECRFSR(x) \
(*(volatile unsigned int *)(x + 0x188))
#define FECSTAT_RMON_R_PACKETS(x) \
(*(volatile unsigned int *)(x + 0x284))
#define FECSTAT_RMON_T_PACKETS(x) \
(*(volatile unsigned int *)(x + 0x204))
#define FECSTAT_RMON_R_OCTETS(x) \
(*(volatile unsigned int *)(x + 0x2C4))
#define FECSTAT_RMON_T_OCTETS(x) \
(*(volatile unsigned int *)(x + 0x244))
#define FECSTAT_RMON_R_UNDERSIZE(x) \
(*(volatile unsigned int *)(x + 0x294))
#define FECSTAT_RMON_R_OVERSIZE(x) \
(*(volatile unsigned int *)(x + 0x298))
#define FECSTAT_RMON_R_FRAG(x) \
(*(volatile unsigned int *)(x + 0x29C))
#define FECSTAT_RMON_R_JAB(x) \
(*(volatile unsigned int *)(x + 0x2A0))
#define FECSTAT_RMON_R_MC_PKT(x) \
(*(volatile unsigned int *)(x + 0x28C))
#define FECSTAT_RMON_T_COL(x) \
(*(volatile unsigned int *)(x + 0x224))
#define FECSTAT_IEEE_R_ALIGN(x) \
(*(volatile unsigned int *)(x + 0x2D4))
#define FECSTAT_IEEE_R_CRC(x) \
(*(volatile unsigned int *)(x + 0x2D0))
#define FECSTAT_IEEE_R_MACERR(x) \
(*(volatile unsigned int *)(x + 0x2D8))
#define FECSTAT_IEEE_T_CSERR(x) \
(*(volatile unsigned int *)(x + 0x268))
#define FECSTAT_IEEE_T_MACERR(x) \
(*(volatile unsigned int *)(x + 0x264))
#define FECSTAT_IEEE_T_LCOL(x) \
(*(volatile unsigned int *)(x + 0x25C))
#define FECSTAT_IEEE_R_OCTETS_OK(x) \
(*(volatile unsigned int *)(x + 0x2E0))
#define FECSTAT_IEEE_T_OCTETS_OK(x) \
(*(volatile unsigned int *)(x + 0x274))
#define FECSTAT_IEEE_R_DROP(x) \
(*(volatile unsigned int *)(x + 0x2C8))
#define FECSTAT_IEEE_T_DROP(x) \
(*(volatile unsigned int *)(x + 0x248))
#define FECSTAT_IEEE_R_FRAME_OK(x) \
(*(volatile unsigned int *)(x + 0x2CC))
#define FECSTAT_IEEE_T_FRAME_OK(x) \
(*(volatile unsigned int *)(x + 0x24C))
#define FEC_MMFR(x) \
(*(volatile unsigned int *)(x + 0x040))
#define FEC_FECFRST(x) \
(*(volatile unsigned int *)(x + 0x1C4))
#define FEC_MAX_FRM_SIZE (1518)
#define FEC_MAXBUF_SIZE (1520)
/* Register values */
#define FEC_ECR_RESET (0x00000001)
#define FEC_EIR_CLEAR (0xFFFFFFFF)
#define FEC_EIR_RL (0x00100000)
#define FEC_EIR_HBERR (0x80000000)
#define FEC_EIR_BABR (0x40000000)
/* babbling receive error */
#define FEC_EIR_BABT (0x20000000)
/* babbling transmit error */
#define FEC_EIR_TXF (0x08000000)
/* transmit frame interrupt */
#define FEC_EIR_MII (0x00800000)
/* MII interrupt */
#define FEC_EIR_LC (0x00200000)
/* late collision */
#define FEC_EIR_XFUN (0x00080000)
/* transmit FIFO underrun */
#define FEC_EIR_XFERR (0x00040000)
/* transmit FIFO error */
#define FEC_EIR_RFERR (0x00020000)
/* receive FIFO error */
#define FEC_RCR_MAX_FRM_SIZE (FEC_MAX_FRM_SIZE << 16)
#define FEC_RCR_MII (0x00000004)
#define FEC_FECRFCR_FAE (0x00400000)
/* frame accept error */
#define FEC_FECRFCR_RXW (0x00200000)
/* receive wait condition */
#define FEC_FECRFCR_UF (0x00100000)
/* receive FIFO underflow */
#define FEC_FECRFCR_FRM (0x08000000)
#define FEC_FECRFCR_GR (0x7 << 24)
#define FEC_EIMR_DISABLE (0x00000000)
#define FEC_FECRFAR_ALARM (0x300)
#define FEC_FECTFCR_FRM (0x08000000)
#define FEC_FECTFCR_GR (0x7 << 24)
#define FEC_FECTFCR_FAE (0x00400000)
/* frame accept error */
#define FEC_FECTFCR_TXW (0x00040000)
/* transmit wait condition */
#define FEC_FECTFCR_UF (0x00100000)
/* transmit FIFO underflow */
#define FEC_FECTFCR_OF (0x00080000)
/* transmit FIFO overflow */
#define FEC_FECTFAR_ALARM (0x100)
#define FEC_FECTFWR_XWMRK (0x00000000)
#define FEC_FECTFSR_MSK (0xC0B00000)
#define FEC_FECTFSR_TXW (0x40000000)
/* transmit wait condition */
#define FEC_FECTFSR_FAE (0x00800000)
/* frame accept error */
#define FEC_FECTFSR_UF (0x00200000)
/* transmit FIFO underflow */
#define FEC_FECTFSR_OF (0x00100000)
/* transmit FIFO overflow */
#define FEC_FECRFSR_MSK (0x80F00000)
#define FEC_FECRFSR_FAE (0x00800000)
/* frame accept error */
#define FEC_FECRFSR_RXW (0x00400000)
/* receive wait condition */
#define FEC_FECRFSR_UF (0x00200000)
/* receive FIFO underflow */
#define FEC_CTCWR_TFCW_CRC (0x03000000)
#define FEC_TCR_FDEN (0x00000004)
#define FEC_TCR_HBC (0x00000002)
#define FEC_RCR_DRT (0x00000002)
#define FEC_EIMR_MASK (FEC_EIR_RL | FEC_EIR_HBERR)
#define FEC_ECR_ETHEREN (0x00000002)
#define FEC_FECTFCR_MSK (0x00FC0000)
#define FEC_FECRFCR_MSK (0x00F80000)
#define FEC_EIR_GRA (0x10000000)
#define FEC_TCR_GTS (0x00000001)
#define FEC_MIBC_ENABLE (0x00000000)
#define FEC_MIB_LEN (228)
#define FEC_PHY_ADDR (0x01)
#define FEC_RX_DMA_PRI (6)
#define FEC_TX_DMA_PRI (6)
#define FEC_TX_BUF_NUMBER (8)
#define FEC_RX_BUF_NUMBER (64)
#define FEC_TX_INDEX_MASK (0x7)
#define FEC_RX_INDEX_MASK (0x3f)
#define FEC_RX_DESC_FEC0 SYS_SRAM_FEC_START
#define FEC_TX_DESC_FEC0 \
(FEC_RX_DESC_FEC0 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec))
#define FEC_RX_DESC_FEC1 \
(SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE/2)
#define FEC_TX_DESC_FEC1 \
(FEC_RX_DESC_FEC1 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec))
#define FEC_EIR_MII (0x00800000)
#define FEC_MMFR_READ (0x60020000)
#define FEC_MMFR_WRITE (0x50020000)
#define FEC_FLAGS_RX (0x00000001)
#define FEC_CRCPOL (0xEDB88320)
#define FEC_MII_TIMEOUT (2)
#define FEC_GR_TIMEOUT (1)
#define FEC_TX_TIMEOUT (1)
#define FEC_RX_TIMEOUT (1)
#define FEC_SW_RST 0x2000000
#define FEC_RST_CTL 0x1000000
int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
unsigned int *data);
int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
unsigned int data);
#define FEC_MII_SPEED \
((MCF_CLK / 2) / ((2500000 / 2) * 2))

269
target/linux/coldfire/files-2.6.31/drivers/net/phy/broadcom522x.c
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/*
*Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
* Chenghu Wu <b16972@freescale.com>
*
* Driver for broadcom PHYs 522x
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
/* DP83865 phy identifier values */
#define BCM5222_PHY_ID 0x00406320
/* PHY Register */
#define BCM5222_TIMEOUT 0x100
/* MII Registers */
#define BCM5222_CTRL 0x00
#define BCM5222_STATUS 0x01
#define BCM5222_ID_HIGH 0x02
#define BCM5222_ID_LOW 0x03
#define BCM5222_AN_ADV 0x04
#define BCM5222_AN_LP 0x05
#define BCM5222_AN_EXP 0x06
#define BCM5222_AN_NEXTPG 0x07
#define BCM5222_AN_LP_NPTX 0x08
#define BCM5222_AUX_CS 0x18
#define BCM5222_AUX_STATUS 0x19
/* CONTROL Bits */
#define BCM5222_CTRL_RESET 0x8000
#define BCM5222_CTRL_LOOPBACK 0x4000
#define BCM5222_CTRL_FORCE 0x2000
#define BCM5222_CTRL_AUTOEN 0x1000
#define BCM5222_CTRL_PWRDN 0x0800
#define BCM5222_CTRL_ISOLATE 0x0400
#define BCM5222_CTRL_RESTART 0x0200
#define BCM5222_CTRL_DUPLEX 0x0100
#define BCM5222_CTRL_COLLEN 0x0080
/* STATUS Bits */
#define BCM5222_STATUS_100T4 0x8000
#define BCM5222_STATUS_100TXFDX 0x4000
#define BCM5222_STATUS_100TX 0x2000
#define BCM5222_STATUS_10FDX 0x1000
#define BCM5222_STATUS_10 0x0800
#define BCM5222_STATUS_MF_PREAMBLE 0x0040
#define BCM5222_STATUS_AN_COMPLETE 0x0020
#define BCM5222_STATUS_REMOTE_FAULT 0x0010
#define BCM5222_STATUS_AN_CAPABLE 0x0008
#define BCM5222_STATUS_LINK 0x0004
#define BCM5222_STATUS_JABBER 0x0002
#define BCM5222_STATUS_EXT_CAP 0x0001
/* ID Values */
#define BCM5222_ID_HIGH_VAL 0x0040
#define BCM5222_ID_LOW_VAL 0x6320
/* Advertise Bits */
#define BCM5222_AN_ADV_NEXTPG 0x8000
#define BCM5222_AN_ADV_REMOTE_FAULT 0x2000
#define BCM5222_AN_ADV_PAUSE 0x0400
#define BCM5222_AN_ADV_100T4 0x0200
#define BCM5222_AN_ADV_100TXFDX 0x0100
#define BCM5222_AN_ADV_100TX 0x0080
#define BCM5222_AN_ADV_10FDX 0x0040
#define BCM5222_AN_ADV_10 0x0020
#define BCM5222_AN_ADV_8023 0x0001
#define BCM5222_AN_ADV_ALL \
(BCM5222_AN_ADV_100TXFDX | \
BCM5222_AN_ADV_100TXFDX | \
BCM5222_AN_ADV_100TX | \
BCM5222_AN_ADV_10FDX | \
BCM5222_AN_ADV_10 | \
BCM5222_AN_ADV_8023)
/* AUX CTRL/STATUS Bits */
#define BCM5222_AUX_CS_JABBER_DIS 0x8000
#define BCM5222_AUX_CS_FORCE_LINK 0x4000
#define BCM5222_AUX_CS_10M_TX_PWR 0x0100
#define BCM5222_AUX_CS_HSQ_LSQ_MASK 0x00c0
#define BCM5222_AUX_CS_EDGE_RATE_MASK 0x0030
#define BCM5222_AUX_CS_AN_IND 0x0008
#define BCM5222_AUX_CS_SPEED_FORCE 0x0004
#define BCM5222_AUX_CS_SPEED 0x0002
#define BCM5222_AUX_CS_DUPLEX 0x0001
/* AUX STATUS Bits */
#define BCM5222_AUX_STATUS_AN_COMP 0x8000
#define BCM5222_AUX_STATUS_AN_COMPACK 0x4000
#define BCM5222_AUX_STATUS_AN_ACKDET 0x2000
#define BCM5222_AUX_STATUS_AN_ABDET 0x1000
#define BCM5222_AUX_STATUS_AN_PAUSE 0x0800
#define BCM5222_AUX_STATUS_AN_HCDMASK 0x0700
#define BCM5222_AUX_STATUS_AN_PDFAULT 0x0080
#define BCM5222_AUX_STATUS_LP_RMTFAULT 0x0040
#define BCM5222_AUX_STATUS_LP_PGRX 0x0020
#define BCM5222_AUX_STATUS_LP_NEGABLE 0x0010
#define BCM5222_AUX_STATUS_SPEED 0x0008
#define BCM5222_AUX_STATUS_LINK 0x0004
#define BCM5222_AUX_STATUS_AN_EN 0x0002
#define BCM5222_AUX_STATUS_JABBER 0x0001
static int bcm5222_config_intr(struct phy_device *phydev)
{
int err = 0;
printk(KERN_INFO "%s PHY_INTERRUPT %x\n",
__func__, phydev->interrupts);
return err;
}
static int bcm5222_ack_interrupt(struct phy_device *phydev)
{
return 0;
}
static int bcm5222_config_init(struct phy_device *phydev)
{
return bcm5222_ack_interrupt(phydev);
}
static int bcm5222_config_init_old(struct phy_device *phydev)
{
int timeout;
int flag = 1;
int ret = phy_read(phydev, BCM5222_AUX_STATUS);
if (ret < 0) {
printk(KERN_INFO "%s MII_BCM5222_ISR %x\n",
__func__, ret);
}
/*
* reset
*/
phy_write(phydev, BCM5222_CTRL, BCM5222_CTRL_RESET);
/* check that it cleared */
ret = phy_read(phydev, BCM5222_CTRL);
printk(KERN_INFO "%s BCM5222_CTRL %x\n",
__func__, ret);
/*if reset bit is set, return */
if (ret & BCM5222_CTRL_RESET) {
printk(KERN_ERR "%s %x = BCM5222_CTRL_RESET(%x)\n",
__func__, ret, BCM5222_CTRL_RESET);
return -ETIME;
}
/*
* setup auto-negotiation
*/
/* disable */
phy_write(phydev, BCM5222_CTRL, 0);
ret = phy_read(phydev, BCM5222_CTRL);
printk(KERN_INFO "%s BCM5222_CTRL %x\n",
__func__, ret);
/* set the auto-negotiation advertisement register */
phy_write(phydev, BCM5222_AN_ADV, BCM5222_AN_ADV_ALL);
ret = phy_read(phydev, BCM5222_AN_ADV);
printk(KERN_INFO "%s BCM5222_AN_ADV %x, BCM5222_AN_ADV_ALL %x\n",
__func__, ret, BCM5222_AN_ADV_ALL);
/* enable */
phy_write(phydev, BCM5222_CTRL, BCM5222_CTRL_AUTOEN);
ret = phy_read(phydev, BCM5222_CTRL);
printk(KERN_INFO "%s BCM5222_CTRL %x\n",
__func__, ret);
printk(KERN_INFO "** wait for complete\n");
/* read aux status reg */
ret = phy_read(phydev, BCM5222_AUX_STATUS);
/* Wait for the auto-negotiation completion */
timeout = BCM5222_TIMEOUT;
while (!(ret & BCM5222_AUX_STATUS_AN_COMP)) {
if (!timeout--) {
flag = 0;
printk(KERN_INFO "BCM5222: TIMEOUT\n");
break;
}
mdelay(10);
/* Read PHY status register */
ret = phy_read(phydev, BCM5222_AUX_STATUS);
}
ret = phy_read(phydev, BCM5222_AUX_STATUS);
ret = phy_read(phydev, BCM5222_AN_ADV);
return 0;
}
static int bcm5222_read_status(struct phy_device *phydev)
{
int ret;
ret = phy_read(phydev, BCM5222_AUX_STATUS);
printk(KERN_INFO "%s ret %x\n", __func__, ret);
if (ret & BCM5222_AUX_STATUS_LINK)
phydev->link = 1;
else
phydev->link = 0;
if (ret & BCM5222_AUX_STATUS_SPEED)
phydev->speed = SPEED_100;
else
phydev->speed = SPEED_10;
ret = phy_read(phydev, BCM5222_AUX_CS);
printk(KERN_INFO "%s ret %x\n", __func__, ret);
if (ret & BCM5222_AUX_CS_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
return 0;
}
static int bcm5222_config_aneg(struct phy_device *phydev)
{
phy_read(phydev, BCM5222_AUX_STATUS);
phy_read(phydev, BCM5222_AN_ADV);
return 0;
}
static struct phy_driver bcm5222_driver = {
.phy_id = BCM5222_PHY_ID,
.phy_id_mask = 0xfffffff0,
.name = "Broadcom BCM5222",
.features = PHY_BASIC_FEATURES,
.flags = PHY_HAS_INTERRUPT,
.config_init = bcm5222_config_init,
.config_aneg = genphy_config_aneg,
.read_status = genphy_read_status,
.ack_interrupt = bcm5222_ack_interrupt,
.config_intr = bcm5222_config_intr,
.driver = {.owner = THIS_MODULE,}
};
static int __init bcm5222_init(void)
{
int ret;
ret = phy_driver_register(&bcm5222_driver);
if (ret)
goto err1;
return 0;
err1:
printk(KERN_INFO "register bcm5222 PHY driver fail\n");
return ret;
}
static void __exit bcm5222_exit(void)
{
phy_driver_unregister(&bcm5222_driver);
}
MODULE_DESCRIPTION("Broadcom PHY driver");
MODULE_LICENSE("GPL v2");
module_init(bcm5222_init);
module_exit(bcm5222_exit);

4000
target/linux/coldfire/patches-2.6.31/001-coldfire_support.patch
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61
target/linux/coldfire/patches-2.6.31/005-Add-common-serial-driver-and-add-IRDA-for-m5.patch
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@ -1,61 +0,0 @@
From 9eaa978feb942497c4542cc82e63d5468dc8f184 Mon Sep 17 00:00:00 2001
From: Wang Huan <wanghuan@zch06.freescale.net>
Date: Thu, 25 Feb 2010 15:27:21 +0800
Subject: [PATCH 05/23] Add common serial driver and add IRDA support for m547x_8x
Add common serial driver for mcf5445x board and mcf547x, mcf548x boards.
Also add IRDA support for mcf547x, mcf548x boards.
Signed-off-by: Shrek Wu <b16972@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Chengju-Cai <b22600@freescale.com>
---
arch/m68k/include/asm/mcfuart.h | 35 +++++++++++++---
drivers/serial/Kconfig | 13 ++++++
drivers/serial/mcf.c | 88 +++++++++++++++++++++++++++++++++++++++
3 files changed, 130 insertions(+), 6 deletions(-)
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -47,18 +48,35 @@
#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
+#elif defined(CONFIG_M5445X)
+#include <asm/mcf5445x_intc.h>
+#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
+#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
+#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
+#define MCFINT_VECBASE 64
+#define MCFINT_UART0 26
+#elif defined(CONFIG_M547X_8X)
+#define MCFUART_BASE1 0x8600 /* Base address of UART1 */
+#define MCFUART_BASE2 0x8700 /* Base address of UART2 */
+#define MCFUART_BASE3 0x8800 /* Base address of UART3 */
+#define MCFUART_BASE4 0x8900 /* Base address of UART4 */
+#define MCFINT_VECBASE 64
+#define MCFINT_UART0 35
+#define MCFINT_UART1 34
+#define MCFINT_UART2 33
+#define MCFINT_UART3 32
#endif
-
+#ifndef __ASSEMBLY__
#include <linux/serial_core.h>
#include <linux/platform_device.h>
-
struct mcf_platform_uart {
- unsigned long mapbase; /* Physical address base */
- void __iomem *membase; /* Virtual address if mapped */
- unsigned int irq; /* Interrupt vector */
- unsigned int uartclk; /* UART clock rate */
+ unsigned long mapbase; /* Physical address base */
+ void __iomem *membase; /* Virtual address if mapped */
+ unsigned int irq; /* Interrupt vector */
+ unsigned int uartclk; /* UART clock rate */
};
+#endif
/*
* Define the ColdFire UART register set addresses.

42
target/linux/coldfire/patches-2.6.31/006-mcf548x_ethernet.patch
View File

@ -1,42 +0,0 @@
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2010,6 +2010,29 @@ config FEC2
Say Y here if you want to use the second built-in 10/100 Fast
ethernet controller on some Motorola ColdFire processors.
+config FEC_548x
+ tristate "MCF547x/MCF548x Fast Ethernet Controller support"
+ depends on M547X_8X
+ select PHYLIB
+ help
+ The MCF547x and MCF548x have a built-in Fast Ethernet Controller.
+ Saying Y here will include support for this device in the kernel.
+
+ To compile this driver as a module, choose M here: the module
+ will be called fecm.
+
+config FEC_548x_ENABLE_FEC2
+ bool "Enable the second FEC"
+ depends on FEC_548x
+ help
+ This enables the second FEC on the 547x/548x.
+
+config FEC_548x_SHARED_PHY
+ bool "Shared PHY interface(on some ColdFire designs)"
+ depends on FEC_548x_ENABLE_FEC2
+ help
+ Say Y here if both PHYs are controlled via a single channel.+
+
config FEC_MPC52xx
tristate "MPC52xx FEC driver"
depends on PPC_MPC52xx && PPC_BESTCOMM
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -114,6 +114,7 @@ obj-$(CONFIG_PCMCIA_PCNET) += 8390.o
obj-$(CONFIG_HP100) += hp100.o
obj-$(CONFIG_SMC9194) += smc9194.o
obj-$(CONFIG_FEC) += fec.o
+obj-$(CONFIG_FEC_548x) += fec_m547x.o
obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o
ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y)
obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o

24
target/linux/coldfire/patches-2.6.31/007-bcm5222_phy.patch
View File

@ -1,24 +0,0 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -62,6 +62,11 @@ config BROADCOM_PHY
Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481
and BCM5482 PHYs.
+config BROADCOM5222_PHY
+ tristate "Drivers for Broadcom5222 PHY"
+ ---help---
+ Currently supports the BCM5222 PHYs.
+
config ICPLUS_PHY
tristate "Drivers for ICPlus PHYs"
---help---
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_SMSC_PHY) += smsc.o
obj-$(CONFIG_VITESSE_PHY) += vitesse.o
obj-$(CONFIG_BROADCOM_PHY) += broadcom.o
+obj-$(CONFIG_BROADCOM5222_PHY) += broadcom522x.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_ADM6996_PHY) += adm6996.o
obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o

34
target/linux/coldfire/patches-2.6.31/074-Kconfig_lite_boards.patch
View File

@ -1,34 +0,0 @@
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -381,6 +381,9 @@ choice
depends on M547X_8X
default M5485CFE
+config M5474LITE
+ bool "MCF5474LITE"
+ select M547X
config M5475AFE
bool "MCF5475AFE"
select M547X
@@ -399,6 +402,9 @@ config M5475EFE
config M5475FFE
bool "MCF5475FFE"
select M547X
+config M5484LITE
+ bool "MCF5484LITE"
+ select M548X
config M5485AFE
bool "MCF5485AFE"
select M548X
@@ -465,7 +471,10 @@ config NOR_FLASH_BASE
depends on COLDFIRE
default 0x00000000 if M54451EVB
default 0x00000000 if M54455EVB
- default 0xE0000000 if M547X_8X
+ default 0xE0000000 if M5475CFE
+ default 0xE0000000 if M5485CFE
+ default 0xFF800000 if M5484LITE
+ default 0xFF800000 if M5474LITE
config DMA_BASE
hex

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target/linux/coldfire/patches/001-Coldfire-architecture-support-in-Linux-2.6.38.patch Normal file
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target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch Normal file
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7673
target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch Normal file
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6643
target/linux/coldfire/patches/004-MCF54418-support-in-Linux-2.6.38.patch Normal file
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200
target/linux/coldfire/patches/005-Add-serial-driver-and-irda-driver-support-for-MCF544.patch Normal file
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@ -0,0 +1,200 @@
From 5c37079957c5e5555aa8284a879f8cc44fa8eb25 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:39 +0800
Subject: [PATCH 05/52] Add serial driver and irda driver support for MCF5445x and MCF547x/MCF548x
Add common serial driver for MCF5445x and MCF547x/MCF548x.
Also add irda support for MCF547x/MCF548x.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/tty/serial/Kconfig | 20 ++++++++++
drivers/tty/serial/mcf.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 107 insertions(+), 0 deletions(-)
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1027,6 +1027,26 @@ config SERIAL_68328_RTS_CTS
bool "Support RTS/CTS on 68328 serial port"
depends on SERIAL_68328
+config SERIAL_COLDFIRE_IRDA
+ bool "ColdFire IRDA support"
+ depends on SERIAL_MCF
+ help
+ This driver supports IrDA on the ColdFire platform,
+ such as MCF547x and MCF548x.
+
+ Say Y here if you want to use IrDA 1.1 SIR mode.
+
+config SERIAL_COLDFIRE_EDMA
+ bool "ColdFire serial EDMA support"
+ depends on SERIAL_MCF
+ default n
+ help
+ Enables Enhanced Direct Memory Access(eDMA) in the Coldfire
+ serial driver.
+
+ Say Y here if you want to use DMA processing of transmit
+ and receive data for the serial driver.
+
config SERIAL_MCF
bool "Coldfire serial support"
depends on COLDFIRE
--- a/drivers/tty/serial/mcf.c
+++ b/drivers/tty/serial/mcf.c
@@ -4,6 +4,10 @@
* mcf.c -- Freescale ColdFire UART driver
*
* (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Jason Jin Jason.Jin@freescale.com
+ * Shrek Wu B16972@freescale.com
+ * Chengju Cai b22600@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -23,9 +27,11 @@
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/io.h>
+#include <linux/delay.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
+#include <asm/m5485psc.h>
#include <asm/nettel.h>
/****************************************************************************/
@@ -46,6 +52,10 @@
#define mcf_setppdtr(p, v) do { } while (0)
#endif
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+#define SERIAL_IRDA_LINE (2)
+#endif
+
/****************************************************************************/
/*
@@ -101,6 +111,15 @@ static void mcf_start_tx(struct uart_por
{
struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ if (port->line == SERIAL_IRDA_LINE) {
+ /* Disable IRDA receiver*/
+ writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
+ writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
+
+ writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
+ }
+#endif
pp->imr |= MCFUART_UIR_TXREADY;
writeb(pp->imr, port->membase + MCFUART_UIMR);
}
@@ -154,6 +173,30 @@ static int mcf_startup(struct uart_port
spin_lock_irqsave(&port->lock, flags);
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ if (port->line == SERIAL_IRDA_LINE) {
+ /* Put PSC in IrDA mode */
+ MCF_PSC_SICR(port->line) = MCF_PSC_SICR_SIM_SIR;
+
+ /* Set pulse width to 1.6 uS */
+ MCF_PSC_IRSDR(port->line) = (uint8_t)
+ (16 * (CONFIG_MCFCLK / 10000000));
+ MCF_PSC_IRCR1(port->line) = MCF_PSC_IRCR1_SPUL;
+ MCF_PSC_IRCR2(port->line) = 0;
+
+ /* Enable RTS to send */
+ MCF_PSC_OPSET(port->line) = MCF_PSC_OPSET_RTS;
+
+ /* Setup FIFO Alarms */
+ MCF_PSC_RFAR(port->line) = MCF_PSC_RFAR_ALARM(248);
+ MCF_PSC_TFAR(port->line) = MCF_PSC_TFAR_ALARM(248);
+
+ MCF_PSC_RFCR(port->line) = MCF_PSC_RFCR_FRMEN
+ | MCF_PSC_RFCR_GR(4);
+ MCF_PSC_TFCR(port->line) = MCF_PSC_TFCR_FRMEN
+ | MCF_PSC_RFCR_GR(4);
+ }
+#endif
/* Reset UART, get it into known state... */
writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
@@ -177,7 +220,17 @@ static void mcf_shutdown(struct uart_por
{
struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
unsigned long flags;
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ unsigned long delay_counter = 0;
+#endif
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ while (!((readb(port->membase + MCFUART_USR)) & MCFUART_USR_TXEMPTY)) {
+ if (delay_counter++ > 25000)
+ break;
+ udelay(10);
+ }
+#endif
spin_lock_irqsave(&port->lock, flags);
/* Disable all interrupts now */
@@ -202,7 +255,14 @@ static void mcf_set_termios(struct uart_
unsigned int baudfr;
#endif
unsigned char mr1, mr2;
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ int i = 0; /* hush GCC */
+#endif
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ while (i++ < 35000)
+ udelay(1);
+#endif
baud = uart_get_baud_rate(port, termios, old, 0, 230400);
#if defined(CONFIG_M5272)
baudclk = (MCF_BUSCLK / baud) / 32;
@@ -331,6 +391,23 @@ static void mcf_tx_chars(struct mcf_uart
while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
if (xmit->head == xmit->tail)
break;
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ if (port->line == SERIAL_IRDA_LINE) {
+ while (!((readb(port->membase + MCFUART_USR))\
+ & MCFUART_USR_TXEMPTY))
+ ;
+ /* delay for settle */
+#if defined(CONFIG_M548X)
+ udelay(1);
+#elif defined(CONFIG_M547X)
+ udelay(2);
+#else
+ int i = 0;
+ while (i++ < 25000)
+ udelay(1);
+#endif
+ }
+#endif
writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
port->icount.tx++;
@@ -340,6 +417,16 @@ static void mcf_tx_chars(struct mcf_uart
uart_write_wakeup(port);
if (xmit->head == xmit->tail) {
+#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
+ if (port->line == SERIAL_IRDA_LINE) {
+ /* Enable receiver for IRDA */
+ writeb(MCFUART_UCR_CMDRESETRX,\
+ port->membase + MCFUART_UCR);
+ /* reset RX */
+ writeb(MCFUART_UCR_TXENABLE | MCFUART_UCR_RXENABLE,\
+ port->membase + MCFUART_UCR);
+ }
+#endif
pp->imr &= ~MCFUART_UIR_TXREADY;
writeb(pp->imr, port->membase + MCFUART_UIMR);
}

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target/linux/coldfire/patches/006-Add-FEC-driver-support-for-MCF5445x-MCF5441x-MCF547x.patch Normal file
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target/linux/coldfire/patches/007-Add-eDMA-support-for-MCF5445x.patch Normal file
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target/linux/coldfire/patches/008-Add-DSPI-driver-support-for-MCF5445x-MCF5441x.patch Normal file
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target/linux/coldfire/patches/009-Add-ALSA-driver-for-MCF5445x.patch Normal file
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198
target/linux/coldfire/patches/010-Add-SRAM-char-device-driver-support-for-MCF5445x.patch Normal file
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@ -0,0 +1,198 @@
From f54ba59d355f59e4c01b5b9c7dbc2d27b47302d2 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:41 +0800
Subject: [PATCH 10/52] Add SRAM char device driver support for MCF5445x
Created "/dev/sram" device file and implemented the sram mmap() operation to
provide interface for userspace access.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/char/Kconfig | 11 ++++
drivers/char/Makefile | 2 +
drivers/char/sram.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 164 insertions(+), 0 deletions(-)
create mode 100644 drivers/char/sram.c
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -97,6 +97,17 @@ config DEVKMEM
kind of kernel debugging operations.
When in doubt, say "N".
+config DEVSRAM
+ tristate "/dev/sram virtual device support"
+ depends on M5445X
+ default m
+ help
+ Say Y here if you want to suppot the SRAM char device. When in
+ doubt, say "N".
+
+ It implements mmap system call to provide interface for
+ user space access.
+
config BFIN_JTAG_COMM
tristate "Blackfin JTAG Communication"
depends on BLACKFIN
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -87,3 +87,5 @@ obj-$(CONFIG_RAMOOPS) += ramoops.o
obj-$(CONFIG_JS_RTC) += js-rtc.o
js-rtc-y = rtc.o
+
+obj-$(CONFIG_DEVSRAM) += sram.o
--- /dev/null
+++ b/drivers/char/sram.c
@@ -0,0 +1,151 @@
+/*
+ * linux/drivers/char/sram.c
+ *
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Author: Lanttor.Guo@freescale.com
+ *
+ * SRAM char device driver, implements mmap() system call to provide
+ * interface for user space access.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/kdev_t.h>
+#include <asm/page.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+
+MODULE_LICENSE("GPL");
+
+static struct class *sram_class;
+static int sram_major;
+static int sram_minor;
+static struct cdev sram_cdev;
+
+/*
+ * Set up the cdev structure for sram.
+ */
+static void sram_setup_cdev(struct cdev *dev, int minor,
+ const struct file_operations *fops)
+{
+ int err, devno = MKDEV(sram_major, minor);
+
+ cdev_init(dev, fops);
+ dev->owner = THIS_MODULE;
+ dev->ops = fops;
+ err = cdev_add(dev, devno, 1);
+ /* Fail gracefully if need be */
+ if (err)
+ printk(KERN_NOTICE "Error %d adding sram%d", err, minor);
+}
+
+static int sram_open(struct inode *inode, struct file *filp)
+{
+ filp->f_mapping->backing_dev_info = &directly_mappable_cdev_bdi;
+ return 0;
+}
+
+static int sram_release(struct inode *inode, struct file *filp)
+{
+ return 0;
+}
+
+void sram_vma_open(struct vm_area_struct *vma)
+{
+ printk(KERN_DEBUG "Sram VMA open, virt %lx, phys %lx\n",
+ vma->vm_start,
+ CONFIG_SRAM_BASE + (vma->vm_pgoff << PAGE_SHIFT));
+}
+
+void sram_vma_close(struct vm_area_struct *vma)
+{
+ printk(KERN_DEBUG "Sram VMA close.\n");
+}
+
+
+static struct vm_operations_struct sram_remap_vm_ops = {
+ .open = sram_vma_open,
+ .close = sram_vma_close,
+};
+
+static int sram_remap_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ size_t size = vma->vm_end - vma->vm_start;
+
+ if (PAGE_ALIGN(size) > CONFIG_SRAM_SIZE) {
+ printk(KERN_ERR "required length exceed the size "
+ "of physical sram (%x)\n", CONFIG_SRAM_SIZE);
+ return -EAGAIN;
+ }
+
+ if ((CONFIG_SRAM_BASE + (vma->vm_pgoff << PAGE_SHIFT) + size)
+ > (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE)) {
+ printk(KERN_ERR "required sram range exceed the size "
+ "of phisical sram\n");
+ return -EAGAIN;
+ }
+
+ if (remap_pfn_range(vma, vma->vm_start,
+ (CONFIG_SRAM_BASE >> PAGE_SHIFT) + vma->vm_pgoff,
+ size,
+ vma->vm_page_prot)) {
+ printk(KERN_ERR "remap_pfn_range faile at %s()\n", __func__);
+ return -EAGAIN;
+ }
+
+ vma->vm_ops = &sram_remap_vm_ops;
+ return 0;
+}
+
+static const struct file_operations sram_ops = {
+ .owner = THIS_MODULE,
+ .open = sram_open,
+ .release = sram_release,
+ .mmap = sram_remap_mmap,
+};
+
+static int __init sram_chrdev_init(void)
+{
+ int minor_devs = 1;
+ int result;
+ dev_t dev = 0;
+ sram_minor = 0;
+
+ result = alloc_chrdev_region(&dev, sram_minor, minor_devs, "sram");
+ sram_major = MAJOR(dev);
+ if (result < 0) {
+ printk(KERN_WARNING "sram: can't get major %d\n", sram_major);
+ return result;
+ }
+
+ sram_setup_cdev(&sram_cdev, 0, &sram_ops);
+
+ sram_class = class_create(THIS_MODULE, "sram");
+ device_create(sram_class, NULL, MKDEV(sram_major, sram_minor),
+ NULL, "sram");
+
+ return 0;
+}
+
+static void sram_chrdev_cleanup(void)
+{
+ cdev_del(&sram_cdev);
+ device_destroy(sram_class, MKDEV(sram_major, sram_minor));
+ class_destroy(sram_class);
+ unregister_chrdev_region(MKDEV(sram_major, 0), 1);
+}
+
+module_init(sram_chrdev_init);
+module_exit(sram_chrdev_cleanup);

2514
target/linux/coldfire/patches/011-Add-CAU-driver-for-MCF5445x-and-MCF5441x.patch Normal file
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497
target/linux/coldfire/patches/012-Add-vDSO-support-for-Coldfire-platform.patch Normal file
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@ -0,0 +1,497 @@
From 1ba9968246337836bf0acdbf7733a628da5c5e42 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:42 +0800
Subject: [PATCH 12/52] Add vDSO support for Coldfire platform
This patch adds vDSO support for Coldfire platform.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/coldfire/common/entry.S | 36 ++++++++++
arch/m68k/coldfire/vdso/Makefile | 46 +++++++++++++
arch/m68k/coldfire/vdso/vdso-bin.S | 14 ++++
arch/m68k/coldfire/vdso/vdso-lib.S | 57 ++++++++++++++++
arch/m68k/coldfire/vdso/vdso-note.S | 27 ++++++++
arch/m68k/coldfire/vdso/vdso.c | 124 +++++++++++++++++++++++++++++++++++
arch/m68k/coldfire/vdso/vdso.lds.S | 89 +++++++++++++++++++++++++
arch/m68k/include/asm/auxvec.h | 9 +++
arch/m68k/mm/init.c | 3 +
9 files changed, 405 insertions(+), 0 deletions(-)
create mode 100644 arch/m68k/coldfire/vdso/Makefile
create mode 100644 arch/m68k/coldfire/vdso/vdso-bin.S
create mode 100644 arch/m68k/coldfire/vdso/vdso-lib.S
create mode 100644 arch/m68k/coldfire/vdso/vdso-note.S
create mode 100644 arch/m68k/coldfire/vdso/vdso.c
create mode 100644 arch/m68k/coldfire/vdso/vdso.lds.S
--- a/arch/m68k/coldfire/common/entry.S
+++ b/arch/m68k/coldfire/common/entry.S
@@ -69,6 +69,9 @@ ENTRY(buserr)
movew #0x2700,%sr /* lock interrupts */
#endif
SAVE_ALL_INT
+#ifdef CONFIG_VDSO
+ jsr check_vdso_atomic_cmpxchg_32
+#endif
#ifdef CONFIG_COLDFIRE_FOO
movew PT_0FF_SR(%sp),%d3 /* get original %sr */
oril #0x2000,%d3 /* set supervisor mode in it */
@@ -82,6 +85,9 @@ ENTRY(buserr)
ENTRY(trap)
SAVE_ALL_INT
+#ifdef CONFIG_VDSO
+ jsr check_vdso_atomic_cmpxchg_32
+#endif
GET_CURRENT(%d0)
movel %sp,%sp@- /* stack frame pointer argument */
jsr trap_c
@@ -213,6 +219,9 @@ do_delayed_trace:
*/
ENTRY(inthandler)
SAVE_ALL_INT
+#ifdef CONFIG_VDSO
+ jsr check_vdso_atomic_cmpxchg_32
+#endif
GET_CURRENT(%d0)
movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0
addil #0x10000,%d0
@@ -398,8 +407,35 @@ resume:
movew %a1@(TASK_THREAD+THREAD_SR),%d0
movew %d0,%sr
+#ifdef CONFIG_VDSO
+ /* save thread pointer */
+ lea _vdso_tp,%a0
+ movel (%a0),%a0
+ movel %a1@(TASK_INFO+TINFO_TP_VALUE),(%a0)
+#endif
rts
+#ifdef CONFIG_VDSO
+/* if interrupted PC is between 0x5fffe40c to 0x5ffffe412 */
+/* then set PC back to 0x5fffe40c (start addr of __kernel_atomic_cmpxchg_32) */
+/* note: these absolute addresses depend on vdso-lib.S and vdso.lds.S */
+ENTRY(check_vdso_atomic_cmpxchg_32)
+ movel %sp@(PT_OFF_PC),%d0
+ cmpil #0x5fffe414,%d0 /* __kernel_atomic_cmpxchg_32: line 4 */
+ ble label1
+ cmpil #0x5fffe412,%d0 /* __kernel_atomic_cmpxchg_32: line 3 */
+ beql label0
+ cmpil #0x5fffe40e,%d0 /* __kernel_atomic_cmpxchg_32: line 2 */
+ beql label0
+ jra label1
+label0:
+ /* __kernel_atomic_cmpxchg_32: line 1 */
+ movel #0x5fffe40c,%d0
+ movel %d0,%sp@(PT_OFF_PC)
+label1:
+ rts
+#endif
+
.data
ALIGN
sys_call_table:
--- /dev/null
+++ b/arch/m68k/coldfire/vdso/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile for arch/m68k/coldfire/vdso with special rules
+# for building the DSO lib
+#
+# Based on arch/sh/kernel/vsyscall/Makefile
+#
+# Kurt Mahan <kmahan@freescale.com>
+#
+
+obj-y := vdso.o vdso-bin.o
+
+$(obj)/vdso-bin.o: $(obj)/vdso.lds $(obj)/vdso-lib.so
+
+#
+# The DSO Lib
+#
+
+# special linker script for building DSO images
+quiet_cmd_vdso = VDSO $@
+ cmd_vdso = $(LD) -nostdlib --eh-frame-hdr $(SYSCFLAGS_$(@F)) \
+ -T $(obj)/vdso.lds $^ -o $@
+
+vdso-flags = -shared -s -soname=linux-gate.so.1
+
+SYSCFLAGS_vdso-lib.so = $(vdso-flags)
+
+$(obj)/vdso-lib.so: $(obj)/vdso-lib.o $(obj)/vdso-note.o
+ $(call if_changed,vdso)
+
+$(obj)/vdso.lds: $(srctree)/arch/m68k/coldfire/vdso/vdso.lds.S
+ cp $< $@
+
+#
+# Create a special relocatable object that should mirror the
+# symbol table and layout of the linked DSO lib. With ld -R
+# these symbols can be refered to in the kernel code rather
+# than as hand-coded addresses
+#
+# extra-y += vdso-syms.o
+# $(obj)/built-in.o: $(obj)/vdso-syms.o
+# $(obj)/built-in.o: ld_flags += -R (obj)/vdso-syms.o
+
+# SYSCFLAGS_vdso-syms.o = -r
+# $(obj)/vdso-syms.o: $(src)/vdso.lds \
+# $(obj)/vdso-lib.o $(obj)/vdso-note.o FORCE
+# $(call if_changed,vdso)
--- /dev/null
+++ b/arch/m68k/coldfire/vdso/vdso-bin.S
@@ -0,0 +1,14 @@
+/*
+ * Setup vdso lib (.so) as binary image.
+ */
+
+#include <linux/init.h>
+
+__INITDATA
+
+ .globl vdso_bin_start, vdso_bin_end
+vdso_bin_start:
+ .incbin "arch/m68k/coldfire/vdso/vdso-lib.so"
+vdso_bin_end:
+
+__FINIT
--- /dev/null
+++ b/arch/m68k/coldfire/vdso/vdso-lib.S
@@ -0,0 +1,57 @@
+/*
+ * VDSO userspace code
+ *
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Kurt Mahan <kmahan@freescale.com>
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+
+ .text
+/*
+ * Read the thread pointer into A0 (and D0, for compatibility).
+ */
+ENTRY(__kernel_read_tp)
+ .cfi_startproc
+ lea kuser_vdso_tp,%a0
+ movel (%a0), %d0
+ movel %d0,%a0
+ rts
+ .cfi_endproc
+ .size __kernel_read_tp,.-__kernel_read_tp
+
+/*
+ * Atomic compare exchange. Can not clobber any registers
+ * other than conditional codes.
+ */
+ENTRY(__kernel_atomic_cmpxchg_32)
+ .cfi_startproc
+ cmpl (%a0),%d0
+ bne label0
+ movel %d1, (%a0)
+ jmp label1
+label0:
+ movel (%a0),%d0
+label1:
+ rts
+ .cfi_endproc
+ .size __kernel_atomic_cmpxchg_32,.-__kernel_atomic_cmpxchg_32
+
+/*
+ * Atomic memory barrier. Can not clobber any registers
+ * other than condition codes.
+ */
+ENTRY(__kernel_atomic_barrier)
+ .cfi_startproc
+ /* no code needed for uniprocs */
+ rts
+ .cfi_endproc
+ .size __kernel_atomic_barrier,.-__kernel_atomic_barrier
+
+ .previous
--- /dev/null
+++ b/arch/m68k/coldfire/vdso/vdso-note.S
@@ -0,0 +1,27 @@
+/*
+ * This supplies .note.* sections to go into the PT_NOTE inside the vDSO text.
+ * Here we can supply some information useful to userland.
+ *
+ * Based on arch/sh/kernel/vsyscall/vsyscall-note.S
+ */
+
+#include <linux/uts.h>
+#include <linux/version.h>
+
+#define ASM_ELF_NOTE_BEGIN(name, flags, vendor, type) \
+ .section name, flags; \
+ .balign 4; \
+ .long 1f - 0f; /* name length */ \
+ .long 3f - 2f; /* data length */ \
+ .long type; /* note type */ \
+0: .asciz vendor; /* vendor name */ \
+1: .balign 4; \
+2:
+
+#define ASM_ELF_NOTE_END \
+3: .balign 4; /* pad out section */ \
+ .previous
+
+ ASM_ELF_NOTE_BEGIN(".note.kernel-version", "a", UTS_SYSNAME, 0)
+ .long LINUX_VERSION_CODE
+ ASM_ELF_NOTE_END
--- /dev/null
+++ b/arch/m68k/coldfire/vdso/vdso.c
@@ -0,0 +1,124 @@
+/*
+ * arch/m68k/coldfire/vdso/vdso.c
+ *
+ * Based on arch/sh/kernel/vsyscall/vsyscall.c
+ *
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Kurt Mahan <kmahan@freescale.com>
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gfp.h>
+#include <linux/module.h>
+#include <linux/elf.h>
+#include <linux/sched.h>
+#include <linux/err.h>
+
+/* Mapping vDSO at the default address (what would've been returned
+ * if VDSO_MBASE was 0) makes it impossible to extend data segment
+ * (through brk()) for static binaries. The vDSO fits into one page,
+ * so map it just before TASK_UNMAPPED_BASE.
+ */
+#define VDSO_MBASE (TASK_UNMAPPED_BASE - PAGE_SIZE)
+#define VDSO_VAR_OFFSET 4096
+
+unsigned int vdso_enabled = 1;
+EXPORT_SYMBOL_GPL(vdso_enabled);
+
+static struct page *vdso_pages[1];
+
+/* _vdso_var_start: vdso_page_start + offset_4K */
+/* it's used to save key values from kernel */
+void *_vdso_var_start;
+void *_vdso_tp;
+
+extern const char vdso_bin_start, vdso_bin_end;
+
+int __init vdso_init(void)
+{
+ void *vdso_page = (void *)get_zeroed_page(GFP_ATOMIC);
+ vdso_pages[0] = virt_to_page(vdso_page);
+
+ _vdso_var_start = (void *)(vdso_page + VDSO_VAR_OFFSET);
+ _vdso_tp = _vdso_var_start;
+
+ printk(KERN_INFO "** VDSO_INIT\n");
+
+ /* copy dso bin in */
+ memcpy(vdso_page,
+ &vdso_bin_start, &vdso_bin_end - &vdso_bin_start);
+
+ return 0;
+}
+
+/* setup VMA at program startup for the vdso page */
+int arch_setup_additional_pages(struct linux_binprm *bprm,
+ int executable_stack)
+{
+ struct mm_struct *mm = current->mm;
+ unsigned long addr;
+ int ret;
+
+ current->mm->context.vdso = 0;
+
+ down_write(&mm->mmap_sem);
+ addr = get_unmapped_area(NULL, VDSO_MBASE, PAGE_SIZE, 0, 0);
+ if (IS_ERR_VALUE(addr)) {
+ ret = addr;
+ goto up_fail;
+ }
+
+ ret = install_special_mapping(mm, addr, PAGE_SIZE,
+ VM_READ | VM_EXEC |
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC |
+ VM_ALWAYSDUMP,
+ vdso_pages);
+
+ if (unlikely(ret))
+ goto up_fail;
+
+ current->mm->context.vdso = (void *)addr;
+
+up_fail:
+#ifdef DEBUG
+ printk(KERN_DEBUG "arch_setup_additional_pages: addr: %lx; ret: %d\n",
+ addr, ret);
+#endif
+
+ up_write(&mm->mmap_sem);
+ return ret;
+}
+
+/*
+ * check vma name
+ */
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+ if (vma->vm_mm && vma->vm_start == (long)vma->vm_mm->context.vdso)
+ return "[vdso]";
+
+ return NULL;
+}
+
+struct vm_area_struct *get_gate_vma(struct task_struct *task)
+{
+ return NULL;
+}
+
+int in_gate_area(struct task_struct *task, unsigned long address)
+{
+ return 0;
+}
+
+int in_gate_area_no_task(unsigned long address)
+{
+ return 0;
+}
--- /dev/null
+++ b/arch/m68k/coldfire/vdso/vdso.lds.S
@@ -0,0 +1,89 @@
+/*
+ * Linker script for vdso DSO. The vdso page is an ELF shared
+ * object prelinked to its virtual address, and with only one read-only
+ * segment (that fits in one page). This script controls its layout.
+ *
+ * Based on arch/sh/kernel/vsyscall/vsyscall.lds.S
+ *
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Kurt Mahan <kmahan@freescale.com>
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", "elf32-m68k")
+OUTPUT_ARCH(m68k)
+
+/* The ELF entry point can be used to set the AT_SYSINFO value. */
+ENTRY(__kernel_read_tp);
+ENTRY(__kernel_atomic_cmpxchg_32);
+ENTRY(__kernel_atomic_barrier);
+
+SECTIONS
+{
+ . = 0x5fffe000 + SIZEOF_HEADERS;
+
+ .hash : { *(.hash) } :text
+ .gnu.hash : { *(.gnu.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+
+ /*
+ * This linker script is used both with -r and with -shared.
+ * For the layouts to match, we need to skip more than enough
+ * space for the dynamic symbol table et al. If this amount
+ * is insufficient, ld -shared will barf. Just increase it here.
+ */
+ . = 0x5fffe000 + 0x400;
+
+ .text : { *(.text) } :text
+ .note : { *(.note.*) } :text :note
+ .eh_frame_hdr : { *(.eh_frame_hdr ) } :text :eh_frame_hdr
+ .eh_frame : {
+ KEEP (*(.eh_frame))
+ LONG (0)
+ } :text
+ .dynamic : { *(.dynamic) } :text :dynamic
+ .useless : {
+ *(.got.plt) *(.got)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ } :text
+
+ . = 0x5fffe000 + 0x1000;
+ kuser_vdso_tp = .;
+}
+
+/*
+ * We must supply the ELF program headers explicitly to get just one
+ * PT_LOAD segment, and set the flags explicitly to make segments read-only.
+ */
+PHDRS
+{
+ text PT_LOAD FILEHDR PHDRS FLAGS(5); /* PF_R|PF_X */
+ dynamic PT_DYNAMIC FLAGS(4); /* PF_R */
+ note PT_NOTE FLAGS(4); /* PF_R */
+ eh_frame_hdr PT_GNU_EH_FRAME;
+}
+
+/*
+ * This controls what symbols we export from the DSO.
+ */
+VERSION
+{
+ LINUX_2.6 {
+ global:
+ __kernel_read_tp;
+ __kernel_atomic_cmpxchg_32;
+ __kernel_atomic_barrier;
+
+ local: *;
+ };
+}
--- a/arch/m68k/include/asm/auxvec.h
+++ b/arch/m68k/include/asm/auxvec.h
@@ -1,4 +1,13 @@
#ifndef __ASMm68k_AUXVEC_H
#define __ASMm68k_AUXVEC_H
+/*
+ * Architecture-neutral AT_ values in 0-17, leave some room
+ * for more of them.
+ */
+
+#ifdef CONFIG_VDSO
+/* Entry point to the vdso page */
+#define AT_SYSINFO_EHDR 33
+#endif
#endif
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -39,6 +39,9 @@
#include <asm/sections.h>
#include <asm/tlb.h>
+#ifdef CONFIG_VDSO
+int vdso_init(void);
+#endif
DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);

5318
target/linux/coldfire/patches/013-Add-MCD-DMA-driver-for-MCF547x-MCF548x.patch Normal file
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File diff suppressed because it is too large Load Diff

12
target/linux/coldfire/patches-2.6.31/019-Add-CFV4E-FPU-support-for-MCF547X_8X.patch → target/linux/coldfire/patches/014-Add-CFV4E-FPU-support-for-MCF547x-MCF548x.patch
View File

@ -1,11 +1,11 @@
From a324800cc0ac1a0bd2a596751d276f5daa9d17d2 Mon Sep 17 00:00:00 2001
From: Wang Huan <wanghuan@zch06.freescale.net>
Date: Thu, 4 Feb 2010 16:42:07 +0800
Subject: [PATCH 20/25] Add CFV4E FPU support for MCF547X_8X
From f5d90ef1f575d712c9f061dd5e4d48aa34d73bd0 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:43 +0800
Subject: [PATCH 14/52] Add CFV4E FPU support for MCF547x/MCF548x
Porting the fpu support from ltib-mcf547x_8x-20070107 (2.6.10)
Add CFV4E FPU support for MCF547x/MCF548x.
Signed-off-by: Lanttor Guo <lanttor.guo@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/include/asm/fpu.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)

104
target/linux/coldfire/patches/015-Add-driver-to-support-ten-UART-devices-on-MCF5441x.patch Normal file
View File

@ -0,0 +1,104 @@
From a42f35579c21ffdda461031a5d2d210e27eb506a Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:43 +0800
Subject: [PATCH 15/52] Add driver to support ten UART devices on MCF5441x
Test CPU board: UART0(J1), UART4(J3)
Test SER2 board: UART1(J11), UART2(J31)
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/tty/serial/Kconfig | 70 ++++++++++++++++++++++++++++++++++++++++++++
drivers/tty/serial/mcf.c | 2 +-
2 files changed, 71 insertions(+), 1 deletions(-)
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1070,6 +1070,76 @@ config SERIAL_MCF_CONSOLE
help
Enable a ColdFire internal serial port to be the system console.
+config SERIAL_MCF_UART0
+ bool "Coldfire UART0 device support"
+ depends on SERIAL_MCF && M5441X
+ default y
+ help
+ Enable ColdFire UART0 device configuration
+
+config SERIAL_MCF_UART1
+ bool "Coldfire UART1 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART1 device configuration
+
+config SERIAL_MCF_UART2
+ bool "Coldfire UART2 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART2 device configuration
+
+config SERIAL_MCF_UART3
+ bool "Coldfire UART3 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART3 device configuration
+
+config SERIAL_MCF_UART4
+ bool "Coldfire UART4 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART4 device configuration
+
+config SERIAL_MCF_UART5
+ bool "Coldfire UART5 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART5 device configuration
+
+config SERIAL_MCF_UART6
+ bool "Coldfire UART6 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART6 device configuration
+
+config SERIAL_MCF_UART7
+ bool "Coldfire UART7 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART7 device configuration
+
+config SERIAL_MCF_UART8
+ bool "Coldfire UART8 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART8 device configuration
+
+config SERIAL_MCF_UART9
+ bool "Coldfire UART9 device support"
+ depends on SERIAL_MCF && M5441X
+ default n
+ help
+ Enable ColdFire UART9 device configuration
+
config SERIAL_68360_SMC
bool "68360 SMC uart support"
depends on M68360
--- a/drivers/tty/serial/mcf.c
+++ b/drivers/tty/serial/mcf.c
@@ -527,7 +527,7 @@ static const struct uart_ops mcf_uart_op
.verify_port = mcf_verify_port,
};
-static struct mcf_uart mcf_ports[4];
+static struct mcf_uart mcf_ports[MAX_PORT_NUM];
#define MCF_MAXPORTS ARRAY_SIZE(mcf_ports)

1381
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68
target/linux/coldfire/patches/017-Add-cpu-dma-sync-function-for-coldfire-platform.patch Normal file
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@ -0,0 +1,68 @@
From 04491155db32bc1a9c0b367a7cac0f4a9ea9c4d2 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:43 +0800
Subject: [PATCH 17/52] Add cpu dma sync function for coldfire platform
This patch add dma_sync_sg_for_cpu() and dma_sync_single_for_cpu()
for coldfire platform. The previous empty function do not flush the
cache for the ram used for DMA.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/include/asm/dma-mapping.h | 10 ++++++++--
1 files changed, 8 insertions(+), 2 deletions(-)
--- a/arch/m68k/include/asm/dma-mapping.h
+++ b/arch/m68k/include/asm/dma-mapping.h
@@ -21,6 +21,9 @@ extern void *dma_alloc_coherent(struct d
extern void dma_free_coherent(struct device *, size_t,
void *, dma_addr_t);
+extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
+ enum dma_data_direction);
+
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *handle, gfp_t flag)
{
@@ -42,6 +45,7 @@ extern dma_addr_t dma_map_single(struct
static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
size_t size, enum dma_data_direction dir)
{
+ dma_sync_single_for_device(dev, addr, size, dir);
}
extern dma_addr_t dma_map_page(struct device *, struct page *,
@@ -50,6 +54,7 @@ extern dma_addr_t dma_map_page(struct de
static inline void dma_unmap_page(struct device *dev, dma_addr_t address,
size_t size, enum dma_data_direction dir)
{
+ dma_sync_single_for_device(dev, address, size, dir);
}
extern int dma_map_sg(struct device *, struct scatterlist *, int,
@@ -57,10 +62,9 @@ extern int dma_map_sg(struct device *, s
static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nhwentries, enum dma_data_direction dir)
{
+ dma_map_sg(dev, sg, nhwentries, dir);
}
-extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
- enum dma_data_direction);
extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
enum dma_data_direction);
@@ -75,11 +79,13 @@ static inline void dma_sync_single_range
static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
size_t size, enum dma_data_direction dir)
{
+ dma_sync_single_for_device(dev, handle, size, dir);
}
static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
+ dma_sync_sg_for_device(dev, sg, nents, dir);
}
static inline void dma_sync_single_range_for_cpu(struct device *dev,

973
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@ -0,0 +1,973 @@
From c1de95e3a608c48b5576e32181480930d9106ac4 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:44 +0800
Subject: [PATCH 18/52] Add SSD1289 TFT LCD framebuffer driver on TWR-MCF5441X
Add SSD1289 TFT LCD framebuffer driver on TWR-MCF5441X. Flexbus and spi
interfaces are both supported.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/coldfire/m5441x/config.c | 1 +
arch/m68k/coldfire/m5441x/devices.c | 1 +
arch/m68k/include/asm/fsl-ssd1289-fb.h | 93 ++++
drivers/video/Kconfig | 24 +
drivers/video/Makefile | 1 +
drivers/video/fsl-ssd1289-fb.c | 791 ++++++++++++++++++++++++++++++++
6 files changed, 911 insertions(+), 0 deletions(-)
create mode 100644 arch/m68k/include/asm/fsl-ssd1289-fb.h
create mode 100644 drivers/video/fsl-ssd1289-fb.c
--- a/arch/m68k/coldfire/m5441x/config.c
+++ b/arch/m68k/coldfire/m5441x/config.c
@@ -45,6 +45,7 @@
#include <asm/mcf5441x_fbcs.h>
#include <asm/mcf5441x_dtim.h>
#include <asm/mcf5441x_xbs.h>
+#include <asm/fsl-ssd1289-fb.h>
extern int get_irq_list(struct seq_file *p, void *v);
extern char _text, _end;
--- a/arch/m68k/coldfire/m5441x/devices.c
+++ b/arch/m68k/coldfire/m5441x/devices.c
@@ -33,6 +33,7 @@
#include <asm/mcfqspi.h>
#include <asm/mcfdspi.h>
#include <asm/cf_io.h>
+#include <asm/fsl-ssd1289-fb.h>
/*
* I2C: only support i2c0 module on m5441x platform
--- /dev/null
+++ b/arch/m68k/include/asm/fsl-ssd1289-fb.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Freescale MCF54418 SSD1289 TFT LCD framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __FSL_SSD1289_FB_H__
+#define __FSL_SSD1289_FB_H__
+
+#define SSD1289_REG_OSCILLATION 0x00
+#define SSD1289_REG_DRIVER_OUT_CTRL 0x01
+#define SSD1289_REG_LCD_DRIVE_AC 0x02
+#define SSD1289_REG_POWER_CTRL_1 0x03
+#define SSD1289_REG_COMPARE_1 0x05
+#define SSD1289_REG_COMPARE_2 0x06
+#define SSD1289_REG_DISPLAY_CTRL 0x07
+#define SSD1289_REG_FRAME_CYCLE 0x0b
+#define SSD1289_REG_POWER_CTRL_2 0x0c
+#define SSD1289_REG_POWER_CTRL_3 0x0d
+#define SSD1289_REG_POWER_CTRL_4 0x0e
+#define SSD1289_REG_GATE_SCAN_START 0x0f
+#define SSD1289_REG_SLEEP_MODE 0x10
+#define SSD1289_REG_ENTRY_MODE 0x11
+#define SSD1289_REG_OPT_SPEED_3 0x12
+#define SSD1289_REG_H_PORCH 0x16
+#define SSD1289_REG_V_PORCH 0x17
+#define SSD1289_REG_POWER_CTRL_5 0x1e
+#define SSD1289_REG_GDDRAM_DATA 0x22
+#define SSD1289_REG_WR_DATA_MASK_1 0x23
+#define SSD1289_REG_WR_DATA_MASK_2 0x24
+#define SSD1289_REG_FRAME_FREQUENCY 0x25
+#define SSD1289_REG_OPT_SPEED_1 0x28
+#define SSD1289_REG_OPT_SPEED_2 0x2f
+#define SSD1289_REG_GAMMA_CTRL_1 0x30
+#define SSD1289_REG_GAMMA_CTRL_2 0x31
+#define SSD1289_REG_GAMMA_CTRL_3 0x32
+#define SSD1289_REG_GAMMA_CTRL_4 0x33
+#define SSD1289_REG_GAMMA_CTRL_5 0x34
+#define SSD1289_REG_GAMMA_CTRL_6 0x35
+#define SSD1289_REG_GAMMA_CTRL_7 0x36
+#define SSD1289_REG_GAMMA_CTRL_8 0x37
+#define SSD1289_REG_GAMMA_CTRL_9 0x3a
+#define SSD1289_REG_GAMMA_CTRL_10 0x3b
+#define SSD1289_REG_V_SCROLL_CTRL_1 0x41
+#define SSD1289_REG_V_SCROLL_CTRL_2 0x42
+#define SSD1289_REG_H_RAM_ADR_POS 0x44
+#define SSD1289_REG_V_RAM_ADR_START 0x45
+#define SSD1289_REG_V_RAM_ADR_END 0x46
+#define SSD1289_REG_FIRST_WIN_START 0x48
+#define SSD1289_REG_FIRST_WIN_END 0x49
+#define SSD1289_REG_SECND_WIN_START 0x4a
+#define SSD1289_REG_SECND_WIN_END 0x4b
+#define SSD1289_REG_GDDRAM_X_ADDR 0x4e
+#define SSD1289_REG_GDDRAM_Y_ADDR 0x4f
+
+struct ssd1289 {
+ void __iomem *cmd;
+ void __iomem *data;
+} __packed;
+
+struct fsl_ssd1289_fb_info {
+ struct device *dev;
+ struct ssd1289 ssd1289_reg;
+ int openflag;
+ struct spi_device *spidev;
+
+ struct task_struct *task;
+ unsigned long pseudo_palette[16];
+};
+
+/* LCD description */
+struct fsl_ssd1289_fb_display {
+ /* Screen size */
+ unsigned short width;
+ unsigned short height;
+
+ /* Screen info */
+ unsigned short xres;
+ unsigned short yres;
+ unsigned short bpp;
+};
+
+#define FLEXBUS_LCD_CMD_ADDRESS 0xc0000000
+#define FLEXBUS_LCD_DATA_ADDRESS 0xc0010000
+
+#define SPI_LCD_BLOCK_SIZE 4096
+#define SPI_LCD_BLOCK_HALF_SIZE 2048
+#endif
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1980,6 +1980,30 @@ config FB_FSL_DIU
---help---
Framebuffer driver for the Freescale SoC DIU
+config FB_FSL_SSD1289
+ tristate "SSD1289 TFT LCD (Freescale MCF54418)"
+ depends on FB && M5441X
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ select FB_SYS_FOPS
+ ---help---
+ This is the framebuffer device driver for a Solomon Systech 240RGBx320
+ TFT LCD SSD1289.
+
+choice
+ prompt "SSD1289 LCD Controller Interface mode"
+ depends on FB_FSL_SSD1289
+
+config SSD1289_FLEXBUS_MODE
+ bool "SSD1289 LCD Controller Flexbus Interface mode"
+
+config SSD1289_SPI_MODE
+ bool "SSD1289 LCD Controller SPI Interface mode"
+ depends on SPI_DSPI && DSPI0
+
+endchoice
+
config FB_W100
tristate "W100 frame buffer support"
depends on FB && ARCH_PXA
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_IMX) += imx
obj-$(CONFIG_FB_S3C) += s3c-fb.o
obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
+obj-$(CONFIG_FB_FSL_SSD1289) += fsl-ssd1289-fb.o
obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o
obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/
obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
--- /dev/null
+++ b/drivers/video/fsl-ssd1289-fb.c
@@ -0,0 +1,791 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Freescale MCF54418 SSD1289 TFT LCD framebuffer driver
+ *
+ * Author: Alison Wang <b18965@freescale.com>
+ * Jason Jin <Jason.jin@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <linux/timer.h>
+#include <linux/kthread.h>
+#include <linux/spi/spi.h>
+
+#include <asm/mcf5441x_fbcs.h>
+#include <asm/mcf5441x_dspi.h>
+#include <asm/fsl-ssd1289-fb.h>
+#include <asm/mcf5441x_gpio.h>
+#include <asm/mcf5441x_ccm.h>
+#include <asm/mcf_edma.h>
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#endif
+
+#if defined(CONFIG_SSD1289_SPI_MODE)
+unsigned char spi_block_buffer[SPI_LCD_BLOCK_SIZE];
+
+static int ssd1289_spi_writeblock(struct fb_info *info,
+ unsigned char *daddr, int flag)
+{
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+ struct spi_device *devtmp;
+ int i;
+
+ for (i = 0; i < SPI_LCD_BLOCK_SIZE; i++) {
+ if (i % 2 == 0)
+ spi_block_buffer[i] = 0x01;
+ else if (flag == 1)
+ spi_block_buffer[i] = *(daddr + (i >> 1));
+ else if (flag == 0)
+ spi_block_buffer[i] = 0;
+ }
+
+ devtmp = fbinfo->spidev;
+ spi_write(devtmp, (const unsigned char *)spi_block_buffer,
+ SPI_LCD_BLOCK_SIZE);
+ return 0;
+}
+
+static int ssd1289_spi_write(struct fb_info *info,
+ unsigned short value, unsigned int flag)
+{
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+ struct spi_device *devtmp;
+ unsigned short tmpl;
+ unsigned short tmph;
+
+ devtmp = fbinfo->spidev;
+ if (flag == 1) {
+ /* D/C = 1 */
+ tmph = ((value >> 8) & 0xff) + 0x0100;
+ tmpl = (value & 0xff) + 0x0100;
+ spi_write(devtmp, (const u8 *)&tmph, sizeof(tmph));
+ spi_write(devtmp, (const u8 *)&tmpl, sizeof(tmpl));
+ } else {
+ /* D/C = 0 */
+ tmpl = (value & 0xff);
+ spi_write(devtmp, (const u8 *)&tmpl, sizeof(tmpl));
+ }
+ return 0;
+}
+#elif defined(CONFIG_SSD1289_FLEXBUS_MODE)
+static int ssd1289_flexbus_write(struct fb_info *info, unsigned short value,
+ unsigned int flag)
+{
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+ void __iomem *cmd_addr, *data_addr;
+
+ cmd_addr = fbinfo->ssd1289_reg.cmd;
+ data_addr = fbinfo->ssd1289_reg.data;
+
+ if (flag == 0)
+ out_be16(cmd_addr, value);
+ else
+ out_be16(data_addr, value);
+
+ return 0;
+}
+#endif
+
+static int ssd1289_write(struct fb_info *info, unsigned short value,
+ unsigned int flag)
+{
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ ssd1289_flexbus_write(info, value, flag);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+ ssd1289_spi_write(info, value, flag);
+#endif
+ return 0;
+}
+
+static void fsl_ssd1289_enable_lcd(struct fb_info *info)
+{
+ int i;
+
+#if defined(CONFIG_SSD1289_SPI_MODE)
+ int count;
+#elif defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ /* GPIO configuration */
+ MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_BE3_FB_A1 | MCF_GPIO_PAR_BE_BE2_FB_A0
+ | MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0;
+ MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS0_CS0;
+#endif
+
+ ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0);
+ ssd1289_write(info, 0x0200, 1);
+
+ ssd1289_write(info, SSD1289_REG_OSCILLATION, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ mdelay(100);
+
+ /* turn on the oscillator */
+ ssd1289_write(info, SSD1289_REG_OSCILLATION, 0);
+ ssd1289_write(info, 0x0001, 1);
+
+ mdelay(100);
+ /* power control 1 */
+ ssd1289_write(info, SSD1289_REG_POWER_CTRL_1, 0);
+ ssd1289_write(info, 0xaeac, 1);
+
+ /* power control 2 */
+ ssd1289_write(info, SSD1289_REG_POWER_CTRL_2, 0);
+ ssd1289_write(info, 0x0007, 1);
+
+ /* power control 3 */
+ ssd1289_write(info, SSD1289_REG_POWER_CTRL_3, 0);
+ ssd1289_write(info, 0x000f, 1);
+
+ /* power control 4 */
+ ssd1289_write(info, SSD1289_REG_POWER_CTRL_4, 0);
+ ssd1289_write(info, 0x2900, 1);
+
+ /* power control 5 */
+ ssd1289_write(info, SSD1289_REG_POWER_CTRL_5, 0);
+ ssd1289_write(info, 0x00b3, 1);
+
+ mdelay(15);
+ /* driver output control */
+ ssd1289_write(info, SSD1289_REG_DRIVER_OUT_CTRL, 0);
+ ssd1289_write(info, 0x2b3f, 1);
+
+ /* lcd-driving-waveform control */
+ ssd1289_write(info, SSD1289_REG_LCD_DRIVE_AC, 0);
+ ssd1289_write(info, 0x0600, 1);
+
+ /* sleep mode */
+ ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ /* entry mode */
+ ssd1289_write(info, SSD1289_REG_ENTRY_MODE, 0);
+ ssd1289_write(info, 0x60a8, 1);
+
+ mdelay(15);
+ /* compare register */
+ ssd1289_write(info, SSD1289_REG_COMPARE_1, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ ssd1289_write(info, SSD1289_REG_COMPARE_2, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ /* horizontal porch */
+ ssd1289_write(info, SSD1289_REG_H_PORCH, 0);
+ ssd1289_write(info, 0xef1c, 1);
+
+ /* vertical porch */
+ ssd1289_write(info, SSD1289_REG_V_PORCH, 0);
+ ssd1289_write(info, 0x0003, 1);
+
+ /* display control */
+ ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0);
+ ssd1289_write(info, 0x0233, 1);
+
+ /* frame cycle control */
+ ssd1289_write(info, SSD1289_REG_FRAME_CYCLE, 0);
+ ssd1289_write(info, 0x5312, 1);
+
+ /* gate scan position */
+ ssd1289_write(info, SSD1289_REG_GATE_SCAN_START, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ mdelay(20);
+ /* vertical scroll control */
+ ssd1289_write(info, SSD1289_REG_V_SCROLL_CTRL_1, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ ssd1289_write(info, SSD1289_REG_V_SCROLL_CTRL_2, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ /* 1st screen driving position */
+ ssd1289_write(info, SSD1289_REG_FIRST_WIN_START, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ ssd1289_write(info, SSD1289_REG_FIRST_WIN_END, 0);
+ ssd1289_write(info, 0x013F, 1);
+
+ /* 2nd screen driving position */
+ ssd1289_write(info, SSD1289_REG_SECND_WIN_START, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ ssd1289_write(info, SSD1289_REG_SECND_WIN_END, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ mdelay(20);
+ /* gamma control */
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_1, 0);
+ ssd1289_write(info, 0x0707, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_2, 0);
+ ssd1289_write(info, 0x0704, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_3, 0);
+ ssd1289_write(info, 0x0204, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_4, 0);
+ ssd1289_write(info, 0x0201, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_5, 0);
+ ssd1289_write(info, 0x0203, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_6, 0);
+ ssd1289_write(info, 0x0204, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_7, 0);
+ ssd1289_write(info, 0x0204, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_8, 0);
+ ssd1289_write(info, 0x0502, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_9, 0);
+ ssd1289_write(info, 0x0302, 1);
+
+ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_10, 0);
+ ssd1289_write(info, 0x0500, 1);
+
+ /* ram write data mask */
+ ssd1289_write(info, SSD1289_REG_WR_DATA_MASK_1, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ ssd1289_write(info, SSD1289_REG_WR_DATA_MASK_2, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ /* frame frequency control */
+ ssd1289_write(info, SSD1289_REG_FRAME_FREQUENCY, 0);
+ ssd1289_write(info, 0xe000, 1);
+
+ /* optimize data access speed */
+ ssd1289_write(info, SSD1289_REG_OPT_SPEED_1, 0);
+ ssd1289_write(info, 0x0006, 1);
+
+ ssd1289_write(info, SSD1289_REG_OPT_SPEED_2, 0);
+ ssd1289_write(info, 0x12ae, 1);
+
+ ssd1289_write(info, SSD1289_REG_OPT_SPEED_3, 0);
+ ssd1289_write(info, 0x6ceb, 1);
+
+ /* horizontal ram address position */
+ ssd1289_write(info, SSD1289_REG_H_RAM_ADR_POS, 0);
+ ssd1289_write(info, 0xef00, 1);
+
+ /* vertical ram address position */
+ ssd1289_write(info, SSD1289_REG_V_RAM_ADR_START, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ ssd1289_write(info, SSD1289_REG_V_RAM_ADR_END, 0);
+ ssd1289_write(info, 0x013f, 1);
+
+ mdelay(20);
+
+ /* set start address counter */
+ ssd1289_write(info, SSD1289_REG_GDDRAM_X_ADDR, 0);
+ ssd1289_write(info, 0x00ef, 1);
+
+ ssd1289_write(info, SSD1289_REG_GDDRAM_Y_ADDR, 0);
+ ssd1289_write(info, 0x0000, 1);
+
+ ssd1289_write(info, SSD1289_REG_GDDRAM_DATA, 0);
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ for (i = 0; i < info->screen_size; i += 2)
+ ssd1289_write(info, 0, 1);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+ count = info->screen_size / SPI_LCD_BLOCK_HALF_SIZE;
+ for (i = 0; i < count; i++)
+ ssd1289_spi_writeblock(info, NULL, 0);
+#endif
+}
+
+static void fsl_ssd1289_disable_lcd(struct fb_info *info)
+{
+ ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0);
+ ssd1289_write(info, 0x0200, 1);
+
+ ssd1289_write(info, SSD1289_REG_OSCILLATION, 0);
+ ssd1289_write(info, 0x0000, 1);
+}
+
+static int ssd1289fbd(void *arg)
+{
+ struct fb_info *info = arg;
+ int i;
+ unsigned short *buf_p;
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+#if defined(CONFIG_SSD1289_SPI_MODE)
+ unsigned char *bufspi_p;
+ int count;
+#endif
+
+ while (!kthread_should_stop()) {
+ set_current_state(TASK_INTERRUPTIBLE);
+
+ if (fbinfo->openflag == 1) {
+ buf_p = (unsigned short *)(info->screen_base);
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ for (i = 0; i < info->screen_size; i += 2) {
+ ssd1289_write(info, *buf_p, 1);
+ buf_p++;
+ }
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+ bufspi_p = (unsigned char *)buf_p;
+ count = info->screen_size / SPI_LCD_BLOCK_HALF_SIZE;
+ for (i = 0; i < count; i++)
+ ssd1289_spi_writeblock(info, (bufspi_p +
+ SPI_LCD_BLOCK_HALF_SIZE * i), 1);
+#endif
+ }
+ schedule_timeout(HZ/25);
+ }
+
+ return 0;
+}
+
+static int fsl_ssd1289_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ if (var->xres_virtual < var->xres)
+ var->xres_virtual = var->xres;
+ if (var->yres_virtual < var->yres)
+ var->yres_virtual = var->yres;
+
+ if (var->xoffset < 0)
+ var->xoffset = 0;
+
+ if (var->yoffset < 0)
+ var->yoffset = 0;
+
+ if (var->xoffset + info->var.xres > info->var.xres_virtual)
+ var->xoffset = info->var.xres_virtual - info->var.xres;
+
+ if (var->yoffset + info->var.yres > info->var.yres_virtual)
+ var->yoffset = info->var.yres_virtual - info->var.yres;
+
+ switch (var->bits_per_pixel) {
+ case 8:
+ /* 8 bpp, 332 format */
+ var->red.length = 3;
+ var->red.offset = 5;
+ var->red.msb_right = 0;
+
+ var->green.length = 3;
+ var->green.offset = 2;
+ var->green.msb_right = 0;
+
+ var->blue.length = 2;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 16:
+ /* 16 bpp, 565 format */
+ var->red.length = 5;
+ var->red.offset = 11;
+ var->red.msb_right = 0;
+
+ var->green.length = 6;
+ var->green.offset = 5;
+ var->green.msb_right = 0;
+
+ var->blue.length = 5;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ default:
+ printk(KERN_ERR "Depth not supported: %u BPP\n",
+ var->bits_per_pixel);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int fsl_ssd1289_set_par(struct fb_info *info)
+{
+ struct fb_var_screeninfo *var = &info->var;
+
+ switch (var->bits_per_pixel) {
+ case 16:
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ break;
+ case 8:
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ break;
+ default:
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ break;
+ }
+
+ return 0;
+}
+
+static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
+{
+ return ((val<<width) + 0x7FFF - val)>>16;
+}
+
+static int fsl_ssd1289_setcolreg(unsigned regno,
+ unsigned red, unsigned green, unsigned blue,
+ unsigned transp, struct fb_info *info)
+{
+ int ret = 1;
+
+ /*
+ * If greyscale is true, then we convert the RGB value
+ * to greyscale no matter what visual we are using.
+ */
+ if (info->var.grayscale)
+ red = green = blue = (19595 * red + 38470 * green +
+ 7471 * blue) >> 16;
+ switch (info->fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ if (regno < 16) {
+ u32 *pal = info->pseudo_palette;
+ u32 value;
+
+ red = CNVT_TOHW(red, info->var.red.length);
+ green = CNVT_TOHW(green, info->var.green.length);
+ blue = CNVT_TOHW(blue, info->var.blue.length);
+ transp = CNVT_TOHW(transp, info->var.transp.length);
+
+ value = (red << info->var.red.offset) |
+ (green << info->var.green.offset) |
+ (blue << info->var.blue.offset) |
+ (transp << info->var.transp.offset);
+
+ pal[regno] = value;
+ ret = 0;
+ }
+ break;
+ case FB_VISUAL_STATIC_PSEUDOCOLOR:
+ case FB_VISUAL_PSEUDOCOLOR:
+ break;
+ }
+ return ret;
+}
+
+static int fsl_ssd1289_blank(int blank_mode, struct fb_info *info)
+{
+ if (blank_mode == FB_BLANK_POWERDOWN)
+ fsl_ssd1289_disable_lcd(info);
+ else
+ fsl_ssd1289_enable_lcd(info);
+
+ return 0;
+}
+
+static int fsl_ssd1289_open(struct fb_info *info, int user)
+{
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+ struct task_struct *task;
+ int ret;
+
+ if (fbinfo->openflag == 0) {
+ memset(info->screen_base, 0, info->screen_size);
+ fsl_ssd1289_enable_lcd(info);
+
+ task = kthread_run(ssd1289fbd, info, "SSD1289 LCD");
+ if (IS_ERR(task)) {
+ ret = PTR_ERR(task);
+ return ret;
+ }
+ fbinfo->task = task;
+ }
+
+ fbinfo->openflag = 1;
+ return 0;
+}
+
+static int fsl_ssd1289_release(struct fb_info *info, int user)
+{
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+
+ fbinfo->openflag = 0;
+ if (fbinfo->task) {
+ struct task_struct *task = fbinfo->task;
+ fbinfo->task = NULL;
+ kthread_stop(task);
+ }
+
+ memset(info->screen_base, 0, info->screen_size);
+ fsl_ssd1289_disable_lcd(info);
+ return 0;
+}
+
+static struct fb_ops fsl_ssd1289_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = fsl_ssd1289_check_var,
+ .fb_set_par = fsl_ssd1289_set_par,
+ .fb_setcolreg = fsl_ssd1289_setcolreg,
+ .fb_blank = fsl_ssd1289_blank,
+ .fb_open = fsl_ssd1289_open,
+ .fb_release = fsl_ssd1289_release,
+ .fb_copyarea = cfb_copyarea,
+ .fb_fillrect = cfb_fillrect,
+ .fb_imageblit = cfb_imageblit,
+};
+
+static int fsl_ssd1289_map_video_memory(struct fb_info *info)
+{
+ unsigned int map_size = info->fix.smem_len;
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+
+ fbinfo->ssd1289_reg.cmd =
+ ioremap_nocache(FLEXBUS_LCD_CMD_ADDRESS, 2);
+ fbinfo->ssd1289_reg.data =
+ ioremap_nocache(FLEXBUS_LCD_DATA_ADDRESS, 2);
+#endif
+
+ info->screen_base = kmalloc(map_size, GFP_KERNEL);
+ info->fix.smem_start = virt_to_phys(info->screen_base);
+ info->screen_size = info->fix.smem_len;
+
+ if (info->screen_base)
+ memset(info->screen_base, 0, map_size);
+
+ return info->screen_base ? 0 : -ENOMEM;
+}
+
+static inline void fsl_ssd1289_unmap_video_memory(struct fb_info *info)
+{
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ struct fsl_ssd1289_fb_info *fbinfo = info->par;
+
+ iounmap(fbinfo->ssd1289_reg.cmd);
+ iounmap(fbinfo->ssd1289_reg.data);
+#endif
+ kfree(info->screen_base);
+}
+
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+static int fsl_ssd1289_probe(struct platform_device *pdev)
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+static int fsl_ssd1289_probe(struct spi_device *spi)
+#endif
+{
+ struct fsl_ssd1289_fb_info *fbinfo;
+ struct fb_info *info;
+ struct fsl_ssd1289_fb_display *display;
+ int ret;
+ unsigned long smem_len;
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ info = framebuffer_alloc(sizeof(struct fsl_ssd1289_fb_info),
+ &pdev->dev);
+ if (!info)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, info);
+
+ fbinfo = info->par;
+ fbinfo->dev = &pdev->dev;
+ display = pdev->dev.platform_data;
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+ info = framebuffer_alloc(sizeof(struct fsl_ssd1289_fb_info),
+ &spi->dev);
+ if (!info)
+ return -ENOMEM;
+
+ dev_set_drvdata(&spi->dev, info);
+
+ fbinfo = info->par;
+ fbinfo->dev = &spi->dev;
+ fbinfo->spidev = spi;
+ display = spi->dev.platform_data;
+#endif
+
+ fbinfo->openflag = 0;
+ info->fix.type = FB_TYPE_PACKED_PIXELS;
+ info->fix.type_aux = 0;
+ info->fix.xpanstep = 0;
+ info->fix.ypanstep = 0;
+ info->fix.ywrapstep = 0;
+ info->fix.accel = FB_ACCEL_NONE;
+
+ info->var.nonstd = 0;
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->var.accel_flags = 0;
+ info->var.vmode = FB_VMODE_NONINTERLACED;
+
+ info->fbops = &fsl_ssd1289_ops;
+ info->flags = FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT
+ | FBINFO_HWACCEL_COPYAREA;
+ info->pseudo_palette = &fbinfo->pseudo_palette;
+
+ /* find maximum required memory size for display */
+ smem_len = display->xres;
+ smem_len *= display->yres;
+ smem_len *= display->bpp;
+ smem_len >>= 3;
+ if (info->fix.smem_len < smem_len)
+ info->fix.smem_len = smem_len;
+
+ /* Intialize video memory */
+ ret = fsl_ssd1289_map_video_memory(info);
+ if (ret) {
+ printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
+ ret = -ENOMEM;
+ goto dealloc_fb;
+ }
+
+ info->var.xres = display->xres;
+ info->var.yres = display->yres;
+ info->var.bits_per_pixel = display->bpp;
+ info->fix.line_length = (info->var.xres * info->var.bits_per_pixel) / 8;
+
+ fsl_ssd1289_check_var(&info->var, info);
+
+ ret = register_framebuffer(info);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register framebuffer device: %d\n",
+ ret);
+ goto free_video_memory;
+ }
+
+ printk(KERN_INFO "fb: SSD1289 TFT LCD Framebuffer Driver\n");
+ return 0;
+
+free_video_memory:
+ fsl_ssd1289_unmap_video_memory(info);
+dealloc_fb:
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ platform_set_drvdata(pdev, NULL);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+ dev_set_drvdata(&spi->dev, NULL);
+#endif
+ framebuffer_release(info);
+ return ret;
+}
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+static int fsl_ssd1289_remove(struct platform_device *pdev)
+{
+ struct fb_info *info = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+static int fsl_ssd1289_remove(struct spi_device *spi)
+{
+ struct fb_info *info = dev_get_drvdata(&spi->dev);
+
+ dev_set_drvdata(&spi->dev, NULL);
+#endif
+ unregister_framebuffer(info);
+ fsl_ssd1289_unmap_video_memory(info);
+ framebuffer_release(info);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+static int fsl_ssd1289_suspend(struct platform_device *dev, pm_message_t state)
+{
+ struct fb_info *info = platform_get_drvdata(dev);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+static int fsl_ssd1289_suspend(struct spi_device *spi, pm_message_t state)
+{
+ struct fb_info *info = dev_get_drvdata(&spi->dev);
+#endif
+ /* enter into sleep mode */
+ ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0);
+ ssd1289_write(info, 0x0001, 1);
+ return 0;
+}
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+static int fsl_ssd1289_resume(struct platform_device *dev)
+{
+ struct fb_info *info = platform_get_drvdata(dev);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+static int fsl_ssd1289_resume(struct spi_device *spi)
+{
+ struct fb_info *info = dev_get_drvdata(&spi->dev);
+#endif
+ /* leave sleep mode */
+ ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0);
+ ssd1289_write(info, 0x0000, 1);
+ return 0;
+}
+#else
+#define fsl_ssd1289_suspend NULL
+#define fsl_ssd1289_resume NULL
+#endif
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+static struct platform_driver fsl_ssd1289_driver = {
+ .probe = fsl_ssd1289_probe,
+ .remove = fsl_ssd1289_remove,
+ .suspend = fsl_ssd1289_suspend,
+ .resume = fsl_ssd1289_resume,
+ .driver = {
+ .name = "fsl-ssd1289",
+ .owner = THIS_MODULE,
+ },
+};
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+static struct spi_driver spi_ssd1289_driver = {
+ .driver = {
+ .name = "spi-ssd1289",
+ .bus = &spi_bus_type,
+ .owner = THIS_MODULE,
+ },
+ .probe = fsl_ssd1289_probe,
+ .remove = fsl_ssd1289_remove,
+ .suspend = fsl_ssd1289_suspend,
+ .resume = fsl_ssd1289_resume,
+};
+#endif
+
+static int __devinit fsl_ssd1289_init(void)
+{
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ return platform_driver_register(&fsl_ssd1289_driver);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+ return spi_register_driver(&spi_ssd1289_driver);
+#endif
+}
+
+static void __exit fsl_ssd1289_exit(void)
+{
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ return platform_driver_unregister(&fsl_ssd1289_driver);
+#elif defined(CONFIG_SSD1289_SPI_MODE)
+ return spi_unregister_driver(&spi_ssd1289_driver);
+#endif
+}
+
+module_init(fsl_ssd1289_init);
+module_exit(fsl_ssd1289_exit);
+
+MODULE_AUTHOR("Alison Wang <b18965@freescale.com>");
+MODULE_DESCRIPTION("Freescale MCF54418 SSD1289 TFT LCD Framebuffer Driver");
+MODULE_LICENSE("GPL");

27
target/linux/coldfire/patches/019-Fix-the-format-field-for-the-Coldfire-exception-fram.patch Normal file
View File

@ -0,0 +1,27 @@
From 53cfdf92d9b68f5dac006853dd6727d7bf666b17 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:44 +0800
Subject: [PATCH 19/52] Fix the format field for the Coldfire exception frame
Different with M68K, the correct format field encoding
for ColdFire should be 4, 5, 6 or 7.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/mm/fault.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
--- a/arch/m68k/mm/fault.c
+++ b/arch/m68k/mm/fault.c
@@ -45,7 +45,11 @@ int send_fault_sig(struct pt_regs *regs)
regs->stkadj = frame_extra_sizes[regs->format];
tregs = (struct pt_regs *)((ulong)regs + regs->stkadj);
tregs->vector = regs->vector;
+#ifdef CONFIG_COLDFIRE
+ tregs->format = regs->stkadj + 4;
+#else
tregs->format = 0;
+#endif
tregs->pc = fixup->fixup;
tregs->sr = regs->sr;
return -1;

1257
target/linux/coldfire/patches/020-Add-dual-FEC-1588-timer-support.patch Normal file
View File

File diff suppressed because it is too large Load Diff

6152
target/linux/coldfire/patches/021-Add-ethernet-switch-driver-for-MCF54418.patch Normal file
View File

File diff suppressed because it is too large Load Diff

32
target/linux/coldfire/patches/022-Redefine-I-O-read-and-write-functions.patch Normal file
View File

@ -0,0 +1,32 @@
From f8dab3ef2c0da1c50dee07142c0b8088da61bc82 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:45 +0800
Subject: [PATCH 22/52] Redefine I/O read and write functions
Redefine readb(), writeb(), readw(), writew(), readl(), write()
functions.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/include/asm/cf_io.h | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
--- a/arch/m68k/include/asm/cf_io.h
+++ b/arch/m68k/include/asm/cf_io.h
@@ -20,6 +20,16 @@
#include <asm-generic/iomap.h>
+/*
+ * These should be valid on any ioremap()ed region
+ */
+#define readb(addr) in_8(addr)
+#define writeb(val, addr) out_8((addr), (val))
+#define readw(addr) in_le16(addr)
+#define writew(val, addr) out_le16((addr), (val))
+#define readl(addr) in_le32(addr)
+#define writel(val, addr) out_le32((addr), (val))
+
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)

357
target/linux/coldfire/patches/023-Replace-readl-and-writel-for-FEC-driver.patch Normal file
View File

@ -0,0 +1,357 @@
From f7df9a8f3ce3a600ceeb7302bf0de899f321c818 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:45 +0800
Subject: [PATCH 23/52] Replace readl and writel for FEC driver
Replace readl and writel by fec_readl and fec_writel
for FEC driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/net/fec.c | 129 ++++++++++++++++++++++++++++-------------------------
1 files changed, 68 insertions(+), 61 deletions(-)
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -244,6 +244,11 @@ static void fec_stop(struct net_device *
/* Transmitter timeout */
#define TX_TIMEOUT (2 * HZ)
+#define fec_readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+#define fec_writel(b, addr) \
+ (void)((*(volatile unsigned int *) (addr)) = (b))
+
static void *swap_buffer(void *bufaddr, int len)
{
int i;
@@ -347,7 +352,7 @@ fec_enet_start_xmit(struct sk_buff *skb,
bdp->cbd_sc = status;
/* Trigger transmission start */
- writel(0, fep->hwp + FEC_X_DES_ACTIVE);
+ fec_writel(0, fep->hwp + FEC_X_DES_ACTIVE);
/* If this was the last BD in the ring, start at the beginning again. */
if (status & BD_ENET_TX_WRAP)
@@ -390,8 +395,8 @@ fec_enet_interrupt(int irq, void * dev_i
irqreturn_t ret = IRQ_NONE;
do {
- int_events = readl(fep->hwp + FEC_IEVENT);
- writel(int_events, fep->hwp + FEC_IEVENT);
+ int_events = fec_readl(fep->hwp + FEC_IEVENT);
+ fec_writel(int_events, fep->hwp + FEC_IEVENT);
#ifdef CONFIG_FEC_1588
if (__raw_readb(MCF_DTIM1_DTER) & MCF_DTIM_DTER_REF)
@@ -646,7 +651,7 @@ rx_processing_done:
* incoming frames. On a heavily loaded network, we should be
* able to keep up at the expense of system resources.
*/
- writel(0, fep->hwp + FEC_R_DES_ACTIVE);
+ fec_writel(0, fep->hwp + FEC_R_DES_ACTIVE);
}
fep->cur_rx = bdp;
@@ -686,9 +691,9 @@ static void __inline__ fec_get_mac(struc
*/
if (!is_valid_ether_addr(iap)) {
*((unsigned long *) &tmpaddr[0]) =
- be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
+ be32_to_cpu(fec_readl(fep->hwp + FEC_ADDR_LOW));
*((unsigned short *) &tmpaddr[4]) =
- be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
+ be16_to_cpu(fec_readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
iap = &tmpaddr[0];
}
@@ -740,9 +745,9 @@ static void fec_enet_adjust_link(struct
if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
#ifdef CONFIG_FEC_1588
- writel(0x00000012, fep->hwp + FEC_ECNTRL);
+ fec_writel(0x00000012, fep->hwp + FEC_ECNTRL);
#else
- writel(0x00000002, fep->hwp + FEC_ECNTRL);
+ fec_writel(0x00000002, fep->hwp + FEC_ECNTRL);
#endif
status_change = 1;
}
@@ -763,7 +768,7 @@ static int fec_enet_mdio_read(struct mii
init_completion(&fep->mdio_done);
/* start a read op */
- writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+ fec_writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
@@ -777,7 +782,7 @@ static int fec_enet_mdio_read(struct mii
}
/* return value */
- return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
+ return FEC_MMFR_DATA(fec_readl(fep->hwp + FEC_MII_DATA));
}
static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
@@ -790,7 +795,7 @@ static int fec_enet_mdio_write(struct mi
init_completion(&fep->mdio_done);
/* start a write op */
- writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
+ fec_writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
FEC_MMFR_TA | FEC_MMFR_DATA(value),
fep->hwp + FEC_MII_DATA);
@@ -905,7 +910,7 @@ static int fec_enet_mii_init(struct plat
* Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
*/
fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+ fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
fep->mii_bus = mdiobus_alloc();
if (fep->mii_bus == NULL) {
@@ -1151,30 +1156,30 @@ static void set_multicast_list(struct ne
unsigned char hash;
if (dev->flags & IFF_PROMISC) {
- tmp = readl(fep->hwp + FEC_R_CNTRL);
+ tmp = fec_readl(fep->hwp + FEC_R_CNTRL);
tmp |= 0x8;
- writel(tmp, fep->hwp + FEC_R_CNTRL);
+ fec_writel(tmp, fep->hwp + FEC_R_CNTRL);
return;
}
- tmp = readl(fep->hwp + FEC_R_CNTRL);
+ tmp = fec_readl(fep->hwp + FEC_R_CNTRL);
tmp &= ~0x8;
- writel(tmp, fep->hwp + FEC_R_CNTRL);
+ fec_writel(tmp, fep->hwp + FEC_R_CNTRL);
if (dev->flags & IFF_ALLMULTI) {
/* Catch all multicast addresses, so set the
* filter to all 1's
*/
- writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
- writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
+ fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+ fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
return;
}
/* Clear filter and add the addresses in hash register
*/
- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
+ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
netdev_for_each_mc_addr(ha, dev) {
/* Only support group multicast for now */
@@ -1198,13 +1203,13 @@ static void set_multicast_list(struct ne
hash = (crc >> (32 - HASH_BITS)) & 0x3f;
if (hash > 31) {
- tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+ tmp = fec_readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
tmp |= 1 << (hash - 32);
- writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+ fec_writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
} else {
- tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
+ tmp = fec_readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
tmp |= 1 << hash;
- writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
+ fec_writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
}
}
}
@@ -1221,10 +1226,10 @@ fec_set_mac_address(struct net_device *d
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
- writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
+ fec_writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
(dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
fep->hwp + FEC_ADDR_LOW);
- writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
+ fec_writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
fep->hwp + FEC_ADDR_HIGH);
return 0;
}
@@ -1323,7 +1328,7 @@ fec_restart(struct net_device *dev, int
u32 val, temp_mac[2];
/* Whack a reset. We should wait for this. */
- writel(1, fep->hwp + FEC_ECNTRL);
+ fec_writel(1, fep->hwp + FEC_ECNTRL);
udelay(10);
/*
@@ -1332,31 +1337,32 @@ fec_restart(struct net_device *dev, int
*/
if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
- writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
- writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+ fec_writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+ fec_writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
}
#ifdef CONFIG_FEC_1588
- writel(0x7fff8000, fep->hwp + FEC_IEVENT);
+ fec_writel(0x7fff8000, fep->hwp + FEC_IEVENT);
#else
/* Clear any outstanding interrupt. */
- writel(0xffc00000, fep->hwp + FEC_IEVENT);
+ fec_writel(0xffc00000, fep->hwp + FEC_IEVENT);
#endif
/* Reset all multicast. */
- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
+ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
#ifndef CONFIG_M5272
- writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
- writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
+ fec_writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
+ fec_writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
#endif
/* Set maximum receive buffer size. */
- writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
+ fec_writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
/* Set receive and transmit descriptor base. */
- writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
- writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
+ fec_writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
+ fec_writel((unsigned long)fep->bd_dma +
+ sizeof(struct bufdesc) * RX_RING_SIZE,
fep->hwp + FEC_X_DES_START);
fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
@@ -1374,24 +1380,24 @@ fec_restart(struct net_device *dev, int
/* Enable MII mode */
if (duplex) {
/* MII enable / FD enable */
- writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
- writel(0x04, fep->hwp + FEC_X_CNTRL);
+ fec_writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
+ fec_writel(0x04, fep->hwp + FEC_X_CNTRL);
} else {
/* MII enable / No Rcv on Xmit */
- writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
- writel(0x0, fep->hwp + FEC_X_CNTRL);
+ fec_writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
+ fec_writel(0x0, fep->hwp + FEC_X_CNTRL);
}
fep->full_duplex = duplex;
/* Set MII speed */
- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+ fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
/*
* The phy interface and speed need to get configured
* differently on enet-mac.
*/
if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
- val = readl(fep->hwp + FEC_R_CNTRL);
+ val = fec_readl(fep->hwp + FEC_R_CNTRL);
/* MII or RMII */
if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
@@ -1405,23 +1411,23 @@ fec_restart(struct net_device *dev, int
else
val |= (1 << 9);
- writel(val, fep->hwp + FEC_R_CNTRL);
+ fec_writel(val, fep->hwp + FEC_R_CNTRL);
} else {
#ifdef FEC_MIIGSK_ENR
if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
/* disable the gasket and wait */
- writel(0, fep->hwp + FEC_MIIGSK_ENR);
- while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
+ fec_writel(0, fep->hwp + FEC_MIIGSK_ENR);
+ while (fec_readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
udelay(1);
/*
* configure the gasket:
* RMII, 50 MHz, no loopback, no echo
*/
- writel(1, fep->hwp + FEC_MIIGSK_CFGR);
+ fec_writel(1, fep->hwp + FEC_MIIGSK_CFGR);
/* re-enable the gasket */
- writel(2, fep->hwp + FEC_MIIGSK_ENR);
+ fec_writel(2, fep->hwp + FEC_MIIGSK_ENR);
}
#endif
}
@@ -1433,22 +1439,22 @@ fec_restart(struct net_device *dev, int
ret = fec_ptp_start(fep->ptp_priv);
if (ret) {
fep->ptimer_present = 0;
- writel(2, fep->hwp + FEC_ECNTRL);
+ fec_writel(2, fep->hwp + FEC_ECNTRL);
} else {
- val = readl(fep->hwp + FEC_ECNTRL);
+ val = fec_readl(fep->hwp + FEC_ECNTRL);
val |= 0x00000012;
- writel(val, fep->hwp + FEC_ECNTRL);
+ fec_writel(val, fep->hwp + FEC_ECNTRL);
}
} else
- writel(2, fep->hwp + FEC_ECNTRL);
+ fec_writel(2, fep->hwp + FEC_ECNTRL);
#else
/* And last, enable the transmit and receive processing */
- writel(2, fep->hwp + FEC_ECNTRL);
+ fec_writel(2, fep->hwp + FEC_ECNTRL);
#endif
- writel(0, fep->hwp + FEC_R_DES_ACTIVE);
+ fec_writel(0, fep->hwp + FEC_R_DES_ACTIVE);
/* Enable interrupts we wish to service */
- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+ fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
}
static void
@@ -1458,21 +1464,22 @@ fec_stop(struct net_device *dev)
/* We cannot expect a graceful transmit stop without link !!! */
if (fep->link) {
- writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
+ /* Graceful transmit stop */
+ fec_writel(1, fep->hwp + FEC_X_CNTRL);
udelay(10);
- if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
+ if (!(fec_readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
printk("fec_stop : Graceful transmit stop did not complete !\n");
}
/* Whack a reset. We should wait for this. */
- writel(1, fep->hwp + FEC_ECNTRL);
+ fec_writel(1, fep->hwp + FEC_ECNTRL);
udelay(10);
- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+ fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
#ifdef CONFIG_FEC_1588
if (fep->ptimer_present)
fec_ptp_stop(fep->ptp_priv);
#endif
- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+ fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
}
static int __devinit

2093
target/linux/coldfire/patches/024-Add-SEC-1.1-support-for-MCF547x-and-MCF548x.patch Normal file
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1216
target/linux/coldfire/patches/025-Add-I2C-driver-for-MCF5445x-MCF547x-MCF548x.patch Normal file
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627
target/linux/coldfire/patches/026-Add-RTC-driver-support-for-MCF5445x.patch Normal file
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@ -0,0 +1,627 @@
From 40563ab5aa698191dbd8a05fe6053aa790eee2a1 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:46 +0800
Subject: [PATCH 26/52] Add RTC driver support for MCF5445x
On-chip RTC module support for MCF54451 and MCF54455.
Using internal 32K clock to drive the rtc module.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/rtc/Kconfig | 9 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mcf.c | 583 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 593 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-mcf.c
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -919,6 +919,15 @@ config RTC_DRV_MV
This driver can also be built as a module. If so, the module
will be called rtc-mv.
+config RTC_MCF
+ tristate "Freescale Coldfire Real Time Clock"
+ depends on COLDFIRE
+ help
+ If you say yes here you will get support for the on-chip Coldfire
+ Real-Time Clock.
+
+ If you build it as a module it will be call mcf-rtc.
+
config RTC_DRV_PS3
tristate "PS3 RTC"
depends on PPC_PS3
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -102,3 +102,4 @@ obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41
obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o
obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o
obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
+obj-$(CONFIG_RTC_MCF) += rtc-mcf.o
--- /dev/null
+++ b/drivers/rtc/rtc-mcf.c
@@ -0,0 +1,583 @@
+/*
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Implementation based on rtc-mxc.c
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <asm/mcfsim.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#ifdef readl
+#undef readl
+#endif
+
+#ifdef writel
+#undef writel
+#endif
+
+#define readl(addr) in_be32(addr)
+#define writel(val, addr) out_be32((addr), (val))
+
+#define RTC_INPUT_CLK_32768HZ 0x8000
+#define RTC_INPUT_CLK_32000HZ 0x7D00
+#define RTC_INPUT_CLK_38400HZ 0x9600
+#define RTC_INPUT_CLK_48000HZ 0xBB80
+
+#define PIT_ALL_ON (MCF_RTC_ISR_2HZ | MCF_RTC_ISR_SAM0 | MCF_RTC_ISR_SAM1 | \
+ MCF_RTC_ISR_SAM2 | MCF_RTC_ISR_SAM3 | MCF_RTC_ISR_SAM4 | \
+ MCF_RTC_ISR_SAM5 | MCF_RTC_ISR_SAM6 | MCF_RTC_ISR_SAM7)
+
+#define MAX_PIE_NUM 9
+#define MAX_PIE_FREQ 512
+const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
+ {2, MCF_RTC_ISR_2HZ},
+ {4, MCF_RTC_ISR_SAM0},
+ {8, MCF_RTC_ISR_SAM1},
+ {16, MCF_RTC_ISR_SAM2},
+ {32, MCF_RTC_ISR_SAM3},
+ {64, MCF_RTC_ISR_SAM4},
+ {128, MCF_RTC_ISR_SAM5},
+ {256, MCF_RTC_ISR_SAM6},
+ {MAX_PIE_FREQ, MCF_RTC_ISR_SAM7},
+};
+
+/* Those are the bits from a classic RTC we want to mimic */
+#define RTC_IRQF 0x80 /* any of the following 3 is active */
+#define RTC_PF 0x40 /* Periodic interrupt */
+#define RTC_AF 0x20 /* Alarm interrupt */
+#define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */
+
+#define MCF_RTC_TIME 0
+#define MCF_RTC_ALARM 1
+
+struct rtc_plat_data {
+ struct rtc_device *rtc;
+ int irq;
+ unsigned int irqen;
+ int alrm_sec;
+ int alrm_min;
+ int alrm_hour;
+ int alrm_mday;
+};
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-mcf.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+#define RTC_VERSION "0.1"
+
+static u32 rtc_freq = 2; /* minimun value for PIE */
+static unsigned long rtc_status;
+
+static struct rtc_time g_rtc_alarm = {
+ .tm_year = 0,
+ .tm_mon = 0,
+ .tm_mday = 0,
+ .tm_hour = 0,
+ .tm_mon = 0,
+ .tm_sec = 0,
+};
+
+static DEFINE_SPINLOCK(rtc_lock);
+
+/*!
+ * This function is used to obtain the RTC time or the alarm value in
+ * second.
+ *
+ * @param time_alarm use MCF_RTC_TIME for RTC time value;
+ * MCF_RTC_ALARM for alarm value
+ *
+ * @return The RTC time or alarm time in second.
+ */
+static u32 get_alarm_or_time(struct device *dev, int time_alarm)
+{
+ u32 day, hr, min, sec, hr_min;
+
+ if (time_alarm == MCF_RTC_TIME) {
+ day = MCF_RTC_DAYS_DAYS(readl(MCF_RTC_DAYS));
+ hr_min = readl(MCF_RTC_HOURMIN);
+ sec = MCF_RTC_SECONDS_SECONDS(readl(MCF_RTC_SECONDS));
+ } else if (time_alarm == MCF_RTC_ALARM) {
+ day = MCF_RTC_ALRM_DAY_DAYS(readl(MCF_RTC_ALRM_DAY));
+ hr_min = readl(MCF_RTC_ALRM_HM);
+ sec = MCF_RTC_ALRM_SEC_SECONDS(readl(MCF_RTC_ALRM_SEC));
+ } else {
+ panic("wrong value for time_alarm=%d\n", time_alarm);
+ }
+
+ hr = (hr_min >> 8) & 0x001F;
+ min = hr_min & 0x003F;
+
+ return (((day * 24 + hr) * 60) + min) * 60 + sec;
+}
+
+/*!
+ * This function sets the RTC alarm value or the time value.
+ *
+ * @param time_alarm the new alarm value to be updated in the RTC
+ * @param time use MCF_RTC_TIME for RTC time value;
+ * MCF_RTC_ALARM for alarm value
+ */
+static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time)
+{
+ u32 day, hr, min, sec, temp;
+
+ day = time / 86400;
+ time -= day * 86400;
+ /* time is within a day now */
+ hr = time / 3600;
+ time -= hr * 3600;
+ /* time is within an hour now */
+ min = time / 60;
+ sec = time - min * 60;
+
+ temp = (hr << 8) + min;
+
+ if (time_alarm == MCF_RTC_TIME) {
+ writel(day, MCF_RTC_DAYS);
+ writel(sec, MCF_RTC_SECONDS);
+ writel(temp, MCF_RTC_HOURMIN);
+ } else if (time_alarm == MCF_RTC_ALARM) {
+ writel(day, MCF_RTC_ALRM_DAY);
+ writel(sec, MCF_RTC_ALRM_SEC);
+ writel(temp, MCF_RTC_ALRM_HM);
+ } else {
+ panic("wrong value for time_alarm=%d\n", time_alarm);
+ }
+}
+
+/*!
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ *
+ * @param alrm the new alarm value to be updated in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+{
+ struct rtc_time alarm_tm, now_tm;
+ unsigned long now, time;
+ int ret;
+
+ now = get_alarm_or_time(dev, MCF_RTC_TIME);
+ rtc_time_to_tm(now, &now_tm);
+ alarm_tm.tm_year = now_tm.tm_year;
+ alarm_tm.tm_mon = now_tm.tm_mon;
+ alarm_tm.tm_mday = now_tm.tm_mday;
+ alarm_tm.tm_hour = alrm->tm_hour;
+ alarm_tm.tm_min = alrm->tm_min;
+ alarm_tm.tm_sec = alrm->tm_sec;
+ rtc_tm_to_time(&now_tm, &now);
+ rtc_tm_to_time(&alarm_tm, &time);
+ if (time < now) {
+ time += 60 * 60 * 24;
+ rtc_time_to_tm(time, &alarm_tm);
+ }
+ ret = rtc_tm_to_time(&alarm_tm, &time);
+
+ /* clear all the interrupt status bits */
+ writel(readl(MCF_RTC_ISR), MCF_RTC_ISR);
+
+ set_alarm_or_time(dev, MCF_RTC_ALARM, time);
+
+ return ret;
+}
+
+/*!
+ * This function is the RTC interrupt service routine.
+ *
+ * @param irq RTC IRQ number
+ * @param dev_id device ID which is not used
+ *
+ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
+ */
+static irqreturn_t mcf_rtc_interrupt(int irq, void *dev_id)
+{
+ struct platform_device *pdev = dev_id;
+ struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+ u32 status, events = 0;
+
+ spin_lock(&rtc_lock);
+
+ /* clear interrupt sources */
+ status = readl(MCF_RTC_ISR) & readl(MCF_RTC_IER);
+ writel(status, MCF_RTC_ISR);
+
+ /* clear alarm interrupt if it has occurred */
+ if (status & MCF_RTC_ISR_ALM)
+ status &= ~MCF_RTC_ISR_ALM;
+
+ /* update irq data & counter */
+ if (status & MCF_RTC_ISR_ALM)
+ events |= (RTC_AF | RTC_IRQF);
+ if (status & MCF_RTC_ISR_1HZ)
+ events |= (RTC_UF | RTC_IRQF);
+ if (status & PIT_ALL_ON)
+ events |= (RTC_PF | RTC_IRQF);
+
+ if ((status & MCF_RTC_ISR_ALM) && rtc_valid_tm(&g_rtc_alarm))
+ rtc_update_alarm(&pdev->dev, &g_rtc_alarm);
+
+ spin_unlock(&rtc_lock);
+ rtc_update_irq(pdata->rtc, 1, events);
+ return IRQ_HANDLED;
+}
+
+/*!
+ * clear all interrupts and release the IRQ
+ */
+static void mcf_rtc_release(struct device *dev)
+{
+ spin_lock_irq(&rtc_lock);
+ writel(0, MCF_RTC_IER); /* Disable all rtc interrupts */
+ writel(0x0000FFBF, MCF_RTC_ISR); /* Clear all interrupt status */
+ spin_unlock_irq(&rtc_lock);
+ rtc_status = 0;
+}
+
+/*!
+ * This function is used to support some ioctl calls directly.
+ * Other ioctl calls are supported indirectly through the
+ * arm/common/rtctime.c file.
+ *
+ * @param cmd ioctl command as defined in include/linux/rtc.h
+ * @param arg value for the ioctl command
+ *
+ * @return 0 if successful or negative value otherwise.
+ */
+static int mcf_rtc_ioctl(struct device *dev, unsigned int cmd,
+ unsigned long arg)
+{
+ int i;
+
+ switch (cmd) {
+ case RTC_PIE_OFF:
+ writel((readl(MCF_RTC_IER) & ~PIT_ALL_ON), MCF_RTC_IER);
+ return 0;
+ case RTC_IRQP_SET:
+ if (arg < 2 || arg > MAX_PIE_FREQ || (arg % 2) != 0)
+ return -EINVAL; /* Also make sure a power of 2Hz */
+ if ((arg > 64) && (!capable(CAP_SYS_RESOURCE)))
+ return -EACCES;
+ rtc_freq = arg;
+ return 0;
+ case RTC_IRQP_READ:
+ return put_user(rtc_freq, (u32 *) arg);
+ case RTC_PIE_ON:
+ for (i = 0; i < MAX_PIE_NUM; i++) {
+ if (PIE_BIT_DEF[i][0] == rtc_freq)
+ break;
+ }
+ if (i == MAX_PIE_NUM)
+ return -EACCES;
+ spin_lock_irq(&rtc_lock);
+ writel((readl(MCF_RTC_IER) | PIE_BIT_DEF[i][1]), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+ case RTC_AIE_OFF:
+ spin_lock_irq(&rtc_lock);
+ writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+
+ case RTC_AIE_ON:
+ spin_lock_irq(&rtc_lock);
+ writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+
+ case RTC_UIE_OFF: /* UIE is for the 1Hz interrupt */
+ spin_lock_irq(&rtc_lock);
+ writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_1HZ), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+
+ case RTC_UIE_ON:
+ spin_lock_irq(&rtc_lock);
+ writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_1HZ), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+ }
+ return -ENOIOCTLCMD;
+}
+
+/*!
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param tm contains the RTC time value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ u32 val;
+
+ /* Avoid roll-over from reading the different registers */
+ do {
+ val = get_alarm_or_time(dev, MCF_RTC_TIME);
+ } while (val != get_alarm_or_time(dev, MCF_RTC_TIME));
+
+ rtc_time_to_tm(val, tm);
+ return 0;
+}
+
+/*!
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param tm the time value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ unsigned long time;
+ int ret;
+
+ ret = rtc_tm_to_time(tm, &time);
+ if (ret != 0)
+ return ret;
+
+ /* Avoid roll-over from reading the different registers */
+ do {
+ set_alarm_or_time(dev, MCF_RTC_TIME, time);
+ } while (time != get_alarm_or_time(dev, MCF_RTC_TIME));
+
+ return ret;
+}
+
+/*!
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param alrm contains the RTC alarm value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ rtc_time_to_tm(get_alarm_or_time(dev, MCF_RTC_ALARM), &alrm->time);
+ alrm->pending = ((readl(MCF_RTC_ISR) & MCF_RTC_ISR_ALM) != 0) ? 1 : 0;
+
+ return 0;
+}
+
+/*!
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param alrm the alarm value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ int ret;
+
+ spin_lock_irq(&rtc_lock);
+ if (rtc_valid_tm(&alrm->time)) {
+ if (alrm->time.tm_sec > 59 ||
+ alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) {
+ ret = -EINVAL;
+ goto out;
+ }
+ ret = rtc_update_alarm(dev, &alrm->time);
+ } else {
+ ret = rtc_valid_tm(&alrm->time);
+ if (ret)
+ goto out;
+ ret = rtc_update_alarm(dev, &alrm->time);
+ }
+
+ if (ret == 0) {
+ memcpy(&g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
+
+ if (alrm->enabled) {
+ writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_ALM),
+ MCF_RTC_IER);
+ } else {
+ writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM),
+ MCF_RTC_IER);
+ }
+ }
+out:
+ spin_unlock_irq(&rtc_lock);
+
+ return ret;
+}
+
+/*!
+ * This function is used to provide the content for the /proc/driver/rtc
+ * file.
+ *
+ * @param buf the buffer to hold the information that the driver
+ * wants to write
+ *
+ * @return The number of bytes written into the rtc file.
+ */
+static int mcf_rtc_proc(struct device *dev, struct seq_file *sq)
+{
+ char *p = sq->buf;
+
+ p += sprintf(p, "alarm_IRQ\t: %s\n",
+ (((readl(MCF_RTC_IER)) & MCF_RTC_ISR_ALM) !=
+ 0) ? "yes" : "no");
+ p += sprintf(p, "update_IRQ\t: %s\n",
+ (((readl(MCF_RTC_IER)) & MCF_RTC_ISR_1HZ) !=
+ 0) ? "yes" : "no");
+ p += sprintf(p, "periodic_IRQ\t: %s\n",
+ (((readl(MCF_RTC_IER)) & PIT_ALL_ON) !=
+ 0) ? "yes" : "no");
+ p += sprintf(p, "periodic_freq\t: %d\n", rtc_freq);
+
+ return p - (sq->buf);
+}
+
+/*!
+ * The RTC driver structure
+ */
+static struct rtc_class_ops mcf_rtc_ops = {
+ .ioctl = mcf_rtc_ioctl,
+ .read_time = mcf_rtc_read_time,
+ .set_time = mcf_rtc_set_time,
+ .read_alarm = mcf_rtc_read_alarm,
+ .set_alarm = mcf_rtc_set_alarm,
+ .proc = mcf_rtc_proc,
+};
+
+static int __devinit mcf_rtc_probe(struct platform_device *pdev)
+{
+ struct timespec tv;
+ struct rtc_device *rtc;
+ struct rtc_plat_data *pdata = NULL;
+ u32 ret = 0;
+
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+ /* External clock is hard wired to 32768Hz.
+ * Clock settings 32K, 38.4K and 48K are defined above. */
+#if defined(CONFIG_M5227x) | defined(CONFIG_M5445X)
+ writel(0, MCF_RTC_GOCU);
+ writel(RTC_INPUT_CLK_32768HZ, MCF_RTC_GOCL);
+#endif
+ /* Configure and enable the RTC */
+ pdata->irq = MCFINT_VECBASE + MCFINT_RTC;
+ if (request_irq(pdata->irq, mcf_rtc_interrupt, IRQF_DISABLED,
+ pdev->name, pdev) < 0) {
+ dev_warn(&pdev->dev, "interrupt not available.\n");
+ pdata->irq = -1;
+ }
+
+ if (test_and_set_bit(1, &rtc_status))
+ return -EBUSY;
+
+ rtc = rtc_device_register(pdev->name, &pdev->dev, &mcf_rtc_ops,
+ THIS_MODULE);
+ if (IS_ERR(rtc)) {
+ ret = PTR_ERR(rtc);
+ if (pdata->irq >= 0)
+ free_irq(pdata->irq, pdev);
+ kfree(pdata);
+ return ret;
+ }
+ pdata->rtc = rtc;
+ platform_set_drvdata(pdev, pdata);
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = get_alarm_or_time(&pdev->dev, MCF_RTC_TIME);
+
+#ifdef CONFIG_M5301x
+ writel(RTC_INPUT_CLK_32768HZ, MCF_RTC_GOC);
+ writel(0x08, MCF_RTC_OCEN);
+#endif
+ writeb(4, MCFSIM_ICR_RTC);
+
+ writel(MCF_RTC_IER_1HZ, MCF_RTC_IER); /* Unmask the 1Hz timer */
+
+ writel(MCF_RTC_CR_EN, MCF_RTC_CR);
+ if ((readl(MCF_RTC_CR) & MCF_RTC_CR_EN) == 0) {
+ printk(KERN_ALERT "RTC Hardware couldn't be enabled!\n");
+ return -EPERM;
+ }
+
+ printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION);
+ return ret;
+}
+
+static int __devexit mcf_rtc_remove(struct platform_device *pdev)
+{
+ struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+
+ rtc_device_unregister(pdata->rtc);
+ if (pdata->irq >= 0)
+ free_irq(pdata->irq, pdev);
+ kfree(pdata);
+ mcf_rtc_release(NULL);
+ return 0;
+}
+
+/*!
+ * Contains pointers to the power management callback functions.
+ */
+MODULE_ALIAS("mcf-rtc");
+static struct platform_driver mcf_rtc_driver = {
+ .driver = {
+ .name = "mcf-rtc",
+ .owner = THIS_MODULE,
+ },
+ .probe = mcf_rtc_probe,
+ .remove = __devexit_p(mcf_rtc_remove),
+};
+
+/*!
+ * This function creates the /proc/driver/rtc file and registers the device RTC
+ * in the /dev/misc directory. It also reads the RTC value from external source
+ * and setup the internal RTC properly.
+ *
+ * @return -1 if RTC is failed to initialize; 0 is successful.
+ */
+static int __init mcf_rtc_init(void)
+{
+ return platform_driver_register(&mcf_rtc_driver);
+}
+
+/*!
+ * This function removes the /proc/driver/rtc file and un-registers the
+ * device RTC from the /dev/misc directory.
+ */
+static void __exit mcf_rtc_exit(void)
+{
+ platform_driver_unregister(&mcf_rtc_driver);
+
+}
+
+module_init(mcf_rtc_init);
+module_exit(mcf_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Real Time Clock Driver (MCF)");
+MODULE_LICENSE("GPL");

681
target/linux/coldfire/patches/027-Add-RTC-driver-support-on-MCF5441x-platform.patch Normal file
View File

@ -0,0 +1,681 @@
From 6462d09dad154b69ea6180c0acb2d009627ff1be Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:46 +0800
Subject: [PATCH 27/52] Add RTC driver support on MCF5441x platform
Support on-chip robust-RTC module on MCF5441x platform.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/rtc/Kconfig | 9 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-m5441x.c | 638 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 648 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-m5441x.c
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -928,6 +928,15 @@ config RTC_MCF
If you build it as a module it will be call mcf-rtc.
+config RTC_M5441X
+ tristate "Freescale Coldfire M5441X platform Real Time Clock"
+ depends on COLDFIRE
+ help
+ If you say yes here you will get support for the on-chip Coldfire
+ Real-Time Clock for mcf5441x platform.
+
+ If you build it as a module it will be call rtc-m5441x.
+
config RTC_DRV_PS3
tristate "PS3 RTC"
depends on PPC_PS3
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -103,3 +103,4 @@ obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm83
obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o
obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
obj-$(CONFIG_RTC_MCF) += rtc-mcf.o
+obj-$(CONFIG_RTC_M5441X) += rtc-m5441x.o
--- /dev/null
+++ b/drivers/rtc/rtc-m5441x.c
@@ -0,0 +1,638 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Lanttor.Guo@freescale.com
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Implementation based on rtc-mcf.c
+ */
+
+/*
+ * RTC Real Time Clock (RTC) Driver
+ *
+ * @file rtc-m5441x.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ */
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <asm/mcfsim.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#ifdef readw
+#undef readw
+#endif
+
+#ifdef writew
+#undef writew
+#endif
+
+#define readw(addr) in_be16(addr)
+#define writew(val, addr) out_be16((addr), (val))
+
+
+#define PIT_ALL_ON (MCF_RTC_ISR_2HZ | MCF_RTC_ISR_SAM0 | MCF_RTC_ISR_SAM1 | \
+ MCF_RTC_ISR_SAM2 | MCF_RTC_ISR_SAM3 | MCF_RTC_ISR_SAM4 | \
+ MCF_RTC_ISR_SAM5 | MCF_RTC_ISR_SAM6 | MCF_RTC_ISR_SAM7)
+
+#define MAX_PIE_NUM 9
+#define MAX_PIE_FREQ 512
+const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
+ {2, MCF_RTC_ISR_2HZ},
+ {4, MCF_RTC_ISR_SAM0},
+ {8, MCF_RTC_ISR_SAM1},
+ {16, MCF_RTC_ISR_SAM2},
+ {32, MCF_RTC_ISR_SAM3},
+ {64, MCF_RTC_ISR_SAM4},
+ {128, MCF_RTC_ISR_SAM5},
+ {256, MCF_RTC_ISR_SAM6},
+ {MAX_PIE_FREQ, MCF_RTC_ISR_SAM7},
+};
+
+/* Those are the bits from a classic RTC we want to mimic */
+#define RTC_IRQF 0x80 /* any of the following 3 is active */
+#define RTC_PF 0x40 /* Periodic interrupt */
+#define RTC_AF 0x20 /* Alarm interrupt */
+#define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */
+
+#define MCF_RTC_TIME 0
+#define MCF_RTC_ALARM 1
+
+struct rtc_plat_data {
+ struct rtc_device *rtc;
+ int irq;
+ unsigned int irqen;
+ int alrm_sec;
+ int alrm_min;
+ int alrm_hour;
+ int alrm_mday;
+};
+
+static const int year_cal_basic = 2112;
+
+#define RTC_VERSION "0.1"
+
+static u32 rtc_freq = 2; /* minimun value for PIE */
+static unsigned long rtc_status;
+
+static struct rtc_time g_rtc_alarm = {
+ .tm_year = 0,
+ .tm_mon = 0,
+ .tm_mday = 0,
+ .tm_hour = 0,
+ .tm_mon = 0,
+ .tm_sec = 0,
+};
+
+static DEFINE_SPINLOCK(rtc_lock);
+
+
+/*
+ * This funciton is used to disable RTC register write protection
+ */
+static void disable_register_write_protection(void)
+{
+ if (readw(MCF_RTC_SR) & MCF_RTC_SR_WPE) {
+ writew(0x0000, MCF_RTC_CR);
+ writew(0x0001, MCF_RTC_CR);
+ writew(0x0003, MCF_RTC_CR);
+ writew(0x0002, MCF_RTC_CR);
+ }
+
+}
+
+/*
+ * This function is used to obtain the RTC time or the alarm value in
+ * second.
+ *
+ * @param time_alarm use MCF_RTC_TIME for RTC time value;
+ * MCF_RTC_ALARM for alarm value
+ *
+ * @return The RTC time or alarm time in second.
+ */
+static u32 get_alarm_or_time(struct device *dev, int time_alarm,
+ struct rtc_time *tm)
+{
+ dev_dbg(dev, "debug function %s()!\n", __func__);
+
+ if (time_alarm == MCF_RTC_TIME) {
+ /*check register information */
+ dev_dbg(dev, "RTC_YEARMON:0x%x,RTC_DAYS:0x%x,RTC_HOURMIN:0x%x,"
+ "RTC_SECONDS:0x%x\n", readw(MCF_RTC_YEARMON),
+ readw(MCF_RTC_DAYS), readw(MCF_RTC_HOURMIN),
+ readw(MCF_RTC_SECONDS));
+
+ /* get year */
+ tm->tm_year = year_cal_basic +
+ (char)(MCF_RTC_YEARMON_YEAR_RD(readw(MCF_RTC_YEARMON)));
+ /* get month */
+ tm->tm_mon =
+ MCF_RTC_YEARMON_MON_RD(readw(MCF_RTC_YEARMON)) - 1;
+ /* get month day */
+ tm->tm_mday = MCF_RTC_DAYS_DAY_RD(readw(MCF_RTC_DAYS));
+ /* get year day */
+ tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon,
+ tm->tm_year);
+ /* year minus 1900 */
+ tm->tm_year = tm->tm_year - 1900;
+ /* get week day */
+ tm->tm_wday = MCF_RTC_DAYS_DAYWEEK_RD(readw(MCF_RTC_DAYS));
+ /* get hours */
+ tm->tm_hour =
+ MCF_RTC_HOURMIN_HOURS_RD(readw(MCF_RTC_HOURMIN));
+ /* get minutes */
+ tm->tm_min =
+ MCF_RTC_HOURMIN_MINUTES_RD(readw(MCF_RTC_HOURMIN));
+ /* get seconds */
+ tm->tm_sec =
+ MCF_RTC_SECONDS_SECONDS_RD(readw(MCF_RTC_SECONDS));
+ /* no day saving time */
+ tm->tm_isdst = -1;
+
+ /* check rtc_tm fileds information */
+ dev_dbg(dev, "RTC TIME --> year:%d,yday:%d,mon:%d,mday:%d,"
+ "wday:%d,hour:%d,min:%d,sec:%d\n", tm->tm_year,
+ tm->tm_yday, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ } else if (time_alarm == MCF_RTC_ALARM) {
+ tm->tm_year = year_cal_basic +
+ (char)MCF_RTC_YEARMON_YEAR_RD
+ (readw(MCF_RTC_ALRM_YRMON));
+ tm->tm_mon =
+ MCF_RTC_YEARMON_MON_RD(readw(MCF_RTC_ALRM_YRMON)) - 1;
+ tm->tm_mday = MCF_RTC_DAYS_DAY_RD(readw(MCF_RTC_ALRM_DAYS));
+ tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon,
+ tm->tm_year);
+ tm->tm_year = tm->tm_year - 1900;
+ tm->tm_wday =
+ MCF_RTC_DAYS_DAYWEEK_RD(readw(MCF_RTC_ALRM_DAYS));
+ tm->tm_hour =
+ MCF_RTC_HOURMIN_HOURS_RD(readw(MCF_RTC_ALRM_HM));
+ tm->tm_min =
+ MCF_RTC_HOURMIN_MINUTES_RD(readw(MCF_RTC_ALRM_HM));
+ tm->tm_sec =
+ MCF_RTC_SECONDS_SECONDS_RD(readw(MCF_RTC_ALRM_SEC));
+ tm->tm_isdst = -1;
+
+ /* debug information */
+ dev_dbg(dev, "RTC ALARM --> year:%d,yday:%d,mon:%d,mday:%d,"
+ "wday:%d,hour:%d,min:%d,sec:%d\n", tm->tm_year,
+ tm->tm_yday, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ } else {
+ panic("wrong value for time_alarm=%d\n", time_alarm);
+ }
+
+ return 0;
+}
+
+/*
+ * This function sets the RTC alarm value or the time value.
+ *
+ * @param time_alarm the new alarm value to be updated in the RTC
+ * @param time use MCF_RTC_TIME for RTC time value;
+ * MCF_RTC_ALARM for alarm value
+ */
+static void set_alarm_or_time(struct device *dev, int time_alarm,
+ struct rtc_time *tm)
+{
+ char year;
+
+ dev_dbg(dev, "debug function %s()!\n", __func__);
+
+ /* wirte enable setting */
+ disable_register_write_protection();
+
+ if (time_alarm == MCF_RTC_TIME) {
+ /* check rtc_time fields information */
+ dev_dbg(dev, "RTC TIME --> year:%d,yday:%d,mon:%d,mday:%d,"
+ "wday:%d,hour:%d,min:%d,sec:%d\n", tm->tm_year,
+ tm->tm_yday, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ year = ((tm->tm_year + 1900) - year_cal_basic);
+ /* write RTC_YEARMON register */
+ writew((year << 8) | (tm->tm_mon + 1), MCF_RTC_YEARMON);
+
+ /* write RTC_DAYS register */
+ writew(MCF_RTC_DAYS_DAYWEEK_SET(tm->tm_wday) |
+ MCF_RTC_DAYS_DAY_SET(tm->tm_mday), MCF_RTC_DAYS);
+
+ /* write RTC_HOURMIN register */
+ writew(MCF_RTC_HOURMIN_HOURS_SET(tm->tm_hour) |
+ MCF_RTC_HOURMIN_MINUTES_SET(tm->tm_min),
+ MCF_RTC_HOURMIN);
+
+ /* write RTC_SECONDS register */
+ writew(MCF_RTC_SECONDS_SECONDS_SET
+ (tm->tm_sec), MCF_RTC_SECONDS);
+
+ /* debug information */
+ dev_dbg(dev, "RTC_YEARMON:0x%x, RTC_DAYS:0x%x, "
+ "RTC_HOURMIN:0x%x, RTC_SECONDS:0x%x\n",
+ readw(MCF_RTC_YEARMON), readw(MCF_RTC_DAYS),
+ readw(MCF_RTC_HOURMIN), readw(MCF_RTC_SECONDS));
+ } else if (time_alarm == MCF_RTC_ALARM) {
+
+ year = ((tm->tm_year + 1900) - year_cal_basic);
+ /* write RTC_YEARMON register */
+ writew((year << 8) | (tm->tm_mon + 1), MCF_RTC_ALRM_YRMON);
+
+ /* write RTC_DAYS register */
+ writew(MCF_RTC_DAYS_DAYWEEK_SET(tm->tm_wday) |
+ MCF_RTC_DAYS_DAY_SET(tm->tm_mday), MCF_RTC_ALRM_DAYS);
+
+ /* write RTC_HOURMIN register */
+ writew(MCF_RTC_HOURMIN_HOURS_SET(tm->tm_hour) |
+ MCF_RTC_HOURMIN_MINUTES_SET(tm->tm_min),
+ MCF_RTC_ALRM_HM);
+
+ /* write RTC_SECONDS register */
+ writew(MCF_RTC_SECONDS_SECONDS_SET
+ (tm->tm_sec), MCF_RTC_ALRM_SEC);
+
+ /* debug information */
+ dev_dbg(dev, "ALRM_YRMON:0x%x,ALRM_DAYS:0x%x,ALRM_HM:0x%x,"
+ "ALRM_SEC:0x%x\n", readw(MCF_RTC_ALRM_YRMON),
+ readw(MCF_RTC_ALRM_DAYS), readw(MCF_RTC_ALRM_HM),
+ readw(MCF_RTC_ALRM_SEC));
+ } else {
+ panic("wrong value for time_alarm=%d\n", time_alarm);
+ }
+}
+
+/*!
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ *
+ * @param alrm the new alarm value to be updated in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+{
+ /* clear all the interrupt status bits */
+ disable_register_write_protection();
+
+ writew(readw(MCF_RTC_ISR), MCF_RTC_ISR);
+
+ set_alarm_or_time(dev, MCF_RTC_ALARM, alrm);
+
+ return 0;
+}
+
+/*!
+ * This function is the RTC interrupt service routine.
+ *
+ * @param irq RTC IRQ number
+ * @param dev_id device ID which is not used
+ *
+ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
+ */
+static irqreturn_t mcf_rtc_interrupt(int irq, void *dev_id)
+{
+ struct platform_device *pdev = dev_id;
+ struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+ u16 status = 0;
+ u32 events = 0;
+
+ spin_lock(&rtc_lock);
+
+ /* clear interrupt sources */
+ status = readw(MCF_RTC_ISR) & readw(MCF_RTC_IER);
+
+ disable_register_write_protection();
+
+ writew(status, MCF_RTC_ISR);
+
+ /* clear alarm interrupt if it has occurred */
+ if (status & MCF_RTC_ISR_ALM)
+ status &= ~MCF_RTC_ISR_ALM;
+
+ /* update irq data & counter */
+ if (status & MCF_RTC_ISR_ALM)
+ events |= (RTC_AF | RTC_IRQF);
+ if (status & MCF_RTC_ISR_1HZ)
+ events |= (RTC_UF | RTC_IRQF);
+ if (status & PIT_ALL_ON)
+ events |= (RTC_PF | RTC_IRQF);
+
+ if ((status & MCF_RTC_ISR_ALM) && rtc_valid_tm(&g_rtc_alarm))
+ rtc_update_alarm(&pdev->dev, &g_rtc_alarm);
+
+ spin_unlock(&rtc_lock);
+ rtc_update_irq(pdata->rtc, 1, events);
+ return IRQ_HANDLED;
+}
+
+/*!
+ * clear all interrupts and release the IRQ
+ */
+static void mcf_rtc_release(struct device *dev)
+{
+ spin_lock_irq(&rtc_lock);
+
+ disable_register_write_protection();
+
+ writew(0, MCF_RTC_IER); /* Disable all rtc interrupts */
+ writew(readw(MCF_RTC_ISR), MCF_RTC_ISR);
+ spin_unlock_irq(&rtc_lock);
+ rtc_status = 0;
+}
+
+/*!
+ * This function is used to support some ioctl calls directly.
+ * Other ioctl calls are supported indirectly through the
+ * arm/common/rtctime.c file.
+ *
+ * @param cmd ioctl command as defined in include/linux/rtc.h
+ * @param arg value for the ioctl command
+ *
+ * @return 0 if successful or negative value otherwise.
+ */
+static int mcf_rtc_ioctl(struct device *dev, unsigned int cmd,
+ unsigned long arg)
+{
+ int i;
+
+ disable_register_write_protection();
+
+ switch (cmd) {
+ case RTC_PIE_OFF:
+ writew((readw(MCF_RTC_IER) & ~PIT_ALL_ON), MCF_RTC_IER);
+ return 0;
+ case RTC_IRQP_SET:
+ if (arg < 2 || arg > MAX_PIE_FREQ || (arg % 2) != 0)
+ return -EINVAL; /* Also make sure a power of 2Hz */
+ if ((arg > 64) && (!capable(CAP_SYS_RESOURCE)))
+ return -EACCES;
+ rtc_freq = arg;
+ return 0;
+ case RTC_IRQP_READ:
+ return put_user(rtc_freq, (u32 *) arg);
+ case RTC_PIE_ON:
+ for (i = 0; i < MAX_PIE_NUM; i++) {
+ if (PIE_BIT_DEF[i][0] == rtc_freq)
+ break;
+ }
+ if (i == MAX_PIE_NUM)
+ return -EACCES;
+ spin_lock_irq(&rtc_lock);
+ writew((readw(MCF_RTC_IER) | PIE_BIT_DEF[i][1]), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+ case RTC_AIE_OFF:
+ spin_lock_irq(&rtc_lock);
+ writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+
+ case RTC_AIE_ON:
+ spin_lock_irq(&rtc_lock);
+ writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+
+ case RTC_UIE_OFF: /* UIE is for the 1Hz interrupt */
+ spin_lock_irq(&rtc_lock);
+ writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_1HZ), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+
+ case RTC_UIE_ON:
+ spin_lock_irq(&rtc_lock);
+ writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_1HZ), MCF_RTC_IER);
+ spin_unlock_irq(&rtc_lock);
+ return 0;
+ }
+ return -ENOIOCTLCMD;
+}
+
+/*!
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param tm contains the RTC time value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ do {
+ get_alarm_or_time(dev, MCF_RTC_TIME, tm);
+ } while (0);
+
+ return 0;
+}
+
+/*!
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param tm the time value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ do {
+ set_alarm_or_time(dev, MCF_RTC_TIME, tm);
+ } while (0);
+
+ return 0;
+}
+
+/*!
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param alrm contains the RTC alarm value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ do {
+ get_alarm_or_time(dev, MCF_RTC_ALARM, &alrm->time);
+ } while (0);
+
+ alrm->pending = ((readw(MCF_RTC_ISR) & MCF_RTC_ISR_ALM) != 0) ? 1 : 0;
+
+ return 0;
+}
+
+/*!
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param alrm the alarm value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mcf_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ int ret;
+
+ spin_lock_irq(&rtc_lock);
+
+ disable_register_write_protection();
+
+ if (rtc_valid_tm(&alrm->time)) {
+ if (alrm->time.tm_sec > 59 ||
+ alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) {
+ ret = -EINVAL;
+ goto out;
+ }
+ ret = rtc_update_alarm(dev, &alrm->time);
+ } else {
+ ret = rtc_valid_tm(&alrm->time);
+ if (ret)
+ goto out;
+ ret = rtc_update_alarm(dev, &alrm->time);
+ }
+
+ if (ret == 0) {
+ memcpy(&g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
+
+ if (alrm->enabled) {
+ writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_ALM),
+ MCF_RTC_IER);
+ } else {
+ writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM),
+ MCF_RTC_IER);
+ }
+ }
+out:
+ spin_unlock_irq(&rtc_lock);
+
+ return ret;
+}
+
+/*!
+ * The RTC driver structure
+ */
+static struct rtc_class_ops mcf_rtc_ops = {
+ .ioctl = mcf_rtc_ioctl,
+ .read_time = mcf_rtc_read_time,
+ .set_time = mcf_rtc_set_time,
+ .read_alarm = mcf_rtc_read_alarm,
+ .set_alarm = mcf_rtc_set_alarm,
+};
+
+static int __devinit mcf_rtc_probe(struct platform_device *pdev)
+{
+ struct rtc_device *rtc;
+ struct rtc_plat_data *pdata = NULL;
+ u32 ret = 0;
+
+ disable_register_write_protection();
+ /* Clear interrupt before request irq */
+ writew(0x0100, MCF_RTC_CR);
+ writew(0x0001, MCF_RTC_IER);
+
+ if (!(readw(MCF_RTC_CFG_DATA) & MCF_RTC_CFG_DATA_OSCEN))
+ writew(MCF_RTC_CFG_DATA_OSCEN, MCF_RTC_CFG_DATA);
+
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ pdata->irq = MCFINT_VECBASE + MCFINT_RTC;
+ if (request_irq(pdata->irq, mcf_rtc_interrupt, IRQF_DISABLED,
+ pdev->name, pdev) < 0) {
+ dev_warn(&pdev->dev, "interrupt not available.\n");
+ pdata->irq = -1;
+ }
+
+ if (test_and_set_bit(1, &rtc_status))
+ return -EBUSY;
+
+ rtc = rtc_device_register(pdev->name, &pdev->dev, &mcf_rtc_ops,
+ THIS_MODULE);
+ if (IS_ERR(rtc)) {
+ ret = PTR_ERR(rtc);
+ if (pdata->irq >= 0)
+ free_irq(pdata->irq, pdev);
+ kfree(pdata);
+ return ret;
+ }
+ pdata->rtc = rtc;
+ platform_set_drvdata(pdev, pdata);
+
+ dev_dbg(&pdev->dev, "RTC_CR:0x%x, RTC_SR:0x%x\n", readw(MCF_RTC_CR),
+ readw(MCF_RTC_SR));
+
+ printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION);
+ return ret;
+}
+
+static int __devexit mcf_rtc_remove(struct platform_device *pdev)
+{
+ struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+
+ rtc_device_unregister(pdata->rtc);
+ if (pdata->irq >= 0)
+ free_irq(pdata->irq, pdev);
+ kfree(pdata);
+ mcf_rtc_release(NULL);
+ return 0;
+}
+
+/*!
+ * Contains pointers to the power management callback functions.
+ */
+MODULE_ALIAS("rtc-m5441x");
+static struct platform_driver mcf_rtc_driver = {
+ .driver = {
+ .name = "rtc-m5441x",
+ .owner = THIS_MODULE,
+ },
+ .probe = mcf_rtc_probe,
+ .remove = __devexit_p(mcf_rtc_remove),
+};
+
+/*!
+ * This function creates the /proc/driver/rtc file and registers the device RTC
+ * in the /dev/misc directory. It also reads the RTC value from external source
+ * and setup the internal RTC properly.
+ *
+ * @return -1 if RTC is failed to initialize; 0 is successful.
+ */
+static int __init mcf_rtc_init(void)
+{
+ return platform_driver_register(&mcf_rtc_driver);
+}
+
+/*!
+ * This function removes the /proc/driver/rtc file and un-registers the
+ * device RTC from the /dev/misc directory.
+ */
+static void __exit mcf_rtc_exit(void)
+{
+ platform_driver_unregister(&mcf_rtc_driver);
+
+}
+
+module_init(mcf_rtc_init);
+module_exit(mcf_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Real Time Clock Driver (MCF)");
+MODULE_LICENSE("GPL V2");

195
target/linux/coldfire/patches/028-Add-SD-MMC-SDIO-over-SPI-support-for-MCF54451-and-MC.patch Normal file
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@ -0,0 +1,195 @@
From d1b6aa1480c937e326bef99746299cd004a51f28 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:46 +0800
Subject: [PATCH 28/52] Add SD/MMC/SDIO over SPI support for MCF54451 and MCF54418
Add SD/MMC/SDIO over SPI support for MCF54451 and MCF54418.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/mmc/core/sdio.c | 9 +++++-
drivers/mmc/host/Kconfig | 35 +++++++++++++++++++++
drivers/mmc/host/mmc_spi.c | 73 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 116 insertions(+), 1 deletions(-)
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -566,8 +566,15 @@ static void mmc_sdio_detect(struct mmc_h
/*
* Just check if our card has been removed.
*/
+#if defined(M54451_SD_HW_DETECT)
+ {
+ unsigned char x;
+ err = mmc_io_rw_direct(host->card, 0, 0,
+ SDIO_FBR_BASE(0) + SDIO_FBR_CIS + 0, 0, &x);
+ }
+#else
err = mmc_select_card(host->card);
-
+#endif
mmc_release_host(host);
/*
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -368,6 +368,41 @@ config MMC_SPI
If unsure, or if your system has no SPI master driver, say N.
+config M54451_SD_HW_DETECT
+ tristate "use extern IRQ7 to detect SD/MMC card"
+ depends on MMC_SPI && M54451
+ default y
+ help
+ MMC/SD interface on 54551evb was over SPI. Enable this option will
+ use irq7 to dectect the card inserting/removing.
+
+config M5441X_SD_HW_DETECT
+ tristate "use extern IRQ to detect SD/MMC card"
+ depends on MMC_SPI && M5441X
+ help
+ MMC/SD interface on 54418evb was over SPI. Enable this option will
+ use irq7 or irq1 to dectect the card inserting/removing.
+
+choice
+ prompt "MMC/SD card detect "
+ depends on M5441X_SD_HW_DETECT
+
+config DETECT_USE_EXTERN_IRQ7
+ tristate "based extern IRQ7"
+ depends on M5441X_SD_HW_DETECT
+ help
+ MMC/SD cards using spi controller,
+ we use the extern irq7 to detect card.
+
+config DETECT_USE_EXTERN_IRQ1
+ tristate "based extern IRQ1"
+ depends on M5441X_SD_HW_DETECT
+ help
+ MMC/SD cards using spi controller,
+ we use the extern irq1 to detect card.
+
+endchoice
+
config MMC_S3C
tristate "Samsung S3C SD/MMC Card Interface support"
depends on ARCH_S3C2410
--- a/drivers/mmc/host/mmc_spi.c
+++ b/drivers/mmc/host/mmc_spi.c
@@ -9,6 +9,10 @@
* (C) Copyright 2007, ATRON electronic GmbH,
* Jan Nikitenko <jan.nikitenko@gmail.com>
*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Modified for M54451EVB/M54418TWR boards.
+ * Shrek Wu <b16972@freescale.com>
+ * Jingchang Lu <b22599@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,6 +36,14 @@
#include <linux/crc7.h>
#include <linux/crc-itu-t.h>
#include <linux/scatterlist.h>
+#if defined(CONFIG_M54451_SD_HW_DETECT)
+#include <asm/mcf5445x_eport.h>
+#include <asm/mcf5445x_intc.h>
+#include <asm/mcfsim.h>
+#elif defined(CONFIG_M5441X_SD_HW_DETECT)
+#include <asm/mcf5441x_eport.h>
+#include <asm/mcfsim.h>
+#endif
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */
@@ -268,6 +280,9 @@ static int mmc_spi_response_get(struct m
unsigned short rotator;
int i;
char tag[32];
+#if defined(CONFIG_M54451_SD_HW_DETECT) || defined(CONFIG_M5441X_SD_HW_DETECT)
+ u8 oldcp_value = 0;
+#endif
snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s",
cmd->opcode, maptype(cmd));
@@ -278,6 +293,9 @@ static int mmc_spi_response_get(struct m
* first byte. After STOP_TRANSMISSION command it may include
* two data bits, but otherwise it's all ones.
*/
+#if defined(CONFIG_M54451_SD_HW_DETECT) || defined(CONFIG_M5441X_SD_HW_DETECT)
+ oldcp_value = *cp;
+#endif
cp += 8;
while (cp < end && *cp == 0xff)
cp++;
@@ -310,6 +328,15 @@ static int mmc_spi_response_get(struct m
}
checkstatus:
+#if defined(CONFIG_M54451_SD_HW_DETECT) || defined(CONFIG_M5441X_SD_HW_DETECT)
+ if ((*cp == 0) && (oldcp_value == 0)) {
+ dev_dbg(&host->spi->dev, "NO CARD in the SD SOCKET, "
+ "new status %02x, old status %02x\n",
+ *cp, oldcp_value);
+ value = -EBADR;
+ goto done;
+ }
+#endif
bitshift = 0;
if (*cp & 0x80) {
/* Houston, we have an ugly card with a bit-shifted response */
@@ -1313,7 +1340,53 @@ mmc_spi_detect_irq(int irq, void *mmc)
struct mmc_spi_host *host = mmc_priv(mmc);
u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
+#if defined(CONFIG_M54451_SD_HW_DETECT)
+ dev_dbg(&host->spi->dev, "mmc_spi_detect_irq "
+ "MCF_EPORT_EPPAR %x, MCF_EPORT_EPIER %x,"
+ "MCF_INTC0_ICR7 %x, MCF_GPIO_PAR_IRQ %x,"
+ "MCF_EPORT_EPDDR %x, MCF_EPORT_EPFR %x\n",
+ MCF_EPORT_EPPAR, MCF_EPORT_EPIER,
+ MCF_INTC0_ICR7, MCF_GPIO_PAR_IRQ,
+ MCF_EPORT_EPDDR, MCF_EPORT_EPFR);
+
+ MCF_EPORT_EPIER &= (~MCF_EPORT_EPIER_EPIE7);
+#elif defined(CONFIG_M5441X_SD_HW_DETECT)
+#if defined(CONFIG_DETECT_USE_EXTERN_IRQ1)
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE1);
+#elif defined(CONFIG_DETECT_USE_EXTERN_IRQ7)
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7);
+#else
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7);
+#endif
+#endif
mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
+#if defined(CONFIG_M54451_SD_HW_DETECT)
+ MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA7_BOTH;
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
+ MCF_EPORT_EPFR |= MCF_EPORT_EPFR_EPF7;
+ dev_dbg(&host->spi->dev, "mmc_spi_detect_irq "
+ "MCF_EPORT_EPPAR %x, MCF_EPORT_EPIER %x,"
+ "MCF_INTC0_ICR7 %x, MCF_GPIO_PAR_IRQ %x,"
+ "MCF_EPORT_EPDDR %x, MCF_EPORT_EPFR %x\n",
+ MCF_EPORT_EPPAR, MCF_EPORT_EPIER,
+ MCF_INTC0_ICR7, MCF_GPIO_PAR_IRQ,
+ MCF_EPORT_EPDDR, MCF_EPORT_EPFR);
+
+#elif defined(CONFIG_M5441X_SD_HW_DETECT)
+#if defined(CONFIG_DETECT_USE_EXTERN_IRQ1)
+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH;
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1;
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF1;
+#elif defined(CONFIG_DETECT_USE_EXTERN_IRQ7)
+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7;
+#else
+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7;
+#endif
+#endif
return IRQ_HANDLED;
}

2214
target/linux/coldfire/patches/029-Add-eSDHC-driver-for-MCF5441x.patch Normal file
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File diff suppressed because it is too large Load Diff

38
target/linux/coldfire/patches/030-Add-SPI-device-configuration-for-FXS-and-FXO-on-MCF5.patch Normal file
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@ -0,0 +1,38 @@
From 2a73218ebe0bdca04cc9299da50d7f079ca46a7d Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:47 +0800
Subject: [PATCH 30/52] Add SPI device configuration for FXS and FXO on MCF54451 platform
Add SPI device configuration for FXS and FXO on MCF54451 platform.
So FXS and FXO drivers can use SPI subsystem interfaces for the SPI
read and write operations. So as to fix the confliction between FXO/FXS
with other SPI devices.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/spi/Kconfig | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -189,6 +189,20 @@ config SPI_COLDFIRE_DSPI_EDMA
help
Say "yes" if you want DSPI master driver to use eDMA for transfers.
+config VOIP_FXS
+ boolean "Coldfire VoIP FXS driver"
+ depends on M54451 && SPI_MASTER && SPI_DSPI
+ default n
+ help
+ Say "yes" if you want VoIP FXS driver to use DSPI for transfers.
+
+config VOIP_FXO
+ boolean "Coldfire VoIP FXO driver"
+ depends on M54451 && SPI_MASTER && SPI_DSPI
+ default n
+ help
+ Say "yes" if you want VoIP FXO driver to use DSPI for transfers.
+
config SPI_IMX_VER_IMX1
def_bool y if SOC_IMX1

338
target/linux/coldfire/patches/031-Add-watchdog-driver-support-for-MCF5445x-and-MCF547x.patch Normal file
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@ -0,0 +1,338 @@
From 42bf8a598049f6cb3c90b1f28a2f1b8daebe3de8 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:47 +0800
Subject: [PATCH 31/52] Add watchdog driver support for MCF5445x and MCF547x/MCF548x
Add watchdog driver support for MCF5445x and MCF547x/MCF548x.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/watchdog/Kconfig | 9 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/mcf_wdt.c | 292 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 302 insertions(+), 0 deletions(-)
create mode 100644 drivers/watchdog/mcf_wdt.c
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -974,6 +974,15 @@ config BCM63XX_WDT
# PARISC Architecture
+# ColdFire Architecture
+
+config COLDFIRE_WATCHDOG
+ tristate "ColdFire watchdog support"
+ depends on M547X_8X || M5445X || M5441X
+ help
+ To compile this driver as a module, choose M here: the
+ module will be called softdog.
+
# POWERPC Architecture
config GEF_WDT
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -107,6 +107,7 @@ obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc
# M68K Architecture
obj-$(CONFIG_M54xx_WATCHDOG) += m54xx_wdt.o
+obj-$(CONFIG_COLDFIRE_WATCHDOG) += mcf_wdt.o
# MIPS Architecture
obj-$(CONFIG_ATH79_WDT) += ath79_wdt.o
--- /dev/null
+++ b/drivers/watchdog/mcf_wdt.c
@@ -0,0 +1,292 @@
+/*
+ * drivers/watchdog/mcf_wdt.c
+ *
+ * Watchdog driver for ColdFire processors
+ *
+ * Copyright (C) 2006-2007, 2009-2011 Freescale Semiconductor, Inc.
+ * All Rights Reserved.
+ *
+ * Author: Shrek Wu<B16972@freesale.com>
+ * ChengJu Cai<B22600@freesale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+
+#include <linux/uaccess.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+static int nowayout;
+static unsigned int heartbeat = MCF_GPT_MAX_TIMEOUT;
+static unsigned long wdt_status;
+
+#define WDT_IN_USE 0
+#define WDT_OK_TO_CLOSE 1
+
+static unsigned long wdt_tick_rate;
+
+#ifdef CONFIG_M547X_8X
+static int
+wdt_enable(int time)
+{
+ if (time > 30 || time < 1)
+ return -EINVAL;
+
+ heartbeat = time;
+
+ MCF_GPT_GMS0 = 0;
+ MCF_GPT_GCIR0 = MCF_GPT_GCIR_PRE(heartbeat * wdt_tick_rate) |
+ MCF_GPT_GCIR_CNT(0xffff);
+ MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN |
+ MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS_GPIO;
+
+ return 0;
+}
+
+static void
+wdt_disable(void)
+{
+ MCF_GPT_GMS0 = 0;
+}
+
+static void
+wdt_keepalive(void)
+{
+ MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS0;
+}
+
+#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X)
+
+/* Enable watchdog and set time-out */
+static int
+wdt_enable(int time)
+{
+ unsigned int sign = 0x01 << 31;
+ int i = 0, timeout_n = 31;
+ int max_timeout = sign / MCF_BUSCLK;
+ unsigned int count;
+
+ if (time > max_timeout || time < 1)
+ return -EINVAL;
+
+ count = time * MCF_BUSCLK;
+
+ for (i = 0; i < 31; i++) {
+ if (count & (sign >> i)) {
+ if ((count & (~(sign >> i))) == 0)
+ timeout_n = 31 - i;
+ else
+ timeout_n = 31 - i + 1;
+ break;
+ }
+ }
+
+ heartbeat = (unsigned int)(0x01 << timeout_n) / MCF_BUSCLK;
+
+ MCF_SCM_CWCR = MCF_SCM_CWCR_CWE
+ | MCF_SCM_CWCR_CWRI(0x02)
+ | MCF_SCM_CWCR_CWT(timeout_n);
+
+ return 0;
+}
+
+/* Disable the watchdog */
+static void
+wdt_disable(void)
+{
+ MCF_SCM_CWCR = 0x00;
+}
+
+/* Reset the watchdog timer counter */
+static void
+wdt_keepalive(void)
+{
+ MCF_SCM_CWSR = 0x55;
+ MCF_SCM_CWSR = 0xAA;
+}
+#endif
+
+static int
+mcf_wdt_open(struct inode *inode, struct file *file)
+{
+ int ret;
+ if (test_and_set_bit(WDT_IN_USE, &wdt_status))
+ return -EBUSY;
+
+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+ ret = wdt_enable(heartbeat);
+ if (ret)
+ return ret;
+
+ return nonseekable_open(inode, file);
+}
+
+static ssize_t
+mcf_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
+{
+ if (len) {
+ if (!nowayout) {
+ size_t i;
+
+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+ for (i = 0; i != len; i++) {
+ char c;
+
+ if (get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ set_bit(WDT_OK_TO_CLOSE, &wdt_status);
+ }
+ }
+ wdt_keepalive();
+ }
+
+ return len;
+}
+
+
+static struct watchdog_info ident = {
+ .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT |
+ WDIOF_KEEPALIVEPING,
+ .identity = "Coldfire Watchdog",
+};
+
+static long
+mcf_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long __user arg)
+{
+ long ret = -ENOIOCTLCMD;
+ int time = 0;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ ret = copy_to_user((struct watchdog_info *)arg, &ident,
+ sizeof(ident)) ? -EFAULT : 0;
+ break;
+
+ case WDIOC_GETSTATUS:
+ ret = put_user(0, (int *)arg);
+ break;
+
+ case WDIOC_GETBOOTSTATUS:
+ ret = put_user(0, (int *)arg);
+ break;
+
+ case WDIOC_SETTIMEOUT:
+ ret = get_user(time, (int *)arg);
+ if (ret)
+ break;
+
+ ret = wdt_enable(time);
+ if (ret)
+ break;
+ ret = put_user(heartbeat, (int *)arg);
+ break;
+
+ case WDIOC_GETTIMEOUT:
+ ret = put_user(heartbeat, (int *)arg);
+ break;
+
+ case WDIOC_KEEPALIVE:
+ wdt_keepalive();
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static int
+mcf_wdt_release(struct inode *inode, struct file *file)
+{
+ if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) {
+#ifdef CONFIG_M547X_8X
+ MCF_GPT_GCIR0 = (0x0A << 16) | 0x09;
+ MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS0;
+#else
+ wdt_keepalive();
+#endif
+ } else {
+ printk(KERN_CRIT "WATCHDOG: Device closed unexpectdly\n");
+ wdt_disable();
+ }
+
+ clear_bit(WDT_IN_USE, &wdt_status);
+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+#ifdef CONFIG_M547X_8X
+ /*disable the XLB priority, otherwise the watchdog reset may fail*/
+ MCF_XARB_PRIEN = 0;
+ /* Also disable the PCI, Ugly! But there is issue between PCI and
+ * watchdog. Otherwise the watchdog reset may fail, only valuable
+ * for testing!
+ */
+ MCF_SPCR &= ~0x02;
+ asm("tpf");
+#endif
+
+ return 0;
+}
+
+
+static const struct file_operations mcf_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = mcf_wdt_write,
+ .unlocked_ioctl = mcf_wdt_ioctl,
+ .open = mcf_wdt_open,
+ .release = mcf_wdt_release,
+};
+
+static struct miscdevice mcf_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &mcf_wdt_fops,
+};
+
+static int __init mcf_wdt_init(void)
+{
+ wdt_tick_rate = MCF_BUSCLK/0xffff;
+#ifdef CONFIG_WATCHDOG_NOWAYOUT
+ nowayout = 1;
+#else
+ nowayout = 0;
+#endif
+ printk(KERN_INFO "ColdFire watchdog driver is loaded.\n");
+
+ return misc_register(&mcf_wdt_miscdev);
+}
+
+static void __exit mcf_wdt_exit(void)
+{
+ misc_deregister(&mcf_wdt_miscdev);
+}
+
+module_init(mcf_wdt_init);
+module_exit(mcf_wdt_exit);
+
+MODULE_AUTHOR("Deepak Saxena");
+MODULE_DESCRIPTION("ColdFire Watchdog");
+
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds (default 60s)");
+
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+

33
target/linux/coldfire/patches/032-Change-some-jffs2-warning-to-debug-info.patch Normal file
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@ -0,0 +1,33 @@
From 8834b24adf7efc8a50fcbc153910276b355fb4e9 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:47 +0800
Subject: [PATCH 32/52] Change some jffs2 warning to debug info
As the NFC issue, the jffs2 verify buf may fail sometimes.
This patch move this kind of warning to debug information.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
fs/jffs2/wbuf.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
--- a/fs/jffs2/wbuf.c
+++ b/fs/jffs2/wbuf.c
@@ -246,13 +246,13 @@ static int jffs2_verify_write(struct jff
else
eccstr = "OK or unused";
- printk(KERN_WARNING "Write verify error (ECC %s) at %08x. Wrote:\n",
+ printk(KERN_DEBUG "Write verify error (ECC %s) at %08x. Wrote:\n",
eccstr, c->wbuf_ofs);
- print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1,
+ print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
c->wbuf, c->wbuf_pagesize, 0);
- printk(KERN_WARNING "Read back:\n");
- print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1,
+ printk(KERN_DEBUG "Read back:\n");
+ print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
c->wbuf_verify, c->wbuf_pagesize, 0);
return -EIO;

49
target/linux/coldfire/patches/033-Fix-structure-fsl_ssd1289_data-definition-bug-for-SS.patch Normal file
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@ -0,0 +1,49 @@
From 1ebacc69cb9b9c2508b1e75cb23ef572cda51eec Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:47 +0800
Subject: [PATCH 33/52] Fix structure fsl_ssd1289_data definition bug for SSD1289 FB driver
Fix the bug that structure fsl_ssd1289_data definition depends on
DSPI enabled for SSD1289 framebuffer driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/coldfire/m5441x/devices.c | 20 ++++++++++----------
1 files changed, 10 insertions(+), 10 deletions(-)
--- a/arch/m68k/coldfire/m5441x/devices.c
+++ b/arch/m68k/coldfire/m5441x/devices.c
@@ -138,6 +138,16 @@ static struct platform_device nfc_device
};
#endif
+#if defined(CONFIG_FB_FSL_SSD1289) || defined(CONFIG_FB_FSL_SSD1289_MODULE)
+static struct fsl_ssd1289_fb_display fsl_ssd1289_data = {
+ .width = 320,
+ .height = 240,
+ .xres = 320,
+ .yres = 240,
+ .bpp = 16,
+};
+#endif
+
/*
* DSPI
*/
@@ -197,16 +207,6 @@ static struct coldfire_dspi_chip at26df0
};
#endif
-#if defined(CONFIG_FB_FSL_SSD1289) || defined(CONFIG_FB_FSL_SSD1289_MODULE)
-static struct fsl_ssd1289_fb_display fsl_ssd1289_data = {
- .width = 320,
- .height = 240,
- .xres = 320,
- .yres = 240,
- .bpp = 16,
-};
-#endif
-
#if defined(CONFIG_SSD1289_SPI_MODE)
static struct coldfire_dspi_chip ssd1289_chip_info = {
.mode = SPI_MODE_0,

50
target/linux/coldfire/patches/034-Enable-the-NFC-driver-for-soft_ecc.patch Normal file
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@ -0,0 +1,50 @@
From 25ebef8c87221774de01d1f1de4fb615fcfc6b54 Mon Sep 17 00:00:00 2001
From: Jason Jin <Jason.jin@freescale.com>
Date: Thu, 4 Aug 2011 09:59:47 +0800
Subject: [PATCH 34/52] Enable the NFC driver for soft_ecc.
If enabled YAFFS2 support, soft ecc should be used for the
nand flash driver.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
drivers/mtd/nand/Kconfig | 6 ++++++
drivers/mtd/nand/fsl_nfc.c | 12 +++++++++---
2 files changed, 15 insertions(+), 3 deletions(-)
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -481,6 +481,12 @@ config MTD_NAND_FSL_NFC
Enables support for NAND Flash chips wired onto Freescale PowerPC
processor localbus with User-Programmable Machine support.
+config MTD_NAND_FSL_NFC_SWECC
+ bool "Software ECC"
+ depends on MTD_NAND_FSL_NFC
+ help
+ Use software ECC.
+
config MTD_NAND_MXC
tristate "MXC NAND support"
depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51
--- a/drivers/mtd/nand/fsl_nfc.c
+++ b/drivers/mtd/nand/fsl_nfc.c
@@ -403,9 +403,15 @@ fsl_nfc_command(struct mtd_info *mtd, un
if (page != -1)
prv->page = page;
- nfc_set_field(mtd, NFC_FLASH_CONFIG,
- CONFIG_ECC_MODE_MASK,
- CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
+ if(hardware_ecc)
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_MODE_MASK,
+ CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
+ else
+ /* set ECC BY_PASS */
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_MODE_MASK,
+ CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
if (!(page%0x40)) {
nfc_set_field(mtd, NFC_FLASH_CONFIG,

764
target/linux/coldfire/patches/036-Add-FlexCAN-support-on-ColdFire-M548X-M54418-platfor.patch Normal file
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@ -0,0 +1,764 @@
From c3b97e08b06be76ee9f2b410b13c045425fc7f3e Mon Sep 17 00:00:00 2001
From: Jingchang Lu <b35083@freescale.com>
Date: Thu, 4 Aug 2011 09:59:48 +0800
Subject: [PATCH 36/52] Add FlexCAN support on ColdFire M548X, M54418 platform
Each cpu core has two FlexCAN interface, and the M54418's FlexCAN
also support Rx message buffer FIFO mode but M548X not.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
arch/m68k/Kconfig | 2 +
arch/m68k/coldfire/m5441x/Makefile | 4 +
arch/m68k/coldfire/m5441x/mcf-flexcan.c | 121 ++++++++++++++++
arch/m68k/coldfire/m547x/Makefile | 3 +
arch/m68k/coldfire/m547x/mcf-flexcan.c | 117 +++++++++++++++
drivers/net/can/Kconfig | 9 ++
drivers/net/can/flexcan.c | 239 ++++++++++++++++++++++++++++++-
7 files changed, 489 insertions(+), 6 deletions(-)
create mode 100644 arch/m68k/coldfire/m5441x/mcf-flexcan.c
create mode 100644 arch/m68k/coldfire/m547x/mcf-flexcan.c
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -372,6 +372,7 @@ config M547X
config M548X
bool
depends on M547X_8X
+ select HAVE_CAN_FLEXCAN
default n
choice
@@ -430,6 +431,7 @@ config M5441X
select GENERIC_TIME
select USB_EHCI_FSL
select HAVE_FSL_USB_DR
+ select HAVE_CAN_FLEXCAN
help
This option will add support for the MCF5441x processor with mmu.
--- a/arch/m68k/coldfire/m5441x/Makefile
+++ b/arch/m68k/coldfire/m5441x/Makefile
@@ -36,3 +36,7 @@ endif
ifneq ($(CONFIG_MODELO_SWITCH),)
obj-y += l2switch.o
endif
+
+ifneq ($(CONFIG_CAN_FLEXCAN),)
+obj-y += mcf-flexcan.o
+endif
--- /dev/null
+++ b/arch/m68k/coldfire/m5441x/mcf-flexcan.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Huan Wang, b18965@freescale.com, Fri Aug 08 2008
+ *
+ * Description:
+ * CAN bus driver for Freescale Coldfire embedded CPU
+ *
+ * Changelog:
+ * Fri Aug 08 2008 Huan Wang <b18965@freescale.com>
+ * - create, support for MCF548x
+ *
+ * Tue Dec 08 2009 ChengJu Cai <b22600@freescale.com>
+ * - support for MCF532x MCF5253 MCF5227x
+ *
+ * July 2011 Jingchang.Lu <b35083@freescale.com>
+ * - Add into kernel CAN driver layer
+ *
+ * This file is part of the Linux kernel
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <asm/mcfsim.h>
+
+
+static struct resource mcf5441x_can0_resources[] = {
+ [0] = {
+ .start = 0xFC020000,
+ .end = 0xFC0208C0,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0 + 64 + 64,
+ .end = 0 + 64 + 64,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource mcf5441x_can1_resources[] = {
+ [0] = {
+ .start = 0xFC024000,
+ .end = 0xFC0248C0,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 4 + 64 + 64,
+ .end = 4 + 64 + 64,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device mcf_flexcan[PDEV_MAX] = {
+ [0] = {
+ .name = "flexcan",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mcf5441x_can0_resources),
+ .resource = mcf5441x_can0_resources,
+ },
+ [1] = {
+ .name = "flexcan",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(mcf5441x_can1_resources),
+ .resource = mcf5441x_can1_resources,
+ },
+
+};
+
+
+static void __init mcf_flexcan_config(void)
+{
+ MCF_PM_PPMCR0 = 8; /* enable FlexCAN0 clock */
+ MCF_PM_PPMCR0 = 9; /* enable FlexCAN1 clock */
+
+ /* CAN0 */
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK) |
+ MCF_GPIO_PAR_CANI2C_I2C0SCL_CAN0TX;
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK) |
+ MCF_GPIO_PAR_CANI2C_I2C0SDA_CAN0RX;
+ /* CAN1 */
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1TX_MASK) |
+ MCF_GPIO_PAR_CANI2C_CAN1TX_CAN1TX;
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1RX_MASK) |
+ MCF_GPIO_PAR_CANI2C_CAN1RX_CAN1RX;
+
+
+}
+
+static int __init flexcan_of_to_pdev(void)
+{
+ int i, err = -ENODEV;
+ for (i = 0; i < PDEV_MAX; i++) {
+ err = platform_device_register(&mcf_flexcan[i]);
+ if (err)
+ return err;
+ printk(KERN_INFO "ColdFire FlexCAN devices loaded\n");
+ }
+ return err;
+}
+
+static int __init mcf_flexcan_init(void)
+{
+ int err;
+ mcf_flexcan_config();
+ err = flexcan_of_to_pdev();
+
+ return 0;
+}
+
+arch_initcall(mcf_flexcan_init);
--- a/arch/m68k/coldfire/m547x/Makefile
+++ b/arch/m68k/coldfire/m547x/Makefile
@@ -5,3 +5,6 @@
obj-$(CONFIG_M547X_8X) += config.o mcf548x-devices.o devices.o
obj-$(CONFIG_PCI) += pci.o pci_dummy.o
obj-$(CONFIG_MCD_DMA) += dma.o
+ifneq ($(CONFIG_CAN_FLEXCAN),)
+obj-y += mcf-flexcan.o
+endif
--- /dev/null
+++ b/arch/m68k/coldfire/m547x/mcf-flexcan.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Huan Wang, b18965@freescale.com, Fri Aug 08 2008
+ *
+ * Description:
+ * CAN bus driver for Freescale Coldfire embedded CPU
+ *
+ * Changelog:
+ * Fri Aug 08 2008 Huan Wang <b18965@freescale.com>
+ * - create, support for MCF548x
+ *
+ * Tue Dec 08 2009 ChengJu Cai <b22600@freescale.com>
+ * - support for MCF532x MCF5253 MCF5227x
+ *
+ * July 2011 Jingchang.Lu <b35083@freescale.com>
+ * - Add into kernel CAN driver layer
+ *
+ * This file is part of the Linux kernel
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <asm/mcfsim.h>
+
+
+static struct resource mcf548x_can0_resources[] = {
+ [0] = {
+ .start = MCF_MBAR + 0x0000A000,
+ .end = MCF_MBAR + 0x0000A7FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 49 + 64,
+ .end = 49 + 64,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource mcf548x_can1_resources[] = {
+ [0] = {
+ .start = MCF_MBAR + 0x0000A800,
+ .end = MCF_MBAR + 0x0000AFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 55 + 64,
+ .end = 55 + 64,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device mcf_flexcan[PDEV_MAX] = {
+ [0] = {
+ .name = "flexcan",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mcf548x_can1_resources),
+ .resource = mcf548x_can0_resources,
+ },
+ [1] = {
+ .name = "flexcan",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(mcf548x_can1_resources),
+ .resource = mcf548x_can1_resources,
+ },
+
+};
+
+
+static void __init mcf_flexcan_config(void)
+{
+ int i;
+ MCF_PAR_TIMER = MCF_PAR_TIMER | 0x28;
+ MCF_PAR_TIMER = MCF_PAR_TIMER & 0xf8;
+ MCF_PAR_DSPI = MCF_PAR_DSPI | 0x0a00;
+ MCF_PAR_FECI2CIRQ = MCF_PAR_FECI2CIRQ | 0x0283;
+ MCF_PAR_PSCn(2) = MCF_PAR_PSCn(2) & 0x0f;
+ MCF_PAR_PSCn(2) = MCF_PAR_PSCn(2) | 0x50;
+
+ for (i = 0; i < 2; i++) {
+ MCF_ICR(ISC_CANn_MBOR(i)) = 0x33 + 0x01 * i;
+ MCF_ICR(ISC_CANn_ERR(i)) = 0x33 + 0x01 * i;
+ MCF_ICR(ISC_CANn_BUSOFF(i)) = 0x33 + 0x01 * i;
+ }
+
+
+}
+
+static int __init flexcan_of_to_pdev(void)
+{
+ int i, err = -ENODEV;
+ for (i = 0; i < PDEV_MAX; i++) {
+ err = platform_device_register(&mcf_flexcan[i]);
+ if (err)
+ return err;
+ printk(KERN_INFO "ColdFire FlexCAN devices loaded\n");
+ }
+ return err;
+}
+
+static int __init mcf_flexcan_init(void)
+{
+ int err;
+ mcf_flexcan_config();
+ err = flexcan_of_to_pdev();
+
+ return 0;
+}
+
+arch_initcall(mcf_flexcan_init);
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -103,6 +103,15 @@ config CAN_FLEXCAN
---help---
Say Y here if you want to support for Freescale FlexCAN.
+config FLEXCAN_NORXFIFO
+ bool "FlexCAN message buffer without Rx FIFO mode"
+ depends on CAN_FLEXCAN && COLDFIRE
+ default n
+ ---help---
+ Say Y here if you FlexCAN message buffer has no Rx FIFO mode.
+ Freescale Coldfire series have different FlexCAN core version,
+ MCF54418's support Rx FIFO mode while others such as MCF5485 not.
+
config PCH_CAN
tristate "PCH CAN"
depends on CAN_DEV && PCI
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -4,6 +4,7 @@
* Copyright (c) 2005-2006 Varma Electronics Oy
* Copyright (c) 2009 Sascha Hauer, Pengutronix
* Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
*
* Based on code originally by Andrey Volkov <avolkov@varma-el.com>
*
@@ -35,8 +36,28 @@
#include <linux/module.h>
#include <linux/platform_device.h>
+#ifndef CONFIG_COLDFIRE
#include <mach/clock.h>
+#else
+#include <asm/mcfsim.h>
+
+#undef readb
+#undef readw
+#undef readl
+#define readb(addr) __raw_readb(addr)
+#define readw(addr) __raw_readw(addr)
+#define readl(addr) __raw_readl(addr)
+
+#undef writeb
+#undef writew
+#undef writel
+#define writeb(b, addr) __raw_writeb(b, addr)
+#define writew(b, addr) __raw_writew(b, addr)
+#define writel(b, addr) __raw_writel(b, addr)
+
+#endif
+
#define DRV_NAME "flexcan"
/* 8 for RX fifo and 2 error handling */
@@ -85,12 +106,34 @@
#define FLEXCAN_CTRL_LOM BIT(3)
#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
+
+#ifdef CONFIG_COLDFIRE
+
+# if defined(CONFIG_M548X)
+
+#define FLEXCAN_CTRL_ERR_STATE FLEXCAN_CTRL_BOFF_MSK
+#define FLEXCAN_CTRL_ERR_ALL \
+ (FLEXCAN_CTRL_BOFF_MSK | FLEXCAN_CTRL_ERR_MSK)
+
+# elif defined(CONFIG_M5441X)
+
#define FLEXCAN_CTRL_ERR_STATE \
(FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
FLEXCAN_CTRL_BOFF_MSK)
#define FLEXCAN_CTRL_ERR_ALL \
(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
+# endif
+
+#else /* !CONFIG_COLDFIRE */
+
+#define FLEXCAN_CTRL_ERR_STATE \
+ (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
+ FLEXCAN_CTRL_BOFF_MSK)
+#define FLEXCAN_CTRL_ERR_ALL \
+ (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
+
+#endif
/* FLEXCAN error and status register (ESR) bits */
#define FLEXCAN_ESR_TWRN_INT BIT(17)
#define FLEXCAN_ESR_RWRN_INT BIT(16)
@@ -121,6 +164,18 @@
(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
/* FLEXCAN interrupt flag register (IFLAG) bits */
+
+#ifdef CONFIG_FLEXCAN_NORXFIFO
+
+/* MB assignment for no Rx FIFO mode module */
+#define FLEXCAN_TX_BUF_ID 0
+#define FLEXCAN_RX_EXT_ID 15
+#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE 0xfffe
+#define FLEXCAN_IFLAG_DEFAULT \
+ (FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | (0x01 << FLEXCAN_TX_BUF_ID))
+
+#else
+
#define FLEXCAN_TX_BUF_ID 8
#define FLEXCAN_IFLAG_BUF(x) BIT(x)
#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
@@ -130,6 +185,7 @@
(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
+#endif
/* FLEXCAN message buffers */
#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
#define FLEXCAN_MB_CNT_SRR BIT(22)
@@ -163,7 +219,11 @@ struct flexcan_regs {
u32 iflag2; /* 0x2c */
u32 iflag1; /* 0x30 */
u32 _reserved2[19];
+#ifdef CONFIG_COLDFIRE
+ struct flexcan_mb cantxfg[CAN_MB];
+#else
struct flexcan_mb cantxfg[64];
+#endif
};
struct flexcan_priv {
@@ -181,8 +241,13 @@ struct flexcan_priv {
static struct can_bittiming_const flexcan_bittiming_const = {
.name = DRV_NAME,
+#ifdef CONFIG_COLDFIRE
+ .tseg1_min = 1,
+ .tseg1_max = 8,
+#else
.tseg1_min = 4,
.tseg1_max = 16,
+#endif
.tseg2_min = 2,
.tseg2_max = 8,
.sjw_max = 4,
@@ -248,7 +313,7 @@ static int flexcan_start_xmit(struct sk_
struct net_device_stats *stats = &dev->stats;
struct flexcan_regs __iomem *regs = priv->base;
struct can_frame *cf = (struct can_frame *)skb->data;
- u32 can_id;
+ u32 can_id, tmp, tmp1;
u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
if (can_dropped_invalid_skb(dev, skb))
@@ -259,6 +324,11 @@ static int flexcan_start_xmit(struct sk_
if (cf->can_id & CAN_EFF_FLAG) {
can_id = cf->can_id & CAN_EFF_MASK;
ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
+#ifdef CONFIG_COLDFIRE
+ tmp = (can_id & CAN_SFF_MASK) << 18;
+ tmp1 = can_id >> 11;
+ can_id = tmp | tmp1;
+#endif
} else {
can_id = (cf->can_id & CAN_SFF_MASK) << 18;
}
@@ -456,6 +526,87 @@ static int flexcan_poll_state(struct net
return 1;
}
+#ifdef CONFIG_FLEXCAN_NORXFIFO
+/* Get one frame from receive message buffer */
+static int flexcan_read_frame(struct net_device *dev)
+{
+ const struct flexcan_priv *priv = netdev_priv(dev);
+ struct flexcan_regs __iomem *regs = priv->base;
+ struct net_device_stats *stats = &dev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+ struct flexcan_mb __iomem *mb;
+ u32 reg_iflag1, reg_ctrl, reg_id, i;
+
+ reg_iflag1 = readl(&regs->iflag1);
+
+ /* buf[0] if for TX */
+ for (i = 0; i < CAN_MB; i++) {
+ if (i == FLEXCAN_TX_BUF_ID)
+ continue;
+ /* find one received message slot */
+ if (reg_iflag1 & (0x01 << i))
+ break;
+ }
+ if (i >= CAN_MB)
+ return 0;
+
+ mb = &regs->cantxfg[i];
+
+ skb = alloc_can_skb(dev, &cf);
+ if (unlikely(!skb)) {
+ stats->rx_dropped++;
+ return 0;
+ }
+
+ reg_ctrl = readl(&mb->can_ctrl);
+ reg_id = readl(&mb->can_id);
+
+ /* deactive RX buff */
+ writel(0, &mb->can_ctrl);
+
+ if (reg_ctrl & FLEXCAN_MB_CNT_IDE) {
+#ifdef CONFIG_COLDFIRE
+ /* Coldfire can_id order */
+ cf->can_id = (reg_id & CAN_EFF_MASK) >> 18;
+ cf->can_id |= (reg_id & 0x3ffff) << 11;
+ cf->can_id |= CAN_EFF_FLAG;
+#else
+ cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
+#endif
+ } else
+ cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
+
+ if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
+ cf->can_id |= CAN_RTR_FLAG;
+ cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
+
+ *(__be32 *)(cf->data + 0) = cpu_to_be32(readl(&mb->data[0]));
+ *(__be32 *)(cf->data + 4) = cpu_to_be32(readl(&mb->data[1]));
+
+ /* reactive RX buffer */
+ if (i == FLEXCAN_RX_EXT_ID)
+ writel(FLEXCAN_MB_CNT_CODE(0x4)|0x600000,
+ &regs->cantxfg[i].can_ctrl);
+ else
+ writel(FLEXCAN_MB_CNT_CODE(0x4),
+ &regs->cantxfg[i].can_ctrl);
+
+ /* mark as read */
+ writel((0x01 << i), &regs->iflag1);
+ /* release MB lock */
+ readl(&regs->timer);
+
+ netif_receive_skb(skb);
+
+ stats->rx_packets++;
+ stats->rx_bytes += cf->can_dlc;
+
+ return 1;
+
+}
+#else
+
static void flexcan_read_fifo(const struct net_device *dev,
struct can_frame *cf)
{
@@ -466,9 +617,16 @@ static void flexcan_read_fifo(const stru
reg_ctrl = readl(&mb->can_ctrl);
reg_id = readl(&mb->can_id);
- if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
+ if (reg_ctrl & FLEXCAN_MB_CNT_IDE) {
+#ifdef CONFIG_COLDFIRE
+ /* ColdFire can_id order as follow */
+ cf->can_id = (reg_id & CAN_EFF_MASK) >> 18;
+ cf->can_id |= (reg_id & 0x3ffff) << 11;
+ cf->can_id |= CAN_EFF_FLAG;
+#else
cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
- else
+#endif
+ } else
cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
@@ -503,6 +661,7 @@ static int flexcan_read_frame(struct net
return 1;
}
+#endif
static int flexcan_poll(struct napi_struct *napi, int quota)
{
@@ -554,6 +713,14 @@ static irqreturn_t flexcan_irq(int irq,
reg_iflag1 = readl(&regs->iflag1);
reg_esr = readl(&regs->esr);
writel(FLEXCAN_ESR_ERR_INT, &regs->esr); /* ACK err IRQ */
+#ifdef CONFIG_COLDFIRE
+#ifdef CONFIG_FLEXCAN_NORXFIFO
+ writel(FLEXCAN_ESR_BOFF_INT, &regs->esr);
+#else
+ /* ACK TWRN and RWRN error, and bus-off interrupt*/
+ writel(FLEXCAN_ESR_ERR_STATE, &regs->esr);
+#endif
+#endif
/*
* schedule NAPI in case of:
@@ -575,13 +742,14 @@ static irqreturn_t flexcan_irq(int irq,
&regs->ctrl);
napi_schedule(&priv->napi);
}
-
+#ifndef CONFIG_FLEXCAN_NORXFIFO
/* FIFO overflow */
if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
writel(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
dev->stats.rx_over_errors++;
dev->stats.rx_errors++;
}
+#endif
/* transmission complete interrupt */
if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
@@ -676,9 +844,14 @@ static int flexcan_chip_start(struct net
*
*/
reg_mcr = readl(&regs->mcr);
+#ifdef CONFIG_FLEXCAN_NORXFIFO
+ reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
+ FLEXCAN_MCR_SUPV;
+#else
reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
FLEXCAN_MCR_IDAM_C;
+#endif
dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr);
writel(reg_mcr, &regs->mcr);
@@ -713,9 +886,19 @@ static int flexcan_chip_start(struct net
writel(0, &regs->cantxfg[i].can_id);
writel(0, &regs->cantxfg[i].data[0]);
writel(0, &regs->cantxfg[i].data[1]);
-
+#ifdef CONFIG_FLEXCAN_NORXFIFO
+ if (i == FLEXCAN_TX_BUF_ID)
+ continue;
+ if (i == FLEXCAN_RX_EXT_ID) /* enable receive extend message */
+ writel(FLEXCAN_MB_CNT_CODE(0x4)|0x600000,
+ &regs->cantxfg[i].can_ctrl);
+ else
+ writel(FLEXCAN_MB_CNT_CODE(0x4),
+ &regs->cantxfg[i].can_ctrl);
+#else
/* put MB into rx queue */
writel(FLEXCAN_MB_CNT_CODE(0x4), &regs->cantxfg[i].can_ctrl);
+#endif
}
/* acceptance mask/acceptance code (accept everything) */
@@ -772,6 +955,7 @@ static void flexcan_chip_stop(struct net
return;
}
+
static int flexcan_open(struct net_device *dev)
{
struct flexcan_priv *priv = netdev_priv(dev);
@@ -786,6 +970,24 @@ static int flexcan_open(struct net_devic
err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
if (err)
goto out_close;
+ err = request_irq(dev->irq + 1, flexcan_irq, \
+ IRQF_DISABLED, dev->name, dev);
+ if (err) {
+ free_irq(dev->irq, dev);
+ goto out_close;
+ }
+#if defined(CONFIG_M548X)
+ err = request_irq(dev->irq + 2, flexcan_irq, \
+ IRQF_DISABLED, dev->name, dev);
+#elif defined(CONFIG_M5441X)
+ err = request_irq(dev->irq + 3, flexcan_irq, \
+ IRQF_DISABLED, dev->name, dev);
+#endif
+ if (err) {
+ free_irq(dev->irq, dev);
+ free_irq(dev->irq + 1, dev);
+ goto out_close;
+ }
/* start chip and queuing */
err = flexcan_chip_start(dev);
@@ -813,6 +1015,14 @@ static int flexcan_close(struct net_devi
flexcan_chip_stop(dev);
free_irq(dev->irq, dev);
+#ifdef CONFIG_COLDFIRE
+ free_irq(dev->irq + 1, dev);
+#if defined(CONFIG_M548X)
+ free_irq(dev->irq + 2, dev);
+#elif defined(CONFIG_M5441X)
+ free_irq(dev->irq + 3, dev);
+#endif
+#endif
clk_disable(priv->clk);
close_candev(dev);
@@ -854,14 +1064,23 @@ static int __devinit register_flexcandev
clk_enable(priv->clk);
+#if !defined(CONFIG_M548X)
/* select "bus clock", chip must be disabled */
flexcan_chip_disable(priv);
reg = readl(&regs->ctrl);
reg |= FLEXCAN_CTRL_CLK_SRC;
writel(reg, &regs->ctrl);
+#endif
flexcan_chip_enable(priv);
+#ifdef CONFIG_FLEXCAN_NORXFIFO
+ /* set freeze, halt and restrict register access */
+ reg = readl(&regs->mcr);
+ reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
+ FLEXCAN_MCR_SUPV;
+ writel(reg, &regs->mcr);
+#else
/* set freeze, halt and activate FIFO, restrict register access */
reg = readl(&regs->mcr);
reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
@@ -880,6 +1099,7 @@ static int __devinit register_flexcandev
err = -ENODEV;
goto out;
}
+#endif
err = register_candev(dev);
@@ -901,17 +1121,19 @@ static int __devinit flexcan_probe(struc
struct net_device *dev;
struct flexcan_priv *priv;
struct resource *mem;
- struct clk *clk;
+ struct clk *clk = NULL;
void __iomem *base;
resource_size_t mem_size;
int err, irq;
+#ifndef CONFIG_COLDFIRE
clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "no clock defined\n");
err = PTR_ERR(clk);
goto failed_clock;
}
+#endif
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
@@ -943,7 +1165,12 @@ static int __devinit flexcan_probe(struc
dev->flags |= IFF_ECHO; /* we support local echo in hardware */
priv = netdev_priv(dev);
+#ifdef CONFIG_COLDFIRE
+ /* return value is core clock but we need bus clock */
+ priv->can.clock.freq = (clk_get_rate(clk)/2);
+#else
priv->can.clock.freq = clk_get_rate(clk);
+#endif
priv->can.bittiming_const = &flexcan_bittiming_const;
priv->can.do_set_mode = flexcan_set_mode;
priv->can.do_get_berr_counter = flexcan_get_berr_counter;

934
target/linux/coldfire/patches/037-Add-ColdFire-MCF54455-PATA-interface-support.patch Normal file
View File

@ -0,0 +1,934 @@
From 8e46c06091fd87904205a977be3c784e3ac61e95 Mon Sep 17 00:00:00 2001
From: Jingchang Lu <b35083@freescale.com>
Date: Thu, 4 Aug 2011 09:59:48 +0800
Subject: [PATCH 37/52] Add ColdFire MCF54455 PATA interface support
ColdFire MCF54455 parallel ATA controller support
both uDMA and PIO mode, this driver implements all.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
arch/m68k/include/asm/pata_fsl.h | 17 +
drivers/ata/Kconfig | 23 +-
drivers/ata/Makefile | 1 +
drivers/ata/pata_fsl.c | 844 ++++++++++++++++++++++++++++++++++++++
4 files changed, 884 insertions(+), 1 deletions(-)
create mode 100644 arch/m68k/include/asm/pata_fsl.h
create mode 100644 drivers/ata/pata_fsl.c
--- /dev/null
+++ b/arch/m68k/include/asm/pata_fsl.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _ASM_M68K_PATA_FSL_H
+#define _ASM_M68K_PATA_FSL_H
+
+/* ATA mapped IO address translate function */
+extern unsigned int io_ata_virt2phys(void *x);
+extern void *io_ata_phys2virt(unsigned int x);
+
+
+#endif
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -14,7 +14,7 @@ menuconfig ATA
tristate "Serial ATA and Parallel ATA drivers"
depends on HAS_IOMEM
depends on BLOCK
- depends on !(M32R || M68K) || BROKEN
+ depends on !(M32R) || BROKEN
select SCSI
---help---
If you want to use a ATA hard disk, ATA tape drive, ATA CD-ROM or
@@ -687,6 +687,27 @@ config PATA_WINBOND
If unsure, say N.
+config PATA_FSL
+ tristate "Freescale on-chip PATA support"
+ depends on (ARCH_MX3 || ARCH_MX27 || PPC_512x || M54455)
+ help
+ Some Freescale processors SOC have parallel ATA controller,
+ such as ColdFire MCF54455.
+
+ Say Y here if you wish to use the on-chip ATA interface.
+
+ If you are unsure, say N to this.
+
+config FSL_PATA_USE_DMA
+ bool "Freescale PATA eDMA support"
+ depends on PATA_FSL && COLDFIRE_EDMA
+ default y
+ help
+ This option enables the uDMA support over PATA interface
+ which can improve performance than PIO mode for read and write.
+
+ If unsure, say Y.
+
endif # ATA_BMDMA
comment "PIO-only SFF controllers"
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_PATA_TOSHIBA) += pata_picco
obj-$(CONFIG_PATA_TRIFLEX) += pata_triflex.o
obj-$(CONFIG_PATA_VIA) += pata_via.o
obj-$(CONFIG_PATA_WINBOND) += pata_sl82c105.o
+obj-$(CONFIG_PATA_FSL) += pata_fsl.o
# SFF PIO only
obj-$(CONFIG_PATA_AT32) += pata_at32.o
--- /dev/null
+++ b/drivers/ata/pata_fsl.c
@@ -0,0 +1,844 @@
+/*
+ * Freescale integrated PATA driver
+ *
+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Description:
+ * This driver is for Coldfire MCF54455 on-chip ATA module.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <scsi/scsi_host.h>
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#ifdef CONFIG_FSL_PATA_USE_DMA
+#include <asm/mcf_edma.h>
+#endif
+#include <asm/pata_fsl.h>
+
+#define DRV_NAME "pata_fsl"
+#define DRV_VERSION "1.0"
+
+#ifdef CONFIG_M54455
+#define WRITE_ATA8(val, reg) \
+ __raw_writeb(val, (ata_regs + reg));
+#define WRITE_ATA16(val, reg) \
+ __raw_writew(val, (ata_regs + reg));
+#else
+#define WRITE_ATA8(val, reg) \
+ __raw_writel(val, (ata_regs + reg));
+#define WRITE_ATA16(val, reg) \
+ __raw_writel(val, (ata_regs + reg));
+#endif
+
+#define MAX_FSL_SG 256 /* MCF_EDMA_TCD_PER_CHAN */
+
+struct pata_fsl_priv {
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ int ultra;
+#endif
+ u8 *fsl_ata_regs;
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ int dma_rchan;
+ int dma_wchan;
+ int dma_done;
+ int dma_dir;
+#if 0
+ int nsg;
+ struct fsl_edma_requestbuf reqbuf[MAX_FSL_SG];
+#endif
+#endif
+};
+
+enum {
+ /* various constants */
+
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ FSL_ATA_MAX_SG_LEN = 65534,
+#endif
+
+ /* offsets to registers */
+
+ FSL_ATA_TIMING_REGS = 0x00,
+ FSL_ATA_FIFO_FILL = 0x20,
+ FSL_ATA_CONTROL = 0x24,
+ FSL_ATA_INT_PEND = 0x28,
+ FSL_ATA_INT_EN = 0x2C,
+ FSL_ATA_INT_CLEAR = 0x30,
+ FSL_ATA_FIFO_ALARM = 0x34,
+ FSL_ATA_DRIVE_DATA = 0xA0,
+ FSL_ATA_DRIVE_CONTROL = 0xD8,
+
+ /* bits within FSL_ATA_CONTROL */
+
+ FSL_ATA_CTRL_FIFO_RST_B = 0x80,
+ FSL_ATA_CTRL_ATA_RST_B = 0x40,
+ FSL_ATA_CTRL_FIFO_TX_EN = 0x20,
+ FSL_ATA_CTRL_FIFO_RCV_EN = 0x10,
+ FSL_ATA_CTRL_DMA_PENDING = 0x08,
+ FSL_ATA_CTRL_DMA_ULTRA = 0x04,
+ FSL_ATA_CTRL_DMA_WRITE = 0x02,
+ FSL_ATA_CTRL_IORDY_EN = 0x01,
+
+ /* bits within the interrupt control registers */
+
+ FSL_ATA_INTR_ATA_INTRQ1 = 0x80,
+ FSL_ATA_INTR_FIFO_UNDERFLOW = 0x40,
+ FSL_ATA_INTR_FIFO_OVERFLOW = 0x20,
+ FSL_ATA_INTR_CTRL_IDLE = 0x10,
+ FSL_ATA_INTR_ATA_INTRQ2 = 0x08,
+};
+
+/*
+ * This structure contains the timing parameters for
+ * ATA bus timing in the 5 PIO modes. The timings
+ * are in nanoseconds, and are converted to clock
+ * cycles before being stored in the ATA controller
+ * timing registers.
+ */
+static struct {
+ short t0, t1, t2_8, t2_16, t2i, t4, t9, tA;
+} pio_specs[] = {
+ [0] = {
+ .t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 0,
+ .t4 = 30, .t9 = 20, .tA = 50
+ },
+ [1] = {
+ .t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0,
+ .t4 = 20, .t9 = 15, .tA = 50
+ },
+ [2] = {
+ .t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0,
+ .t4 = 15, .t9 = 10, .tA = 50
+ },
+ [3] = {
+ .t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0,
+ .t4 = 10, .t9 = 10, .tA = 50
+ },
+ [4] = {
+ .t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0,
+ .t4 = 10, .t9 = 10, .tA = 50
+ },
+};
+
+#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0])
+
+/*
+ * This structure contains the timing parameters for
+ * ATA bus timing in the 3 MDMA modes. The timings
+ * are in nanoseconds, and are converted to clock
+ * cycles before being stored in the ATA controller
+ * timing registers.
+ */
+static struct {
+ short t0M, tD, tH, tJ, tKW, tM, tN, tJNH;
+} mdma_specs[] = {
+ [0] = {
+ .t0M = 480, .tD = 215, .tH = 20, .tJ = 20, .tKW = 215,
+ .tM = 50, .tN = 15, .tJNH = 20
+ },
+ [1] = {
+ .t0M = 150, .tD = 80, .tH = 15, .tJ = 5, .tKW = 50,
+ .tM = 30, .tN = 10, .tJNH = 15
+ },
+ [2] = {
+ .t0M = 120, .tD = 70, .tH = 10, .tJ = 5, .tKW = 25,
+ .tM = 25, .tN = 10, .tJNH = 10
+ },
+};
+
+#define NR_MDMA_SPECS (sizeof mdma_specs / sizeof mdma_specs[0])
+
+/*
+ * This structure contains the timing parameters for
+ * ATA bus timing in the 6 UDMA modes. The timings
+ * are in nanoseconds, and are converted to clock
+ * cycles before being stored in the ATA controller
+ * timing registers.
+ */
+static struct {
+ short t2CYC, tCYC, tDS, tDH, tDVS, tDVH, tCVS, tCVH, tFS_min, tLI_max,
+ tMLI, tAZ, tZAH, tENV_min, tSR, tRFS, tRP, tACK, tSS, tDZFS;
+} udma_specs[] = {
+ [0] = {
+ .t2CYC = 235, .tCYC = 114, .tDS = 15, .tDH = 5, .tDVS = 70,
+ .tDVH = 6, .tCVS = 70, .tCVH = 6, .tFS_min = 0,
+ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
+ .tENV_min = 20, .tSR = 50, .tRFS = 75, .tRP = 160,
+ .tACK = 20, .tSS = 50, .tDZFS = 80
+ },
+ [1] = {
+ .t2CYC = 156, .tCYC = 75, .tDS = 10, .tDH = 5, .tDVS = 48,
+ .tDVH = 6, .tCVS = 48, .tCVH = 6, .tFS_min = 0,
+ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
+ .tENV_min = 20, .tSR = 30, .tRFS = 70, .tRP = 125,
+ .tACK = 20, .tSS = 50, .tDZFS = 63
+ },
+ [2] = {
+ .t2CYC = 117, .tCYC = 55, .tDS = 7, .tDH = 5, .tDVS = 34,
+ .tDVH = 6, .tCVS = 34, .tCVH = 6, .tFS_min = 0,
+ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
+ .tENV_min = 20, .tSR = 20, .tRFS = 60, .tRP = 100,
+ .tACK = 20, .tSS = 50, .tDZFS = 47
+ },
+ [3] = {
+ .t2CYC = 86, .tCYC = 39, .tDS = 7, .tDH = 5, .tDVS = 20,
+ .tDVH = 6, .tCVS = 20, .tCVH = 6, .tFS_min = 0,
+ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
+ .tENV_min = 20, .tSR = 20, .tRFS = 60, .tRP = 100,
+ .tACK = 20, .tSS = 50, .tDZFS = 35
+ },
+ [4] = {
+ .t2CYC = 57, .tCYC = 25, .tDS = 5, .tDH = 5, .tDVS = 7,
+ .tDVH = 6, .tCVS = 7, .tCVH = 6, .tFS_min = 0,
+ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
+ .tENV_min = 20, .tSR = 50, .tRFS = 60, .tRP = 100,
+ .tACK = 20, .tSS = 50, .tDZFS = 25
+ },
+ [5] = {
+ .t2CYC = 38, .tCYC = 17, .tDS = 4, .tDH = 5, .tDVS = 5,
+ .tDVH = 6, .tCVS = 10, .tCVH = 10, .tFS_min = 0,
+ .tLI_max = 75, .tMLI = 20, .tAZ = 10, .tZAH = 20,
+ .tENV_min = 20, .tSR = 20, .tRFS = 50, .tRP = 85,
+ .tACK = 20, .tSS = 50, .tDZFS = 40
+ },
+};
+
+#define NR_UDMA_SPECS (sizeof udma_specs / sizeof udma_specs[0])
+
+struct fsl_ata_time_regs {
+ u8 time_off, time_on, time_1, time_2w;
+ u8 time_2r, time_ax, time_pio_rdx, time_4;
+ u8 time_9, time_m, time_jn, time_d;
+ u8 time_k, time_ack, time_env, time_rpx;
+ u8 time_zah, time_mlix, time_dvh, time_dzfs;
+ u8 time_dvs, time_cvh, time_ss, time_cyc;
+} __packed;
+
+
+static void update_timing_config(struct fsl_ata_time_regs *tp,
+ struct ata_host *host)
+{
+ u32 __iomem *lp = (u32 __iomem *)tp;
+ struct pata_fsl_priv *priv = host->private_data;
+ u32 __iomem *ctlp = (u32 __iomem *)priv->fsl_ata_regs;
+ int i;
+
+ /*
+ * JKM - this could have endianess issues on BE depending
+ * on how the controller is glued to the bus -- probably
+ * should rewrite this to write byte at a time.
+ */
+ for (i = 0; i < 6; i++) {
+ __raw_writel(*lp, ctlp);
+ lp++;
+ ctlp++;
+ }
+}
+
+/*!
+ * Calculate values for the ATA bus timing registers and store
+ * them into the hardware.
+ *
+ * @param xfer_mode specifies XFER xfer_mode
+ * @param pdev specifies platform_device
+ *
+ * @return EINVAL speed out of range, or illegal mode
+ */
+static int set_ata_bus_timing(u8 xfer_mode, struct platform_device *pdev)
+{
+ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+ pdev->dev.platform_data;
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ /* get the bus clock cycle time, in ns */
+ int T = 1 * 1000 * 1000 * 1000 / plat->get_clk_rate();
+ struct fsl_ata_time_regs tr = {0};
+ DPRINTK("clk_rate = %d T = %d\n", plat->get_clk_rate(), T);
+
+ /*
+ * every mode gets the same t_off and t_on
+ */
+ tr.time_off = 3;
+ tr.time_on = 3;
+
+ if (xfer_mode >= XFER_UDMA_0) {
+ int speed = xfer_mode - XFER_UDMA_0;
+ if (speed >= NR_UDMA_SPECS)
+ return -EINVAL;
+
+ tr.time_ack = (udma_specs[speed].tACK + T) / T;
+ tr.time_env = (udma_specs[speed].tENV_min + T) / T;
+ tr.time_rpx = (udma_specs[speed].tRP + T) / T + 2;
+
+ tr.time_zah = (udma_specs[speed].tZAH + T) / T;
+ tr.time_mlix = (udma_specs[speed].tMLI + T) / T;
+ tr.time_dvh = (udma_specs[speed].tDVH + T) / T + 1;
+ tr.time_dzfs = (udma_specs[speed].tDZFS + T) / T;
+
+ tr.time_dvs = (udma_specs[speed].tDVS + T) / T;
+ tr.time_cvh = (udma_specs[speed].tCVH + T) / T;
+ tr.time_ss = (udma_specs[speed].tSS + T) / T;
+ tr.time_cyc = (udma_specs[speed].tCYC + T) / T;
+ } else if (xfer_mode >= XFER_MW_DMA_0) {
+ int speed = xfer_mode - XFER_MW_DMA_0;
+ if (speed >= NR_MDMA_SPECS)
+ return -EINVAL;
+
+ tr.time_m = (mdma_specs[speed].tM + T) / T;
+ tr.time_jn = (mdma_specs[speed].tJNH + T) / T;
+ tr.time_d = (mdma_specs[speed].tD + T) / T;
+
+ tr.time_k = (mdma_specs[speed].tKW + T) / T;
+ } else {
+ int speed = xfer_mode - XFER_PIO_0;
+ if (speed >= NR_PIO_SPECS)
+ return -EINVAL;
+
+ tr.time_1 = (pio_specs[speed].t1 + T) / T;
+ tr.time_2w = (pio_specs[speed].t2_8 + T) / T;
+
+ tr.time_2r = (pio_specs[speed].t2_8 + T) / T;
+ tr.time_ax = (pio_specs[speed].tA + T) / T + 2;
+ tr.time_pio_rdx = 1;
+ tr.time_4 = (pio_specs[speed].t4 + T) / T;
+
+ tr.time_9 = (pio_specs[speed].t9 + T) / T;
+ }
+
+ update_timing_config(&tr, host);
+
+ return 0;
+}
+
+static void pata_fsl_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+ set_ata_bus_timing(adev->pio_mode, to_platform_device(ap->dev));
+}
+
+#ifdef CONFIG_FSL_PATA_USE_DMA
+static void pata_fsl_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+{
+ struct pata_fsl_priv *priv = ap->host->private_data;
+
+ priv->ultra = adev->dma_mode >= XFER_UDMA_0;
+
+ set_ata_bus_timing(adev->dma_mode, to_platform_device(ap->dev));
+}
+#endif
+
+static int pata_fsl_port_start(struct ata_port *ap)
+{
+ return 0;
+}
+
+#ifdef CONFIG_FSL_PATA_USE_DMA
+
+static irqreturn_t dma_callback(int channel, void *arg)
+{
+ struct ata_port *ap = arg;
+ struct pata_fsl_priv *priv = ap->host->private_data;
+ u8 __iomem *ata_regs = priv->fsl_ata_regs;
+
+ mcf_edma_stop_transfer(channel);
+ priv->dma_done = 1;
+ /*
+ * DMA is finished, so unmask INTRQ from the drive to allow the
+ * normal ISR to fire.
+ */
+#if 0
+ __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN);
+#else
+ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN);
+ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL);
+#endif
+
+ return IRQ_HANDLED;
+}
+
+static void pata_fsl_bmdma_setup(struct ata_queued_cmd *qc)
+{
+ int chan;
+ int dma_ultra;
+ u8 ata_control;
+ struct ata_port *ap = qc->ap;
+ struct pata_fsl_priv *priv = ap->host->private_data;
+ u8 __iomem *ata_regs = priv->fsl_ata_regs;
+#if 0
+ struct scatterlist *sg;
+ struct fsl_edma_requestbuf *pbuf;
+ unsigned int si;
+#endif
+ DPRINTK("ENTER\n");
+
+ /* reset the ATA FIFO first */
+ /*
+ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B,FSL_ATA_CONTROL);
+ */
+ priv->dma_dir = qc->dma_dir;
+
+ /*
+ * Configure the on-chip ATA interface hardware.
+ */
+ dma_ultra = priv->ultra ?
+ FSL_ATA_CTRL_DMA_ULTRA : 0;
+
+ ata_control = FSL_ATA_CTRL_FIFO_RST_B |
+ FSL_ATA_CTRL_ATA_RST_B |
+ FSL_ATA_CTRL_DMA_PENDING |
+ dma_ultra;
+
+ if (qc->dma_dir == DMA_TO_DEVICE) {
+ chan = priv->dma_wchan;
+ ata_control |= FSL_ATA_CTRL_FIFO_TX_EN |
+ FSL_ATA_CTRL_DMA_WRITE;
+ } else {
+ chan = priv->dma_rchan;
+ ata_control |= FSL_ATA_CTRL_FIFO_RCV_EN;
+ }
+#if 0
+ __raw_writel(ata_control, ata_regs + FSL_ATA_CONTROL);
+ __raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_FIFO_ALARM);
+ __raw_writel(FSL_ATA_INTR_ATA_INTRQ1, ata_regs + FSL_ATA_INT_EN);
+#else
+ WRITE_ATA8(ata_control, FSL_ATA_CONTROL);
+ WRITE_ATA8(16/*plat->fifo_alarm*/, FSL_ATA_FIFO_ALARM);
+ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ1, FSL_ATA_INT_EN);
+#endif
+ /*mb();*/
+
+ /*
+ * Set up the DMA completion callback.
+ */
+ /*
+ * Copy the sg list to an array.
+ */
+#if 0
+ priv->nsg = 0;
+ pbuf = priv->reqbuf;
+
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
+
+ /*dma_map_sg(NULL, sg, 1, priv->dma_dir); */
+
+ if (priv->dma_dir == DMA_TO_DEVICE) { /* WRITE */
+ pbuf->saddr = sg->dma_address;
+ pbuf->daddr = (dma_addr_t)(priv->fsl_ata_regs + 0x18);
+ pbuf->soff = 4;
+ pbuf->doff = 0;
+ } else { /* Read */
+ pbuf->daddr = sg->dma_address;
+ pbuf->saddr = (dma_addr_t)(priv->fsl_ata_regs + 0x18);
+ pbuf->doff = 4;
+ pbuf->soff = 0;
+ }
+ pbuf->attr = MCF_EDMA_TCD_ATTR_SSIZE_32BIT
+ |MCF_EDMA_TCD_ATTR_DSIZE_32BIT;
+ pbuf->minor_loop = 16*4; /* 16 longwords per request*/
+ pbuf->len = sg_dma_len(sg);
+
+ pbuf++;
+ priv->nsg++;
+ }
+
+ BUG_ON(*(unsigned char *)(ata_regs + FSL_ATA_FIFO_FILL));
+ mcf_edma_sg_config(chan, priv->reqbuf, priv->nsg);
+#else
+ if (priv->dma_dir == DMA_TO_DEVICE) {
+ mcf_edma_sglist_config(chan, qc->sg, qc->n_elem, priv->dma_dir,
+ (dma_addr_t)
+ ((io_ata_virt2phys((void *)priv->fsl_ata_regs)) + 0x18),
+ MCF_EDMA_TCD_ATTR_SSIZE_32BIT
+ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
+ 4, 0, 8*4);
+ } else {
+
+ mcf_edma_sglist_config(chan, qc->sg, qc->n_elem, priv->dma_dir,
+ (dma_addr_t)
+ ((io_ata_virt2phys((void *)priv->fsl_ata_regs)) + 0x18),
+ MCF_EDMA_TCD_ATTR_SSIZE_32BIT
+ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
+ 0, 4, 8*4);
+ }
+
+#endif
+ priv->dma_done = 0;
+
+ DPRINTK("EXIT\n");
+
+}
+
+static void pata_fsl_bmdma_start(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_fsl_priv *priv = ap->host->private_data;
+ int chan;
+
+ /*
+ * Start the channel.
+ */
+ chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan : priv->dma_rchan;
+
+ mcf_edma_enable_transfer(chan);
+
+ ap->ops->sff_exec_command(ap, &qc->tf);
+}
+
+static void pata_fsl_bmdma_stop(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+/*
+ int chan;
+
+ chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan : priv->dma_rchan;
+ mcf_edma_stop_transfer(chan);
+*/
+/* do a dummy read as in ata_bmdma_stop */
+ ata_sff_dma_pause(ap);
+}
+
+static u8 pata_fsl_bmdma_status(struct ata_port *ap)
+{
+ struct pata_fsl_priv *priv = ap->host->private_data;
+
+ return priv->dma_done ? ATA_DMA_INTR : 0;
+}
+
+static void pata_fsl_dma_init(struct ata_port *ap)
+{
+ struct pata_fsl_priv *priv = ap->host->private_data;
+
+ priv->dma_rchan = -1;
+ priv->dma_wchan = -1;
+
+ priv->dma_rchan = mcf_edma_request_channel(MCF_EDMA_CHAN_ATA_RX,
+ dma_callback,
+ NULL, 0x6,
+ (void *)ap,
+ NULL,
+ "MCF ATA RX");
+ if (priv->dma_rchan < 0) {
+ dev_printk(KERN_ERR, ap->dev, "couldn't get RX DMA channel\n");
+ goto err_out;
+ }
+
+ priv->dma_wchan = mcf_edma_request_channel(MCF_EDMA_CHAN_ATA_TX,
+ dma_callback,
+ NULL, 0x6,
+ (void *)ap,
+ NULL,
+ "MCF ATA TX");
+ if (priv->dma_wchan < 0) {
+ dev_printk(KERN_ERR, ap->dev, "couldn't get TX DMA channel\n");
+ goto err_out;
+ }
+
+ dev_printk(KERN_ERR, ap->dev, "rchan=%d wchan=%d\n", priv->dma_rchan,
+ priv->dma_wchan);
+ return;
+
+err_out:
+ ap->mwdma_mask = 0;
+ ap->udma_mask = 0;
+ mcf_edma_free_channel(priv->dma_rchan, ap);
+ mcf_edma_free_channel(priv->dma_wchan, ap);
+ kfree(priv);
+}
+#endif /* CONFIG_FSL_PATA_USE_DMA */
+
+static void ata_dummy_noret(struct ata_port *ap) { return; }
+
+static struct scsi_host_template pata_fsl_sht = {
+ ATA_BMDMA_SHT(DRV_NAME),
+
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ .sg_tablesize = MAX_FSL_SG,
+ .dma_boundary = ATA_DMA_BOUNDARY,
+#endif
+};
+
+static struct ata_port_operations pata_fsl_port_ops = {
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ .inherits = &ata_bmdma_port_ops,
+#else
+ .inherits = &ata_sff_port_ops,
+#endif
+ .set_piomode = pata_fsl_set_piomode,
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ .set_dmamode = pata_fsl_set_dmamode,
+#endif
+ .cable_detect = ata_cable_40wire,
+
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ .bmdma_setup = pata_fsl_bmdma_setup,
+ .bmdma_start = pata_fsl_bmdma_start,
+#endif
+
+ .sff_data_xfer = ata_sff_data_xfer_noirq,
+ .qc_prep = ata_noop_qc_prep,
+
+ .port_start = pata_fsl_port_start,
+
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ .bmdma_stop = pata_fsl_bmdma_stop,
+ .bmdma_status = pata_fsl_bmdma_status,
+#endif
+};
+
+static void fsl_setup_port(struct ata_ioports *ioaddr)
+{
+ unsigned int shift = 2;
+
+ ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift);
+ ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift);
+ ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift);
+ ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift);
+ ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift);
+ ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift);
+ ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift);
+ ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift);
+ ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift);
+ ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift);
+}
+
+/**
+ * pata_fsl_probe - attach a platform interface
+ * @pdev: platform device
+ *
+ * Register a platform bus integrated ATA host controller
+ *
+ * The 3 platform device resources are used as follows:
+ *
+ * - I/O Base (IORESOURCE_MEM) virt. addr. of ATA controller regs
+ * - CTL Base (IORESOURCE_MEM) unused
+ * - IRQ (IORESOURCE_IRQ) platform IRQ assigned to ATA
+ *
+ */
+static int __devinit pata_fsl_probe(struct platform_device *pdev)
+{
+ struct resource *io_res;
+ struct ata_host *host;
+ struct ata_port *ap;
+ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+ pdev->dev.platform_data;
+ struct pata_fsl_priv *priv;
+ u8 *ata_regs;
+ int ret;
+
+ DPRINTK("ENTER\n");
+ /*
+ * Get an ata_host structure for this device
+ */
+ host = ata_host_alloc(&pdev->dev, 1);
+ if (!host)
+ return -ENOMEM;
+ ap = host->ports[0];
+ /*
+ * Allocate private data
+ */
+ priv = kzalloc(sizeof(struct pata_fsl_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ /* free(host); */
+ return -ENOMEM;
+ }
+ host->private_data = priv;
+
+ /*
+ * Set up resources
+ */
+ if (unlikely(pdev->num_resources != 3)) {
+ dev_err(&pdev->dev, "invalid number of resources\n");
+ return -EINVAL;
+ }
+
+ io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ata_regs = (u8 *)io_res->start;
+ priv->fsl_ata_regs = ata_regs;
+ ap->ioaddr.cmd_addr = (void *)(ata_regs + FSL_ATA_DRIVE_DATA);
+ ap->ioaddr.ctl_addr = (void *)(ata_regs + FSL_ATA_DRIVE_CONTROL);
+ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
+ ap->ops = &pata_fsl_port_ops;
+ ap->pio_mask = 0x3F;
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ ap->mwdma_mask = 0x07;
+ ap->udma_mask = 0x1F;
+/* ap->udma_mask = plat->udma_mask; */
+/* pata_fsl_sht.sg_tablesize = plat->max_sg; */
+#else
+ ap->mwdma_mask = 0x00;
+ ap->udma_mask = 0x00;
+#endif
+ fsl_setup_port(&ap->ioaddr);
+
+ /*
+ * Do platform-specific initialization (e.g. allocate pins,
+ * turn on clock). After this call it is assumed that
+ * plat->get_clk_rate() can be called to calculate
+ * timing.
+ */
+ if (plat->init && plat->init(pdev)) {
+ /* REVISIT: don't leak what ata_host_alloc() allocated */
+ return -ENODEV;
+ }
+
+ /* Deassert the reset bit to enable the interface */
+ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL);
+
+ /* Set initial timing and mode */
+ set_ata_bus_timing(XFER_PIO_4, pdev);
+
+#ifdef CONFIG_FSL_PATA_USE_DMA
+ /* get DMA ready */
+ pata_fsl_dma_init(ap);
+#endif
+
+ /*
+ * Enable the ATA INTRQ interrupt from the bus, but
+ * only allow the CPU to see it (INTRQ2) at this point.
+ * INTRQ1, which goes to the DMA, will be enabled later.
+ */
+#if 0
+ __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN);
+#else
+ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN);
+#endif
+
+ /* activate */
+ ret = ata_host_activate(host, platform_get_irq(pdev, 0),
+ ata_sff_interrupt, 0, &pata_fsl_sht);
+ DPRINTK("EXIT ret=%d\n", ret);
+ return ret;
+}
+
+/**
+ * pata_fsl_remove - unplug a platform interface
+ * @pdev: platform device
+ *
+ * A platform bus ATA device has been unplugged. Perform the needed
+ * cleanup. Also called on module unload for any active devices.
+ */
+static int __devexit pata_fsl_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ata_host *host = dev_get_drvdata(dev);
+ struct pata_fsl_priv *priv = host->private_data;
+ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+ pdev->dev.platform_data;
+ u8 *ata_regs = priv->fsl_ata_regs;
+
+#if 0
+ __raw_writel(0, ata_regs + FSL_ATA_INT_EN); /* Disable interrupts */
+#else
+ WRITE_ATA8(0, FSL_ATA_INT_EN); /* Disable interrupts */
+#endif
+
+ ata_host_detach(host);
+
+ if (plat->exit)
+ plat->exit();
+
+ kfree(priv);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int pata_fsl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ struct pata_fsl_priv *priv = host->private_data;
+ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+ pdev->dev.platform_data;
+ u8 *ata_regs = priv->fsl_ata_regs;
+
+ /* Disable interrupts. */
+#if 0
+ __raw_writel(0, ata_regs + FSL_ATA_INT_EN);
+#else
+ WRITE_ATA8(0, FSL_ATA_INT_EN);
+#endif
+
+ if (plat->exit)
+ plat->exit();
+
+ return 0;
+}
+
+static int pata_fsl_resume(struct platform_device *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ struct pata_fsl_priv *priv = host->private_data;
+ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+ pdev->dev.platform_data;
+ u8 *ata_regs = priv->fsl_ata_regs;
+
+ if (plat->init && plat->init(pdev))
+ return -ENODEV;
+ /* Deassert the reset bit to enable the interface */
+#if 0
+ __raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL);
+#else
+ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL);
+#endif
+
+ /* Set initial timing and mode */
+ set_ata_bus_timing(XFER_PIO_4, pdev);
+
+ /*
+ * Enable hardware interrupts.
+ */
+#if 0
+ __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN);
+#else
+ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN);
+#endif
+
+ return 0;
+}
+#endif
+
+static struct platform_driver pata_fsl_driver = {
+ .probe = pata_fsl_probe,
+ .remove = __devexit_p(pata_fsl_remove),
+#ifdef CONFIG_PM
+ .suspend = pata_fsl_suspend,
+ .resume = pata_fsl_resume,
+#endif
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pata_fsl_init(void)
+{
+ int ret;
+
+ DPRINTK("ENTER\n");
+ ret = platform_driver_register(&pata_fsl_driver);
+ DPRINTK("EXIT ret=%d\n", ret);
+ return ret;
+}
+
+static void __exit pata_fsl_exit(void)
+{
+ platform_driver_unregister(&pata_fsl_driver);
+}
+module_init(pata_fsl_init);
+module_exit(pata_fsl_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("low-level driver for Freescale ATA");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);

1287
target/linux/coldfire/patches/038-Add-PCI-Framebuffer-support-for-Silicon-Motion-s-Lyn.patch Normal file
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3051
target/linux/coldfire/patches/039-Add-PCI-bus-driver-for-M54455EVB-and-M547X_8X.patch Normal file
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7007
target/linux/coldfire/patches/040-Add-USB-support-for-MCF5445x-and-MCF54418.patch Normal file
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25
target/linux/coldfire/patches/041-Fix-CAU-driver-bug-for-SHA1-digest-algorithm.patch Normal file
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@ -0,0 +1,25 @@
From da0df827fa9600b3104d4b8d8cc3edbdd5a0849b Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:53 +0800
Subject: [PATCH 41/52] Fix CAU driver bug for SHA1 digest algorithm
Make the compiler to never inline a particular member
function.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/crypto/mcfcau-sha1.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
--- a/drivers/crypto/mcfcau-sha1.c
+++ b/drivers/crypto/mcfcau-sha1.c
@@ -60,7 +60,8 @@ struct mcfcau_sha1_ctx {
u8 buffer[64];
};
-static void mcfcau_sha1_transform(__u32 *digest, const char *in, __u32 *W)
+static noinline void mcfcau_sha1_transform(__u32 *digest,
+ const char *in, __u32 *W)
{
int i;
u32 *tmp_p;

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