ramips: gpio-ralink: use ngpios, not ralink,num-gpios

DTS properties that match *-gpios are treated specially.

Use ngpios instead, as most GPIO drivers upstream do.

Fixes 5.10 DTS errors such as:
  OF: /palmbus@300000/gpio@600: could not find phandle

Fixes DTC warnings such as:
  Warning (gpios_property): /palmbus@300000/gpio@600:ralink,num-gpios:
  Could not get phandle node for (cell 0)

Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Ilya Lipnitskiy 2021-04-05 22:53:46 -07:00 committed by Chuanhong Guo
parent 5f07c579f8
commit 85ca6923bc
13 changed files with 51 additions and 29 deletions

View File

@ -117,8 +117,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,num-gpios = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -134,8 +134,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,num-gpios = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -153,8 +153,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,num-gpios = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -172,8 +172,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <1>;
ralink,gpio-base = <72>;
ralink,num-gpios = <1>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

View File

@ -102,8 +102,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,num-gpios = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -119,8 +119,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,num-gpios = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -138,8 +138,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,num-gpios = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -157,8 +157,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <1>;
ralink,gpio-base = <72>;
ralink,num-gpios = <1>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

View File

@ -81,8 +81,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,num-gpios = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -95,8 +95,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,num-gpios = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -111,8 +111,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,num-gpios = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

View File

@ -110,8 +110,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,num-gpios = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -130,8 +130,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,num-gpios = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -146,8 +146,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <12>;
ralink,gpio-base = <40>;
ralink,num-gpios = <12>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

View File

@ -108,8 +108,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,num-gpios = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -127,8 +127,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,num-gpios = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -143,8 +143,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
ralink,gpio-base = <40>;
ralink,num-gpios = <6>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

View File

@ -117,8 +117,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <0>;
ralink,num-gpios = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -131,8 +131,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
ralink,gpio-base = <24>;
ralink,num-gpios = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -147,8 +147,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ralink,gpio-base = <40>;
ralink,num-gpios = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
@ -163,8 +163,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
ralink,gpio-base = <72>;
ralink,num-gpios = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

View File

@ -117,8 +117,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <22>;
ralink,gpio-base = <0>;
ralink,num-gpios = <22>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
@ -134,8 +134,8 @@
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
ralink,gpio-base = <22>;
ralink,num-gpios = <6>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];

View File

@ -29,7 +29,7 @@ Cc: linux-gpio@vger.kernel.org
+- reg : Physical base address and length of the controller's registers
+- interrupt-parent: phandle to the INTC device node
+- interrupts : Specify the INTC interrupt number
+- ralink,num-gpios : Specify the number of GPIOs
+- ngpios : Specify the number of GPIOs
+- ralink,register-map : The register layout depends on the GPIO bank and actual
+ SoC type. Register offsets need to be in this order.
+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
@ -50,8 +50,8 @@ Cc: linux-gpio@vger.kernel.org
+ interrupt-parent = <&intc>;
+ interrupts = <6>;
+
+ ngpios = <24>;
+ ralink,gpio-base = <0>;
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];

View File

@ -357,7 +357,7 @@ Cc: linux-gpio@vger.kernel.org
+ return -EINVAL;
+ }
+
+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
+ ngpio = of_get_property(np, "ngpios", NULL);
+ if (!ngpio) {
+ dev_err(&pdev->dev, "failed to read number of pins\n");
+ return -EINVAL;

View File

@ -0,0 +1,11 @@
--- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
+++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
@@ -354,7 +354,7 @@ static int rt2880_pinmux_probe(struct pl
if (!of_device_is_available(np))
continue;
- ngpio = of_get_property(np, "ralink,num-gpios", NULL);
+ ngpio = of_get_property(np, "ngpios", NULL);
gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
if (!ngpio || !gpiobase) {
dev_err(&pdev->dev, "failed to load chip info\n");

View File

@ -29,7 +29,7 @@ Cc: linux-gpio@vger.kernel.org
+- reg : Physical base address and length of the controller's registers
+- interrupt-parent: phandle to the INTC device node
+- interrupts : Specify the INTC interrupt number
+- ralink,num-gpios : Specify the number of GPIOs
+- ngpios : Specify the number of GPIOs
+- ralink,register-map : The register layout depends on the GPIO bank and actual
+ SoC type. Register offsets need to be in this order.
+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
@ -50,8 +50,8 @@ Cc: linux-gpio@vger.kernel.org
+ interrupt-parent = <&intc>;
+ interrupts = <6>;
+
+ ngpios = <24>;
+ ralink,gpio-base = <0>;
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];

View File

@ -357,7 +357,7 @@ Cc: linux-gpio@vger.kernel.org
+ return -EINVAL;
+ }
+
+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
+ ngpio = of_get_property(np, "ngpios", NULL);
+ if (!ngpio) {
+ dev_err(&pdev->dev, "failed to read number of pins\n");
+ return -EINVAL;

View File

@ -0,0 +1,11 @@
--- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
+++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
@@ -354,7 +354,7 @@ static int rt2880_pinmux_probe(struct pl
if (!of_device_is_available(np))
continue;
- ngpio = of_get_property(np, "ralink,num-gpios", NULL);
+ ngpio = of_get_property(np, "ngpios", NULL);
gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
if (!ngpio || !gpiobase) {
dev_err(&pdev->dev, "failed to load chip info\n");