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ipq806x: add GSBI1 node to DTSI 

IPQ806x series also has a GSBI1 with UART and I2C peripherals, so lets add the node for it.

Its needed for Edgecore ECW5410 which uses the UART from GSBI1 as second UART for Bluetooth.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This commit is contained in:
Robert Marko 2020-05-18 12:28:37 +02:00 committed by John Crispin
parent 6133ac8e99
commit 811af0d98a
1 changed files with 46 additions and 0 deletions
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46
target/linux/ipq806x/patches-5.4/851-add-gsbi1-dts.patch Normal file
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@ -0,0 +1,46 @@
Index: linux-5.4.65/arch/arm/boot/dts/qcom-ipq8064.dtsi
===================================================================
--- linux-5.4.65.orig/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ linux-5.4.65/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -865,6 +865,41 @@
reg = <0x12100000 0x10000>;
};
+ gsbi1: gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <1>;
+ reg = <0x12440000 0x100>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi1_serial: serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ gsbi1_i2c: i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;