bcm53xx: backport clk driver fix for DT nodes names
It allows dropping downstream patch renaming DT nodes. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki
parent
c5e167e0d6
commit
77d9cce604
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@ -0,0 +1,72 @@
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From 1b24a132eba7a1c19475ba2510ec1c00af3ff914 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <f.fainelli@gmail.com>
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Date: Mon, 5 Sep 2022 09:15:03 -0700
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Subject: [PATCH] clk: iproc: Do not rely on node name for correct PLL setup
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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After commit 31fd9b79dc58 ("ARM: dts: BCM5301X: update CRU block
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description") a warning from clk-iproc-pll.c was generated due to a
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duplicate PLL name as well as the console stopped working. Upon closer
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inspection it became clear that iproc_pll_clk_setup() used the Device
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Tree node unit name as an unique identifier as well as a parent name to
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parent all clocks under the PLL.
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BCM5301X was the first platform on which that got noticed because of the
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DT node unit name renaming but the same assumptions hold true for any
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user of the iproc_pll_clk_setup() function.
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The first 'clock-output-names' property is always guaranteed to be
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unique as well as providing the actual desired PLL clock name, so we
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utilize that to register the PLL and as a parent name of all children
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clock.
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Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Acked-by: Rafał Miłecki <rafal@milecki.pl>
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Link: https://lore.kernel.org/r/20220905161504.1526-1-f.fainelli@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/bcm/clk-iproc-pll.c | 12 ++++++++----
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1 file changed, 8 insertions(+), 4 deletions(-)
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--- a/drivers/clk/bcm/clk-iproc-pll.c
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+++ b/drivers/clk/bcm/clk-iproc-pll.c
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@@ -736,6 +736,7 @@ void iproc_pll_clk_setup(struct device_n
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const char *parent_name;
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struct iproc_clk *iclk_array;
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struct clk_hw_onecell_data *clk_data;
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+ const char *clk_name;
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if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl))
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return;
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@@ -783,7 +784,12 @@ void iproc_pll_clk_setup(struct device_n
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iclk = &iclk_array[0];
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iclk->pll = pll;
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- init.name = node->name;
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+ ret = of_property_read_string_index(node, "clock-output-names",
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+ 0, &clk_name);
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+ if (WARN_ON(ret))
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+ goto err_pll_register;
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+
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+ init.name = clk_name;
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init.ops = &iproc_pll_ops;
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init.flags = 0;
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parent_name = of_clk_get_parent_name(node, 0);
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@@ -803,13 +809,11 @@ void iproc_pll_clk_setup(struct device_n
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goto err_pll_register;
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clk_data->hws[0] = &iclk->hw;
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+ parent_name = clk_name;
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/* now initialize and register all leaf clocks */
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for (i = 1; i < num_clks; i++) {
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- const char *clk_name;
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-
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memset(&init, 0, sizeof(init));
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- parent_name = node->name;
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ret = of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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@ -1,62 +0,0 @@
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Tue, 23 Nov 2021 13:13:05 +0100
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Subject: [PATCH] ARM: dts: BCM5301X: Switch back to old clock nodes names
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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First of all using the same node name prefix resulted in trying to
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register 2 clocks under the same "clock-controller" name:
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[ 0.000000] __clk_core_init: clk clock-controller already initialized
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[ 0.000000] ------------[ cut here ]------------
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[ 0.000000] WARNING: CPU: 0 PID: 0 at drivers/clk/bcm/clk-iproc-pll.c:802 iproc_pll_clk_setup+0x4c8/0x4f4
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[ 0.000000] Modules linked in:
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[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.80 #0
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[ 0.000000] Hardware name: BCM5301X
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[ 0.000000] [<c0108410>] (unwind_backtrace) from [<c0104bc4>] (show_stack+0x10/0x14)
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[ 0.000000] [<c0104bc4>] (show_stack) from [<c03dca28>] (dump_stack+0x94/0xa8)
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[ 0.000000] [<c03dca28>] (dump_stack) from [<c0118440>] (__warn+0xb8/0x114)
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[ 0.000000] [<c0118440>] (__warn) from [<c0118504>] (warn_slowpath_fmt+0x68/0x78)
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[ 0.000000] [<c0118504>] (warn_slowpath_fmt) from [<c043281c>] (iproc_pll_clk_setup+0x4c8/0x4f4)
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[ 0.000000] [<c043281c>] (iproc_pll_clk_setup) from [<c0818c04>] (nsp_genpll_clk_init+0x30/0x38)
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[ 0.000000] [<c0818c04>] (nsp_genpll_clk_init) from [<c0818634>] (of_clk_init+0x118/0x1f8)
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[ 0.000000] [<c0818634>] (of_clk_init) from [<c08039b0>] (time_init+0x24/0x30)
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[ 0.000000] [<c08039b0>] (time_init) from [<c0800d14>] (start_kernel+0x398/0x50c)
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[ 0.000000] [<c0800d14>] (start_kernel) from [<00000000>] (0x0)
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[ 0.000000] ---[ end trace fe236bfe9559ee50 ]---
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Secondly using any other names than "lcpll0" and "genpll" breaks output
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clocks:
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$ cat /sys/kernel/debug/clk/usbclk/clk_rate
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0
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For some reason iproc_clk_recalc_rate() gets called with "parent_rate"
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argument 0 whenever clocks aren't named "lcpll0" and "genpll".
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -421,7 +421,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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- lcpll0: clock-controller@100 {
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+ lcpll0: lcpll0@100 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-lcpll0";
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reg = <0x100 0x14>;
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@@ -430,7 +430,7 @@
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"sdio", "ddr_phy";
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};
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- genpll: clock-controller@140 {
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+ genpll: genpll@140 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-genpll";
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reg = <0x140 0x24>;
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@ -0,0 +1,72 @@
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From 1b24a132eba7a1c19475ba2510ec1c00af3ff914 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <f.fainelli@gmail.com>
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Date: Mon, 5 Sep 2022 09:15:03 -0700
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Subject: [PATCH] clk: iproc: Do not rely on node name for correct PLL setup
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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After commit 31fd9b79dc58 ("ARM: dts: BCM5301X: update CRU block
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description") a warning from clk-iproc-pll.c was generated due to a
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duplicate PLL name as well as the console stopped working. Upon closer
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inspection it became clear that iproc_pll_clk_setup() used the Device
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Tree node unit name as an unique identifier as well as a parent name to
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parent all clocks under the PLL.
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BCM5301X was the first platform on which that got noticed because of the
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DT node unit name renaming but the same assumptions hold true for any
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user of the iproc_pll_clk_setup() function.
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The first 'clock-output-names' property is always guaranteed to be
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unique as well as providing the actual desired PLL clock name, so we
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utilize that to register the PLL and as a parent name of all children
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clock.
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Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Acked-by: Rafał Miłecki <rafal@milecki.pl>
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Link: https://lore.kernel.org/r/20220905161504.1526-1-f.fainelli@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/bcm/clk-iproc-pll.c | 12 ++++++++----
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1 file changed, 8 insertions(+), 4 deletions(-)
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--- a/drivers/clk/bcm/clk-iproc-pll.c
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+++ b/drivers/clk/bcm/clk-iproc-pll.c
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@@ -736,6 +736,7 @@ void iproc_pll_clk_setup(struct device_n
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const char *parent_name;
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struct iproc_clk *iclk_array;
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struct clk_hw_onecell_data *clk_data;
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+ const char *clk_name;
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if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl))
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return;
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@@ -783,7 +784,12 @@ void iproc_pll_clk_setup(struct device_n
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iclk = &iclk_array[0];
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iclk->pll = pll;
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- init.name = node->name;
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+ ret = of_property_read_string_index(node, "clock-output-names",
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+ 0, &clk_name);
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+ if (WARN_ON(ret))
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+ goto err_pll_register;
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+
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+ init.name = clk_name;
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init.ops = &iproc_pll_ops;
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init.flags = 0;
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parent_name = of_clk_get_parent_name(node, 0);
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@@ -803,13 +809,11 @@ void iproc_pll_clk_setup(struct device_n
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goto err_pll_register;
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clk_data->hws[0] = &iclk->hw;
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+ parent_name = clk_name;
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/* now initialize and register all leaf clocks */
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for (i = 1; i < num_clks; i++) {
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- const char *clk_name;
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-
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memset(&init, 0, sizeof(init));
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- parent_name = node->name;
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ret = of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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@ -1,62 +0,0 @@
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Tue, 23 Nov 2021 13:13:05 +0100
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Subject: [PATCH] ARM: dts: BCM5301X: Switch back to old clock nodes names
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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First of all using the same node name prefix resulted in trying to
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register 2 clocks under the same "clock-controller" name:
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[ 0.000000] __clk_core_init: clk clock-controller already initialized
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[ 0.000000] ------------[ cut here ]------------
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[ 0.000000] WARNING: CPU: 0 PID: 0 at drivers/clk/bcm/clk-iproc-pll.c:802 iproc_pll_clk_setup+0x4c8/0x4f4
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[ 0.000000] Modules linked in:
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[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.80 #0
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[ 0.000000] Hardware name: BCM5301X
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[ 0.000000] [<c0108410>] (unwind_backtrace) from [<c0104bc4>] (show_stack+0x10/0x14)
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[ 0.000000] [<c0104bc4>] (show_stack) from [<c03dca28>] (dump_stack+0x94/0xa8)
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[ 0.000000] [<c03dca28>] (dump_stack) from [<c0118440>] (__warn+0xb8/0x114)
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[ 0.000000] [<c0118440>] (__warn) from [<c0118504>] (warn_slowpath_fmt+0x68/0x78)
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[ 0.000000] [<c0118504>] (warn_slowpath_fmt) from [<c043281c>] (iproc_pll_clk_setup+0x4c8/0x4f4)
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[ 0.000000] [<c043281c>] (iproc_pll_clk_setup) from [<c0818c04>] (nsp_genpll_clk_init+0x30/0x38)
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[ 0.000000] [<c0818c04>] (nsp_genpll_clk_init) from [<c0818634>] (of_clk_init+0x118/0x1f8)
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[ 0.000000] [<c0818634>] (of_clk_init) from [<c08039b0>] (time_init+0x24/0x30)
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[ 0.000000] [<c08039b0>] (time_init) from [<c0800d14>] (start_kernel+0x398/0x50c)
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[ 0.000000] [<c0800d14>] (start_kernel) from [<00000000>] (0x0)
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[ 0.000000] ---[ end trace fe236bfe9559ee50 ]---
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Secondly using any other names than "lcpll0" and "genpll" breaks output
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clocks:
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$ cat /sys/kernel/debug/clk/usbclk/clk_rate
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0
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For some reason iproc_clk_recalc_rate() gets called with "parent_rate"
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argument 0 whenever clocks aren't named "lcpll0" and "genpll".
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -421,7 +421,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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- lcpll0: clock-controller@100 {
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+ lcpll0: lcpll0@100 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-lcpll0";
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reg = <0x100 0x14>;
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@@ -430,7 +430,7 @@
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"sdio", "ddr_phy";
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};
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- genpll: clock-controller@140 {
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+ genpll: genpll@140 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-genpll";
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reg = <0x140 0x24>;
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