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mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2024-06-15 19:53:59 +02:00

lantiq: dts: assign the NAND pins to the nand-controller node

Assign the NAND pins to the NAND controller node instead of using pin
hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.

While here, define all NAND pins (CLE, ALE, read/RD, ready busy/RDY and
CE/CS1). This means that the pinctrl subsystem knows that these pins are
in use and cannot be re-assigned as GPIOs for example.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This commit is contained in:
Martin Blumenstingl 2019-07-08 12:10:12 +02:00 committed by Adrian Schmutzler
parent edb0a936f0
commit 7298c25f74
16 changed files with 112 additions and 85 deletions

View File

@ -108,19 +108,6 @@
pinctrl-0 = <&state_default>;
state_default: pinmux {
nand_out {
lantiq,groups = "nand cle", "nand ale";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
nand_cs1 {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
exin {
lantiq,groups = "exin1";
lantiq,function = "exin";
@ -209,6 +196,9 @@
reg = <1 0x0 0x2000000 >;
req-mask = <0x1>; /* PCI request lines to mask during NAND access */
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

View File

@ -109,20 +109,6 @@
pinctrl-0 = <&state_default>;
state_default: pinmux {
nand_out {
lantiq,groups = "nand cle", "nand ale";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
nand_cs1 {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
pci_in {
lantiq,groups = "req1";
lantiq,function = "pci";
@ -158,6 +144,9 @@
reg = <1 0x0 0x2000000 >;
req-mask = <0x1>; /* PCI request lines to mask during NAND access */
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

View File

@ -214,19 +214,6 @@
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
nand_out {
lantiq,groups = "nand cle", "nand ale";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
nand_cs1 {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
};
};
@ -236,6 +223,10 @@
lantiq,cs = <1>;
bank-width = <2>;
reg = <0x1 0x0 0x2000000>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
nand-on-flash-bbt;
nand-ecc-strength = <3>;
nand-ecc-step-size = <256>;

View File

@ -193,18 +193,12 @@
lantiq,groups = "stp";
lantiq,function = "stp";
};
nand {
lantiq,groups = "nand cle", "nand ale",
"nand rd", "nand rdy";
lantiq,function = "ebu";
};
pci {
lantiq,groups = "gnt1", "req1";
lantiq,function = "pci";
};
conf_out {
lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
"io4", "io5", "io6", /* stp */
lantiq,pins = "io4", "io5", "io6", /* stp */
"io21",
"io33";
lantiq,open-drain;
@ -217,8 +211,7 @@
lantiq,output = <1>;
};
conf_in {
lantiq,pins = "io39", /* exin3 */
"io48"; /* nand rdy */
lantiq,pins = "io39"; /* exin3 */
lantiq,pull = <2>;
};
};

View File

@ -19,6 +19,9 @@
bank-width = <2>;
reg = <0 0x0 0x2000000>;
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

View File

@ -13,6 +13,9 @@
bank-width = <2>;
reg = <1 0x0 0x2000000>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
nand-ecc-mode = "soft";
nand-ecc-strength = <3>;
nand-ecc-step-size = <256>;

View File

@ -13,6 +13,9 @@
bank-width = <2>;
reg = <1 0x0 0x2000000>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
nand-ecc-mode = "on-die";
partitions {

View File

@ -193,13 +193,6 @@
pinctrl-0 = <&state_default>;
state_default: pinmux {
nand {
lantiq,groups = "nand cle", "nand ale",
"nand rd", "nand cs1", "nand rdy";
lantiq,function = "ebu";
lantiq,pull = <1>;
};
phy-rst {
lantiq,pins = "io37", "io44";
lantiq,pull = <0>;

View File

@ -36,12 +36,6 @@
};
&state_default {
nand {
lantiq,groups = "nand ale", "nand cle",
"nand cs1", "nand rd", "nand rdy";
lantiq,function = "ebu";
};
pcie-rst {
lantiq,pins = "io21";
lantiq,open-drain = <1>;
@ -85,6 +79,10 @@
lantiq,cs1 = <1>;
bank-width = <1>;
reg = <1 0x0 0x2000000>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
nand-ecc-mode = "on-die";
partitions {

View File

@ -89,6 +89,9 @@
reg = <0 0x0 0x2000000>;
lantiq,cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
@ -172,16 +175,6 @@
lantiq,open-drain = <1>;
lantiq,output = <1>;
};
nand-mux {
lantiq,groups = "nand cle", "nand ale",
"nand rd", "nand cs1",
"nand rdy";
lantiq,function = "ebu";
};
nand-pins {
lantiq,pins = "io13", "io24", "io49";
lantiq,pull = <1>;
};
};
};

View File

@ -30,6 +30,9 @@
bank-width = <2>;
reg = <0 0x0 0x2000000>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

View File

@ -21,6 +21,9 @@
bank-width = <2>;
reg = <0 0x0 0x800000>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

View File

@ -242,19 +242,6 @@
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
nand_out {
lantiq,groups = "nand cle", "nand ale";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
nand_cs1 {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
};
};

View File

@ -178,6 +178,32 @@
};
};
nand_pins: nand {
mux-0 {
lantiq,groups = "nand cle", "nand ale",
"nand rd";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
mux-1 {
lantiq,groups = "nand rdy";
lantiq,function = "ebu";
lantiq,output = <0>;
lantiq,pull = <2>;
};
};
nand_cs1_pins: nand-cs1 {
mux {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
};
spi_pins: spi {
mux-0 {
lantiq,groups = "spi_di";

View File

@ -162,6 +162,32 @@
#gpio-cells = <2>;
gpio-controller;
reg = <0xe100b10 0xa0>;
nand_pins: nand {
mux-0 {
lantiq,groups = "nand cle", "nand ale",
"nand rd";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
mux-1 {
lantiq,groups = "nand rdy";
lantiq,function = "ebu";
lantiq,output = <0>;
lantiq,pull = <2>;
};
};
nand_cs1_pins: nand-cs1 {
mux {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
};
};
asc1: serial@e100c00 {

View File

@ -220,6 +220,32 @@
};
};
nand_pins: nand {
mux-0 {
lantiq,groups = "nand cle", "nand ale",
"nand rd";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
mux-1 {
lantiq,groups = "nand rdy";
lantiq,function = "ebu";
lantiq,output = <0>;
lantiq,pull = <2>;
};
};
nand_cs1_pins: nand-cs1 {
mux {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
};
spi_pins: spi {
mux-0 {
lantiq,groups = "spi_di";