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uboot-sunxi: Update to version 2018.11 

This updates the uboot for the sunxi target to version 2018.11
The removed patches are applied upstream and not needed any more.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Hauke Mehrtens 2018-12-19 12:53:52 +01:00
parent 900c6b1a42
commit 4ed05b805b
12 changed files with 17 additions and 481 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
package/boot/uboot-sunxi/Makefile
View File

@ -9,9 +9,9 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2018.05
PKG_VERSION:=2018.11
PKG_HASH:=4da13c2a6139a78cc08608f21fd4741db27eda336cfad7ab8264fda923b9c048
PKG_HASH:=737c93f2ea03fec669e840dbee32bcf6238e6924ff5f20e4f1c472ee24e5d37e
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>

10
package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -290,6 +290,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
@@ -306,6 +306,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
@ -10,8 +10,8 @@
sun6i-a31s-inet-q972.dtb \
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -679,6 +679,13 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
@@ -641,6 +641,13 @@
function = "lcd0";
};
+ i2c3_pins_a: i2c3@0 {
@ -22,7 +22,7 @@
+ };
+
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2",
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
--- /dev/null
+++ b/arch/arm/dts/sun6i-a31-pangolin.dts
@ -360,7 +360,7 @@
+CONFIG_SUNXI_SPI=y
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -836,6 +836,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
@@ -872,6 +872,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
Set the SCL pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.

4
package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch
View File

@ -2,9 +2,9 @@
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -22,6 +22,7 @@ CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
@@ -25,6 +25,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_SUN7I_GMAC=y
+CONFIG_GMAC_TX_DELAY=1
CONFIG_AXP_ALDO3_VOLT=2800

2
package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch
View File

@ -6,7 +6,7 @@ Subject: sun6i: define alternate-function for UART2 on GPG
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -185,6 +185,7 @@ enum sunxi_gpio_number {
@@ -186,6 +186,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN6I_GPG_TWI3 2

4
package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch
View File

@ -6,7 +6,7 @@ Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -123,6 +123,10 @@ static int gpio_init(void)
@@ -127,6 +127,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
@ -19,7 +19,7 @@ Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -256,6 +256,8 @@ extern int soft_i2c_gpio_scl;
@@ -258,6 +258,8 @@ extern int soft_i2c_gpio_scl;
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"

2
package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch
View File

@ -6,7 +6,7 @@ Subject: ARM: sunxi: Make CONS_INDEX configurable
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -500,6 +500,14 @@ config SYS_BOARD
@@ -535,6 +535,14 @@ config SYS_BOARD
config SYS_SOC
default "sunxi"

2
package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch
View File

@ -17,7 +17,7 @@ Cc: Simon Glass <sjg@chromium.org>
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -649,9 +649,14 @@ static int fit_handle_file(struct image_
@@ -656,9 +656,14 @@ static int fit_handle_file(struct image_
}
*cmd = '\0';
} else if (params->datafile) {

4
package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch
View File

@ -12,7 +12,7 @@ old way of generating images.
--- a/Makefile
+++ b/Makefile
@@ -1215,8 +1215,10 @@ endif
@@ -1255,8 +1255,10 @@ endif
ifneq ($(CONFIG_ARCH_SUNXI),)
ifeq ($(CONFIG_ARM64),)
@ -27,7 +27,7 @@ old way of generating images.
$(call if_changed,cat)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -711,7 +711,6 @@ config ARCH_SOCFPGA
@@ -820,7 +820,6 @@ config ARCH_SOCFPGA
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"

2
package/boot/uboot-sunxi/patches/221-compatible-old-dtc.patch
View File

@ -7,7 +7,7 @@ dtc from kernel 4.9.
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -172,6 +172,11 @@ ld-version = $(shell $(LD) --version | $
@@ -173,6 +173,11 @@ ld-version = $(shell $(LD) --version | $
# Usage: $(call ld-ifversion, -ge, 22252, y)
ld-ifversion = $(shell [ $(ld-version) $(1) $(2) ] && echo $(3) || echo $(4))

63
package/boot/uboot-sunxi/patches/310-sunxi-h3-Sync-OTG-and-HCI-nodes-from-Linux-DT.patch
View File

@ -1,63 +0,0 @@
From 96c04aab58e351fa9ed7e95783018d6dbf60768f Mon Sep 17 00:00:00 2001
From: Jun Nie <jun.nie@linaro.org>
Date: Mon, 7 May 2018 13:03:40 +0530
Subject: sunxi: h3: Sync OTG and HCI nodes from Linux DT
Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
---
arch/arm/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -219,6 +219,19 @@
#size-cells = <0>;
};
+ usb_otg: usb@1c19000 {
+ compatible = "allwinner,sun8i-h3-musb";
+ reg = <0x01c19000 0x400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-h3-usb-phy";
reg = <0x01c19400 0x2c>,
@@ -251,6 +264,25 @@
#phy-cells = <1>;
};
+ ehci0: usb@1c1a000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@1c1a400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;

179
package/boot/uboot-sunxi/patches/320-sunxi-Add-support-for-Orange-Pi-R1.patch
View File

@ -1,179 +0,0 @@
From fd3736abbe57a819312c8df96d14ec396b074581 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Tue, 26 Sep 2017 22:16:59 +0200
Subject: sun8i: h2: Add initial Orange Pi R1
Orange Pi R1 is an open-source single-board computer using the
Allwinner H2+ SOC.
H2+ Orange Pi R1 has
- Quad-core Cortex-A7
- 256MB DDR3
- micrSD slot
- 128MBit SPI Nor flash
- Debug TTL UART
- 100MBit/s Ethernet (H2+)
- 100MBit/s Ethernet (RTL8152B)
- Wifi (RTL8189ETV)
- USB 2.0 OTG + power supply
This board is very similar to the Orange Pi Zero.
The device tree file is copied from the Linux kernel 4.18.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts | 101 +++++++++++++++++++++++++++++
board/sunxi/MAINTAINERS | 5 ++
configs/orangepi_r1_defconfig | 16 +++++
4 files changed, 123 insertions(+)
create mode 100644 arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts
create mode 100644 configs/orangepi_r1_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -350,6 +350,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-tbs-a711.dts
dtb-$(CONFIG_MACH_SUN8I_H3) += \
+ sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* Orange Pi R1 is based on Orange Pi Zero design */
+#include "sun8i-h2-plus-orangepi-zero.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1";
+ compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
+
+ /delete-node/ reg_vcc_wifi;
+
+ /*
+ * Ths pin of this regulator is the same with the Wi-Fi extra
+ * regulator on the original Zero. However it's used for USB
+ * Ethernet rather than the Wi-Fi now.
+ */
+ reg_vcc_usb_eth: reg-vcc-usb-ethernet {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-usb-ethernet";
+ enable-active-high;
+ gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ aliases {
+ ethernet1 = &rtl8189etv;
+ };
+};
+
+/*
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
+ };
+};
+*/
+
+&ohci1 {
+ /*
+ * RTL8152B USB-Ethernet adapter is connected to USB1,
+ * and it's a USB 2.0 device. So the OHCI1 controller
+ * can be left disabled.
+ */
+ status = "disabled";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc_usb_eth>;
+};
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -342,6 +342,11 @@ M: Jagan Teki <jagan@amarulasolutions.co
S: Maintained
F: configs/orangepi_prime_defconfig
+ORANGEPI R1 BOARD
+M: Hauke Mehrtens <hauke@hauke-m.de>
+S: Maintained
+F: configs/orangepi_r1_defconfig
+
PINE64 BOARDS
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
--- /dev/null
+++ b/configs/orangepi_r1_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

222
package/boot/uboot-sunxi/patches/400-ARM-dts-orange-pi-zero-plus.patch
View File

@ -1,222 +0,0 @@
From fd576a3c594ee2356b50a0738403e5cef094935a Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 9 Jun 2018 15:16:42 +0200
Subject: sun50i: h5: Add initial Orange Pi Zero Plus support
Orange Pi Zero Plus is an open-source single-board computer
using the Allwinner H5 SOC.
H5 Orangepi Zero Plus has
- Quad-core Cortex-A53
- 512MB DDR3
- micrSD slot
- 16MBit SPI Nor flash
- Debug TTL UART
- 1GBit/s Ethernet (RTL8211E)
- Wifi (RTL8189FTV)
- USB 2.0 Host
- USB 2.0 OTG + power supply
The device tree file is copied from the Linux kernel 4.18.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts | 145 ++++++++++++++++++++++++++
board/sunxi/MAINTAINERS | 5 +
configs/orangepi_zero_plus_defconfig | 16 +++
4 files changed, 167 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts
create mode 100644 configs/orangepi_zero_plus_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -372,6 +372,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
+ sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi Zero Plus";
+ compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189ftv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ /*
+ * Explicitly define the sdio device, so that we can add an ethernet
+ * alias for it (which e.g. makes u-boot set a mac-address).
+ */
+ rtl8189ftv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+/*
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+*/
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A ports' VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ status = "okay";
+};
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -327,6 +327,11 @@ M: Icenowy Zheng <icenowy@aosc.xyz>
S: Maintained
F: configs/orangepi_zero_defconfig
+ORANGEPI ZERO PLUS BOARD
+M: Hauke Mehrtens <hauke@hauke-m.de>
+S: Maintained
+F: configs/orangepi_zero_plus_defconfig
+
ORANGEPI ZERO PLUS 2 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
--- /dev/null
+++ b/configs/orangepi_zero_plus_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y