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ar71xx: drop target 

This target has been mostly replaced by ath79 and won't be included
in the upcoming release anymore. Finally put it to rest.

This also removes all references in packages, tools, etc. as well as
the uboot-ar71xx and vsc73x5-ucode packages.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This commit is contained in:
Adrian Schmutzler 2020-08-07 15:25:12 +02:00
parent 47b2ee2d9a
commit 4e4ee46495
489 changed files with 10 additions and 84828 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
config/Config-images.in
View File

@ -15,7 +15,6 @@ menu "Target Images"
choice
prompt "Compression"
default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_apm821xx
default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_ar71xx
default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_ath79_mikrotik
default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_lantiq
default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_mpc85xx

33
package/boot/uboot-ar71xx/Makefile
View File

@ -1,33 +0,0 @@
#
# Copyright (C) 2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_VERSION:=2010.03
PKG_RELEASE:=1
PKG_HASH:=902d1b2c15787df55186fae4033685fb0c5a5a12755a08383e97c4a3e255925b
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=ar71xx
BUILD_SUBTARGET:=generic
endef
define U-Boot/nbg460n_550n_550nh
TITLE:=NBG460N/550N/550NH routers
BUILD_DEVICES:=NBG_460N_550N_550NH
HIDDEN:=y
endef
UBOOT_MAKE_FLAGS :=
UBOOT_TARGETS:=nbg460n_550n_550nh
$(eval $(call BuildPackage/U-Boot))

82
package/boot/uboot-ar71xx/patches/0001-upstream-Reproducible-U-Boot-build-support-using-SOURCE_DATE_.patch
View File

@ -1,82 +0,0 @@
From f3f431a712729a1af94d01bd1bfde17a252ff02c Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <contact@paulk.fr>
Date: Sun, 26 Jul 2015 18:48:15 +0200
Subject: [PATCH] Reproducible U-Boot build support, using SOURCE_DATE_EPOCH
In order to achieve reproducible builds in U-Boot, timestamps that are defined
at build-time have to be somewhat eliminated. The SOURCE_DATE_EPOCH environment
variable allows setting a fixed value for those timestamps.
Simply by setting SOURCE_DATE_EPOCH to a fixed value, a number of targets can be
built reproducibly. This is the case for e.g. sunxi devices.
However, some other devices might need some more tweaks, especially regarding
the image generation tools.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
Makefile | 7 ++++---
README | 12 ++++++++++++
tools/default_image.c | 21 ++++++++++++++++++++-
3 files changed, 36 insertions(+), 4 deletions(-)
--- a/README
+++ b/README
@@ -2785,6 +2785,18 @@ Low Level (hardware related) configurati
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
+Reproducible builds
+-------------------
+
+In order to achieve reproducible builds, timestamps used in the U-Boot build
+process have to be set to a fixed value.
+
+This is done using the SOURCE_DATE_EPOCH environment variable.
+SOURCE_DATE_EPOCH is to be set on the build host's shell, not as a configuration
+option for U-Boot or an environment variable in U-Boot.
+
+SOURCE_DATE_EPOCH should be set to a number of seconds since the epoch, in UTC.
+
Building the Software:
======================
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -101,6 +101,9 @@ static void image_set_header (void *ptr,
struct mkimage_params *params)
{
uint32_t checksum;
+ char *source_date_epoch;
+ struct tm *time_universal;
+ time_t time;
image_header_t * hdr = (image_header_t *)ptr;
@@ -109,9 +112,25 @@ static void image_set_header (void *ptr,
sizeof(image_header_t)),
sbuf->st_size - sizeof(image_header_t));
+source_date_epoch = getenv("SOURCE_DATE_EPOCH");
+ if (source_date_epoch != NULL) {
+ time = (time_t) strtol(source_date_epoch, NULL, 10);
+
+ time_universal = gmtime(&time);
+ if (time_universal == NULL) {
+ fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
+ __func__);
+ time = 0;
+ } else {
+ time = mktime(time_universal);
+ }
+ } else {
+ time = sbuf->st_mtime;
+ }
+
/* Build new header */
image_set_magic (hdr, IH_MAGIC);
- image_set_time (hdr, sbuf->st_mtime);
+ image_set_time(hdr, time);
image_set_size (hdr, sbuf->st_size - sizeof(image_header_t));
image_set_load (hdr, params->addr);
image_set_ep (hdr, params->ep);

31
package/boot/uboot-ar71xx/patches/0002-upstream-Makefile-Reproducible-U-Boot-build-support.patch
View File

@ -1,31 +0,0 @@
--- a/Makefile
+++ b/Makefile
@@ -389,8 +389,26 @@ $(VERSION_FILE):
@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
$(TIMESTAMP_FILE):
- @date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
- @date +'#define U_BOOT_TIME "%T"' >> $@
+ (if test -n "$${SOURCE_DATE_EPOCH}"; then \
+ SOURCE_DATE="@$${SOURCE_DATE_EPOCH}"; \
+ DATE=""; \
+ for date in gdate date.gnu date; do \
+ $${date} -u -d "$${SOURCE_DATE}" >/dev/null 2>&1 && DATE="$${date}"; \
+ done; \
+ if test -n "$${DATE}"; then \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"' > $@; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"' >> $@; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"' >> $@; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"' >> $@; \
+ else \
+ return 42; \
+ fi; \
+ else \
+ LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
+ LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
+ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
+ LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
+ fi)
gdbtools:
$(MAKE) -C tools/gdb all || exit 1

26
package/boot/uboot-ar71xx/patches/001-ar71xx.patch
View File

@ -1,26 +0,0 @@
--- a/cpu/mips/Makefile
+++ b/cpu/mips/Makefile
@@ -33,6 +33,7 @@ SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o
COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o
COBJS-$(CONFIG_PURPLE) += asc_serial.o
COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+COBJS-$(CONFIG_AR71XX) += ar71xx_serial.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
--- a/Makefile
+++ b/Makefile
@@ -3474,6 +3474,13 @@ qemu_mips_config : unconfig
@$(MKCONFIG) -a qemu-mips mips mips qemu-mips
#########################################################################
+## MIPS32 AR71XX (24K)
+#########################################################################
+
+nbg460n_550n_550nh_config : unconfig
+ @$(MKCONFIG) -a nbg460n mips mips nbg460n zyxel
+
+#########################################################################
## MIPS64 5Kc
#########################################################################

11
package/boot/uboot-ar71xx/patches/002-ar71xx-spi.patch
View File

@ -1,11 +0,0 @@
diff -ur u-boot-2010.03/drivers/spi/Makefile u-boot-nbg/drivers/spi/Makefile
--- u-boot-2010.03/drivers/spi/Makefile 2010-03-31 23:54:39.000000000 +0200
+++ u-boot-nbg/drivers/spi/Makefile 2010-04-15 19:31:27.000000000 +0200
@@ -25,6 +25,7 @@
LIB := $(obj)libspi.a
+COBJS-$(CONFIG_AR71XX_SPI) += ar71xx_spi.o
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o

22
package/boot/uboot-ar71xx/patches/010-enet-ag71xx.patch
View File

@ -1,22 +0,0 @@
diff -ur u-boot-2010.03/drivers/net/Makefile u-boot-nbg/drivers/net/Makefile
--- u-boot-2010.03/drivers/net/Makefile 2010-03-31 23:54:39.000000000 +0200
+++ u-boot-nbg/drivers/net/Makefile 2010-04-19 23:30:01.000000000 +0200
@@ -27,6 +27,7 @@
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
+COBJS-$(CONFIG_AG71XX) += ag71xx.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
diff -ur u-boot-2010.03/include/netdev.h u-boot-nbg/include/netdev.h
--- u-boot-2010.03/include/netdev.h 2010-03-31 23:54:39.000000000 +0200
+++ u-boot-nbg/include/netdev.h 2010-05-02 11:30:58.000000000 +0200
@@ -42,6 +42,7 @@
/* Driver initialization prototypes */
int au1x00_enet_initialize(bd_t*);
+int ag71xx_register(bd_t * bis, char *phyname[], u16 phyid[], u16 phyfixed[]);
int at91emac_register(bd_t *bis, unsigned long iobase);
int bfin_EMAC_initialize(bd_t *bis);
int cs8900_initialize(u8 dev_num, int base_addr);

28
package/boot/uboot-ar71xx/patches/011-switch-rtl8366sr.patch
View File

@ -1,28 +0,0 @@
diff -ur u-boot-2010.03/drivers/net/Makefile u-boot-nbg/drivers/net/Makefile
--- u-boot-2010.03/drivers/net/Makefile 2010-03-31 23:54:39.000000000 +0200
+++ u-boot-nbg/drivers/net/Makefile 2010-04-19 23:30:01.000000000 +0200
@@ -65,6 +65,7 @@
COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
COBJS-$(CONFIG_RTL8139) += rtl8139.o
COBJS-$(CONFIG_RTL8169) += rtl8169.o
+COBJS-$(CONFIG_RTL8366_MII) += phy/rtl8366_mii.o
COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
COBJS-$(CONFIG_SMC91111) += smc91111.o
diff -ur u-boot-2010.03/include/netdev.h u-boot-nbg/include/netdev.h
--- u-boot-2010.03/include/netdev.h 2010-03-31 23:54:39.000000000 +0200
+++ u-boot-nbg/include/netdev.h 2010-05-02 11:30:58.000000000 +0200
@@ -175,5 +175,13 @@
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
#endif /* CONFIG_MV88E61XX_SWITCH */
+
+#if defined(CONFIG_RTL8366_MII)
+#define RTL8366_DEVNAME "rtl8366"
+#define RTL8366_WANPHY_ID 4
+#define RTL8366_LANPHY_ID -1
+int rtl8366_mii_register(bd_t *bis);
+int rtl8366s_initialize(void);
+#endif
#endif /* _NETDEV_H_ */

11
package/boot/uboot-ar71xx/patches/020-freebsd-compat.patch
View File

@ -1,11 +0,0 @@
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -46,7 +46,7 @@ extern int errno;
#ifdef __linux__
# include <endian.h>
# include <byteswap.h>
-#elif defined(__MACH__)
+#elif defined(__MACH__) || defined(__FreeBSD__)
# include <machine/endian.h>
typedef unsigned long ulong;
typedef unsigned int uint;

23
package/boot/uboot-ar71xx/patches/021-darwin_compat.patch
View File

@ -1,23 +0,0 @@
--- a/config.mk
+++ b/config.mk
@@ -64,9 +64,17 @@ HOSTSTRIP = strip
#
ifeq ($(HOSTOS),darwin)
-HOSTCC = cc
-HOSTCFLAGS += -traditional-cpp
-HOSTLDFLAGS += -multiply_defined suppress
+#get the major and minor product version (e.g. '10' and '6' for Snow Leopard)
+DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.')
+DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.')
+
+before-snow-leopard = $(shell if [ $(DARWIN_MAJOR_VERSION) -le 10 -a \
+ $(DARWIN_MINOR_VERSION) -le 5 ] ; then echo "$(1)"; else echo "$(2)"; fi ;)
+
+# Snow Leopards build environment has no longer restrictions as described above
+HOSTCC = $(call before-snow-leopard, "cc", "gcc")
+HOSTCFLAGS += $(call before-snow-leopard, "-traditional-cpp")
+HOSTLDFLAGS += $(call before-snow-leopard, "-multiply_defined suppress")
else
HOSTCC = gcc
endif

21
package/boot/uboot-ar71xx/patches/022-getline_backport.patch
View File

@ -1,21 +0,0 @@
--- a/tools/os_support.c
+++ b/tools/os_support.c
@@ -23,6 +23,6 @@
#ifdef __MINGW32__
#include "mingw_support.c"
#endif
-#ifdef __APPLE__
+#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
#include "getline.c"
#endif
--- a/tools/os_support.h
+++ b/tools/os_support.h
@@ -28,7 +28,7 @@
#include "mingw_support.h"
#endif
-#ifdef __APPLE__
+#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
#include "getline.h"
#endif

13
package/boot/uboot-ar71xx/patches/023-musl-compat.patch
View File

@ -1,13 +0,0 @@
--- a/include/compiler.h 2018-08-29
+++ b/include/compiler.h 2018-08-29
@@ -46,6 +46,10 @@ extern int errno;
#ifdef __linux__
# include <endian.h>
# include <byteswap.h>
+#ifndef __GLIBC__
+typedef unsigned long ulong;
+typedef unsigned int uint;
+#endif
#elif defined(__MACH__) || defined(__FreeBSD__)
# include <machine/endian.h>
typedef unsigned long ulong;

13
package/boot/uboot-ar71xx/patches/030-no_examples.patch
View File

@ -1,13 +0,0 @@
--- a/Makefile
+++ b/Makefile
@@ -139,9 +139,7 @@ endif
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
-SUBDIRS = tools \
- examples/standalone \
- examples/api
+SUBDIRS = tools
.PHONY : $(SUBDIRS)

112
package/boot/uboot-ar71xx/patches/040-no_extern_inline.patch
View File

@ -1,112 +0,0 @@
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -118,12 +118,12 @@ static inline void set_io_port_base(unsi
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/MIPS mapping
*/
-extern inline phys_addr_t virt_to_phys(volatile void * address)
+static inline phys_addr_t virt_to_phys(volatile void * address)
{
return CPHYSADDR(address);
}
-extern inline void * phys_to_virt(unsigned long address)
+static inline void * phys_to_virt(unsigned long address)
{
return (void *)KSEG0ADDR(address);
}
@@ -131,12 +131,12 @@ extern inline void * phys_to_virt(unsign
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
-extern inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long virt_to_bus(volatile void * address)
{
return CPHYSADDR(address);
}
-extern inline void * bus_to_virt(unsigned long address)
+static inline void * bus_to_virt(unsigned long address)
{
return (void *)KSEG0ADDR(address);
}
@@ -150,12 +150,12 @@ extern unsigned long isa_slot_offset;
extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
#if 0
-extern inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void *ioremap(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
@@ -238,7 +238,7 @@ out:
*/
#define __OUT1(s) \
-extern inline void __out##s(unsigned int value, unsigned int port) {
+static inline void __out##s(unsigned int value, unsigned int port) {
#define __OUT2(m) \
__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
@@ -252,7 +252,7 @@ __OUT1(s##c_p) __OUT2(m) : : "r" (__iosw
SLOW_DOWN_IO; }
#define __IN1(t,s) \
-extern __inline__ t __in##s(unsigned int port) { t _v;
+static inline t __in##s(unsigned int port) { t _v;
/*
* Required nops will be inserted by the assembler
@@ -267,7 +267,7 @@ __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i
__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
#define __INS1(s) \
-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
#define __INS2(m) \
if (count) \
@@ -295,7 +295,7 @@ __INS1(s##c) __INS2(m) \
: "$1");}
#define __OUTS1(s) \
-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
#define __OUTS2(m) \
if (count) \
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -23,7 +23,7 @@
#include <linux/kernel.h>
#endif
-extern __inline__ void
+static inline void
__sti(void)
{
__asm__ __volatile__(
@@ -47,7 +47,7 @@ __sti(void)
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
-extern __inline__ void
+static inline void
__cli(void)
{
__asm__ __volatile__(
@@ -208,7 +208,7 @@ do { \
* For 32 and 64 bit operands we can take advantage of ll and sc.
* FIXME: This doesn't work for R3000 machines.
*/
-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
+static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
{
#ifdef CONFIG_CPU_HAS_LLSC
unsigned long dummy;

12
package/boot/uboot-ar71xx/patches/041-no_weak_alias.patch
View File

@ -1,12 +0,0 @@
--- a/common/main.c
+++ b/common/main.c
@@ -47,8 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
-void inline __show_boot_progress (int val) {}
-void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
+void __attribute__((weak)) show_boot_progress(int val) {}
#if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* for do_reset() prototype */

46
package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/Makefile
View File

@ -1,46 +0,0 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
SOBJS-y += lowlevel_init.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

1
package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/config.mk
View File

@ -1 +0,0 @@
TEXT_BASE = 0x81E00000

39
package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/lowlevel_init.S
View File

@ -1,39 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
.globl lowlevel_init
/*
All done by Bootbase, nothing to do
*/
lowlevel_init:
jr ra
nop

96
package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/nbg460n.c
View File

@ -1,96 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/reboot.h>
#include <asm/ar71xx.h>
#include <asm/ar71xx_gpio.h>
#define NBG460N_WAN_LED 19
phys_size_t initdram(int board_type)
{
return (32*1024*1024);
}
int checkboard(void)
{
// Set pin 19 to 1, to stop WAN LED blinking
ar71xx_setpindir(NBG460N_WAN_LED, 1);
ar71xx_setpin(NBG460N_WAN_LED, 1);
printf("U-boot on Zyxel NBG460N\n");
return 0;
}
void _machine_restart(void)
{
for (;;) {
writel((RESET_MODULE_FULL_CHIP | RESET_MODULE_DDR),
KSEG1ADDR(AR71XX_RESET_BASE + AR91XX_RESET_REG_RESET_MODULE));
readl(KSEG1ADDR(AR71XX_RESET_BASE + AR91XX_RESET_REG_RESET_MODULE));
}
}
int board_eth_init(bd_t *bis)
{
char *phynames[] = {RTL8366_DEVNAME, RTL8366_DEVNAME};
u16 phyids[] = {RTL8366_LANPHY_ID, RTL8366_WANPHY_ID};
u16 phyfixed[] = {1, 0};
if (ag71xx_register(bis, phynames, phyids, phyfixed) <= 0)
return -1;
if (rtl8366s_initialize())
return -1;
if (rtl8366_mii_register(bis))
return -1;
return 0;
}
int misc_init_r(void) {
uint8_t macaddr[6];
uint8_t enetaddr[6];
debug("Testing mac addresses\n");
memcpy(macaddr, (uint8_t *) CONFIG_ETHADDR_ADDR, 6);
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
debug("Setting eth0 mac addr to %pM\n", macaddr);
eth_setenv_enetaddr("ethaddr", macaddr);
}
if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
macaddr[5] += 1;
debug("Setting eth1 mac addr to %pM\n", macaddr);
eth_setenv_enetaddr("eth1addr", macaddr);
}
return 0;
}

42
package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/u-boot.lds
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@ -1,42 +0,0 @@
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

177
package/boot/uboot-ar71xx/src/cpu/mips/ar71xx_serial.c
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@ -1,177 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/addrspace.h>
#include <asm/types.h>
#include <config.h>
#include <asm/ar71xx.h>
#define REG_SIZE 4
/* === END OF CONFIG === */
/* register offset */
#define OFS_RCV_BUFFER (0*REG_SIZE)
#define OFS_TRANS_HOLD (0*REG_SIZE)
#define OFS_SEND_BUFFER (0*REG_SIZE)
#define OFS_INTR_ENABLE (1*REG_SIZE)
#define OFS_INTR_ID (2*REG_SIZE)
#define OFS_DATA_FORMAT (3*REG_SIZE)
#define OFS_LINE_CONTROL (3*REG_SIZE)
#define OFS_MODEM_CONTROL (4*REG_SIZE)
#define OFS_RS232_OUTPUT (4*REG_SIZE)
#define OFS_LINE_STATUS (5*REG_SIZE)
#define OFS_MODEM_STATUS (6*REG_SIZE)
#define OFS_RS232_INPUT (6*REG_SIZE)
#define OFS_SCRATCH_PAD (7*REG_SIZE)
#define OFS_DIVISOR_LSB (0*REG_SIZE)
#define OFS_DIVISOR_MSB (1*REG_SIZE)
#define UART16550_READ(y) readl(KSEG1ADDR(AR71XX_UART_BASE+y))
#define UART16550_WRITE(x, z) writel(z, KSEG1ADDR((AR71XX_UART_BASE+x)))
void
ar71xx_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq)
{
#ifndef CONFIG_AR91XX
u32 pll, pll_div, cpu_div, ahb_div, ddr_div, freq;
pll = readl(KSEG1ADDR(AR71XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
pll_div =
((pll & AR71XX_PLL_DIV_MASK) >> AR71XX_PLL_DIV_SHIFT) + 1;
cpu_div =
((pll & AR71XX_CPU_DIV_MASK) >> AR71XX_CPU_DIV_SHIFT) + 1;
ddr_div =
((pll & AR71XX_DDR_DIV_MASK) >> AR71XX_DDR_DIV_SHIFT) + 1;
ahb_div =
(((pll & AR71XX_AHB_DIV_MASK) >> AR71XX_AHB_DIV_SHIFT) + 1)*2;
freq = pll_div * 40000000;
if (cpu_freq)
*cpu_freq = freq/cpu_div;
if (ddr_freq)
*ddr_freq = freq/ddr_div;
if (ahb_freq)
*ahb_freq = (freq/cpu_div)/ahb_div;
#else
u32 pll, pll_div, ahb_div, ddr_div, freq;
pll = readl(KSEG1ADDR(AR91XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
pll_div =
((pll & AR91XX_PLL_DIV_MASK) >> AR91XX_PLL_DIV_SHIFT);
ddr_div =
((pll & AR91XX_DDR_DIV_MASK) >> AR91XX_DDR_DIV_SHIFT) + 1;
ahb_div =
(((pll & AR91XX_AHB_DIV_MASK) >> AR91XX_AHB_DIV_SHIFT) + 1)*2;
freq = pll_div * 5000000;
if (cpu_freq)
*cpu_freq = freq;
if (ddr_freq)
*ddr_freq = freq/ddr_div;
if (ahb_freq)
*ahb_freq = freq/ahb_div;
#endif
}
int serial_init(void)
{
u32 div;
u32 ahb_freq = 100000000;
ar71xx_sys_frequency (0, 0, &ahb_freq);
div = ahb_freq/(16 * CONFIG_BAUDRATE);
// enable uart pins
#ifndef CONFIG_AR91XX
writel(AR71XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
#else
writel(AR91XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
#endif
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
UART16550_WRITE(OFS_DIVISOR_LSB, (div & 0xff));
UART16550_WRITE(OFS_DIVISOR_MSB, ((div >> 8) & 0xff));
/* clear DIAB bit*/
UART16550_WRITE(OFS_LINE_CONTROL, 0x00);
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, 0x3);
UART16550_WRITE(OFS_INTR_ENABLE, 0);
return 0;
}
int serial_tstc (void)
{
return(UART16550_READ(OFS_LINE_STATUS) & 0x1);
}
int serial_getc(void)
{
while(!serial_tstc());
return UART16550_READ(OFS_RCV_BUFFER);
}
void serial_putc(const char byte)
{
if (byte == '\n') serial_putc ('\r');
while (((UART16550_READ(OFS_LINE_STATUS)) & 0x20) == 0x0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
}
void serial_setbrg (void)
{
}
void serial_puts (const char *s)
{
while (*s)
{
serial_putc (*s++);
}
}

809
package/boot/uboot-ar71xx/src/drivers/net/ag71xx.c
View File

@ -1,809 +0,0 @@
/*
* Atheros AR71xx built-in ethernet mac driver
*
* Copyright (C) 2010 Michael Kurz <michi.kurz@googlemail.com>
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/ar71xx.h>
#include "ag71xx.h"
#ifdef AG71XX_DEBUG
#define DBG(fmt,args...) printf(fmt ,##args)
#else
#define DBG(fmt,args...)
#endif
static struct ag71xx agtable[] = {
{
.mac_base = KSEG1ADDR(AR71XX_GE0_BASE),
.mii_ctrl = KSEG1ADDR(AR71XX_MII_BASE + MII_REG_MII0_CTRL),
.mii_if = CONFIG_AG71XX_MII0_IIF,
} , {
.mac_base = KSEG1ADDR(AR71XX_GE1_BASE),
.mii_ctrl = KSEG1ADDR(AR71XX_MII_BASE + MII_REG_MII1_CTRL),
.mii_if = CONFIG_AG71XX_MII1_IIF,
}
};
static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
{
int err;
int i;
int rsize;
ring->desc_size = sizeof(struct ag71xx_desc);
if (ring->desc_size % (CONFIG_SYS_CACHELINE_SIZE)) {
rsize = roundup(ring->desc_size, CONFIG_SYS_CACHELINE_SIZE);
DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
ring, ring->desc_size,
rsize);
ring->desc_size = rsize;
}
ring->descs_cpu = (u8 *) malloc((size * ring->desc_size)
+ CONFIG_SYS_CACHELINE_SIZE - 1);
if (!ring->descs_cpu) {
err = -1;
goto err;
}
ring->descs_cpu = (u8 *) UNCACHED_SDRAM((((u32) ring->descs_cpu +
CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1)));
ring->descs_dma = (u8 *) virt_to_phys(ring->descs_cpu);
ring->size = size;
ring->buf = malloc(size * sizeof(*ring->buf));
if (!ring->buf) {
err = -1;
goto err;
}
memset(ring->buf, 0, size * sizeof(*ring->buf));
for (i = 0; i < size; i++) {
ring->buf[i].desc =
(struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
DBG("ag71xx: ring %p, desc %d at %p\n",
ring, i, ring->buf[i].desc);
}
flush_cache( (u32) ring->buf, size * sizeof(*ring->buf));
return 0;
err:
return err;
}
static void ag71xx_ring_tx_init(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->tx_ring;
int i;
for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
ring->buf[i].desc->next = (u32) virt_to_phys((ring->descs_dma +
ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE)));
ring->buf[i].desc->ctrl = DESC_EMPTY;
ring->buf[i].skb = NULL;
}
ring->curr = 0;
}
static void ag71xx_ring_rx_clean(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->rx_ring;
int i;
if (!ring->buf)
return;
for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
ring->buf[i].desc->data = (u32) virt_to_phys(NetRxPackets[i]);
flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
ring->buf[i].desc->ctrl = DESC_EMPTY;
}
ring->curr = 0;
}
static int ag71xx_ring_rx_init(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->rx_ring;
unsigned int i;
for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
ring->buf[i].desc->next = (u32) virt_to_phys((ring->descs_dma +
ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE)));
DBG("ag71xx: RX desc at %p, next is %08x\n",
ring->buf[i].desc,
ring->buf[i].desc->next);
}
for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
ring->buf[i].desc->data = (u32) virt_to_phys(NetRxPackets[i]);
ring->buf[i].desc->ctrl = DESC_EMPTY;
}
ring->curr = 0;
return 0;
}
static int ag71xx_rings_init(struct ag71xx *ag)
{
int ret;
ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
if (ret)
return ret;
ag71xx_ring_tx_init(ag);
ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
if (ret)
return ret;
ret = ag71xx_ring_rx_init(ag);
return ret;
}
static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
{
uint32_t base = KSEG1ADDR(AR71XX_PLL_BASE);
u32 t;
t = readl(base + cfg_reg);
t &= ~(3 << shift);
t |= (2 << shift);
writel(t, base + cfg_reg);
udelay(100);
writel(pll_val, base + pll_reg);
t |= (3 << shift);
writel(t, base + cfg_reg);
udelay(100);
t &= ~(3 << shift);
writel(t, base + cfg_reg);
udelay(100);
debug("ar71xx: pll_reg %#x: %#x\n", (unsigned int)(base + pll_reg),
readl(base + pll_reg));
}
static void ar91xx_set_pll_ge0(int speed)
{
//u32 val = ar71xx_get_eth_pll(0, speed);
u32 pll_val;
switch (speed) {
case SPEED_10:
pll_val = 0x00441099;
break;
case SPEED_100:
pll_val = 0x13000a44;
break;
case SPEED_1000:
pll_val = 0x1a000000;
break;
default:
BUG();
}
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
pll_val, AR91XX_ETH0_PLL_SHIFT);
}
static void ar91xx_set_pll_ge1(int speed)
{
//u32 val = ar71xx_get_eth_pll(1, speed);
u32 pll_val;
switch (speed) {
case SPEED_10:
pll_val = 0x00441099;
break;
case SPEED_100:
pll_val = 0x13000a44;
break;
case SPEED_1000:
pll_val = 0x1a000000;
break;
default:
BUG();
}
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
pll_val, AR91XX_ETH1_PLL_SHIFT);
}
static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
{
u32 t;
t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
| (((u32) mac[3]) << 8) | ((u32) mac[2]);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
}
static void ag71xx_dma_reset(struct ag71xx *ag)
{
u32 val;
int i;
DBG("%s: txdesc reg: 0x%08x rxdesc reg: 0x%08x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_TX_DESC),
ag71xx_rr(ag, AG71XX_REG_RX_DESC));
/* stop RX and TX */
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
/* clear descriptor addresses */
ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
/* clear pending RX/TX interrupts */
for (i = 0; i < 256; i++) {
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
}
/* clear pending errors */
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
if (val)
printf("%s: unable to clear DMA Rx status: %08x\n",
ag->dev->name, val);
val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
/* mask out reserved bits */
val &= ~0xff000000;
if (val)
printf("%s: unable to clear DMA Tx status: %08x\n",
ag->dev->name, val);
}
static void ag71xx_halt(struct eth_device *dev)
{
struct ag71xx *ag = (struct ag71xx *) dev->priv;
/* stop RX engine */
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
ag71xx_dma_reset(ag);
}
#define MAX_WAIT 1000
static int ag71xx_send(struct eth_device *dev, volatile void *packet,
int length)
{
struct ag71xx *ag = (struct ag71xx *) dev->priv;
struct ag71xx_ring *ring = &ag->tx_ring;
struct ag71xx_desc *desc;
int i;
i = ring->curr % AG71XX_TX_RING_SIZE;
desc = ring->buf[i].desc;
if (!ag71xx_desc_empty(desc)) {
printf("%s: tx buffer full\n", ag->dev->name);
return 1;
}
flush_cache((u32) packet, length);
desc->data = (u32) virt_to_phys(packet);
desc->ctrl = (length & DESC_PKTLEN_M);
DBG("%s: sending %#08x length %#08x\n",
ag->dev->name, desc->data, desc->ctrl);
ring->curr++;
if (ring->curr >= AG71XX_TX_RING_SIZE){
ring->curr = 0;
}
/* enable TX engine */
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
for (i = 0; i < MAX_WAIT; i++)
{
if (ag71xx_desc_empty(desc))
break;
udelay(10);
}
if (i == MAX_WAIT) {
printf("%s: tx timed out!\n", ag->dev->name);
return -1;
}
/* disable TX engine */
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
desc->data = 0;
desc->ctrl = DESC_EMPTY;
return 0;
}
static int ag71xx_recv(struct eth_device *dev)
{
struct ag71xx *ag = (struct ag71xx *) dev->priv;
struct ag71xx_ring *ring = &ag->rx_ring;
for (;;) {
unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
struct ag71xx_desc *desc = ring->buf[i].desc;
int pktlen;
if (ag71xx_desc_empty(desc))
break;
DBG("%s: rx packets, curr=%u\n", dev->name, ring->curr);
pktlen = ag71xx_desc_pktlen(desc);
pktlen -= ETH_FCS_LEN;
NetReceive(NetRxPackets[i] , pktlen);
flush_cache( (u32) NetRxPackets[i], PKTSIZE_ALIGN);
ring->buf[i].desc->ctrl = DESC_EMPTY;
ring->curr++;
if (ring->curr >= AG71XX_RX_RING_SIZE){
ring->curr = 0;
}
}
if ((ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE) == 0) {
/* start RX engine */
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
}
return 0;
}
#ifdef AG71XX_DEBUG
static char *ag71xx_speed_str(struct ag71xx *ag)
{
switch (ag->speed) {
case SPEED_1000:
return "1000";
case SPEED_100:
return "100";
case SPEED_10:
return "10";
}
return "?";
}
#endif
void ag71xx_link_adjust(struct ag71xx *ag)
{
u32 cfg2;
u32 ifctl;
u32 fifo5;
u32 mii_speed;
if (!ag->link) {
DBG("%s: link down\n", ag->dev->name);
return;
}
cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
ifctl &= ~(MAC_IFCTL_SPEED);
fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
fifo5 &= ~FIFO_CFG5_BM;
switch (ag->speed) {
case SPEED_1000:
mii_speed = MII_CTRL_SPEED_1000;
cfg2 |= MAC_CFG2_IF_1000;
fifo5 |= FIFO_CFG5_BM;
break;
case SPEED_100:
mii_speed = MII_CTRL_SPEED_100;
cfg2 |= MAC_CFG2_IF_10_100;
ifctl |= MAC_IFCTL_SPEED;
break;
case SPEED_10:
mii_speed = MII_CTRL_SPEED_10;
cfg2 |= MAC_CFG2_IF_10_100;
break;
default:
BUG();
return;
}
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
if (ag->macNum == 0)
ar91xx_set_pll_ge0(ag->speed);
else
ar91xx_set_pll_ge1(ag->speed);
ag71xx_mii_ctrl_set_speed(ag, mii_speed);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
DBG("%s: link up (%sMbps/%s duplex)\n",
ag->dev->name,
ag71xx_speed_str(ag),
(1 == ag->duplex) ? "Full" : "Half");
DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
ag71xx_mii_ctrl_rr(ag));
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static int ag71xx_getMiiSpeed(struct ag71xx *ag)
{
uint16_t phyreg, cap;
if (miiphy_read(ag->phyname, ag->phyid,
PHY_BMSR, &phyreg)) {
puts("PHY_BMSR read failed, assuming no link\n");
return -1;
}
if ((phyreg & PHY_BMSR_LS) == 0) {
return -1;
}
if (miiphy_read(ag->phyname, ag->phyid,
PHY_1000BTSR, &phyreg))
return -1;
if (phyreg & PHY_1000BTSR_1000FD) {
ag->speed = SPEED_1000;
ag->duplex = 1;
} else if (phyreg & PHY_1000BTSR_1000HD) {
ag->speed = SPEED_1000;
ag->duplex = 0;
} else {
if (miiphy_read(ag->phyname, ag->phyid,
PHY_ANAR, &cap))
return -1;
if (miiphy_read(ag->phyname, ag->phyid,
PHY_ANLPAR, &phyreg))
return -1;
cap &= phyreg;
if (cap & PHY_ANLPAR_TXFD) {
ag->speed = SPEED_100;
ag->duplex = 1;
} else if (cap & PHY_ANLPAR_TX) {
ag->speed = SPEED_100;
ag->duplex = 0;
} else if (cap & PHY_ANLPAR_10FD) {
ag->speed = SPEED_10;
ag->duplex = 1;
} else {
ag->speed = SPEED_10;
ag->duplex = 0;
}
}
ag->link = 1;
return 0;
}
#endif
static int ag71xx_hw_start(struct eth_device *dev, bd_t * bd)
{
struct ag71xx *ag = (struct ag71xx *) dev->priv;
ag71xx_dma_reset(ag);
ag71xx_ring_rx_clean(ag);
ag71xx_ring_tx_init(ag);
ag71xx_wr(ag, AG71XX_REG_TX_DESC,
(u32) virt_to_phys(ag->tx_ring.descs_dma));
ag71xx_wr(ag, AG71XX_REG_RX_DESC,
(u32) virt_to_phys(ag->rx_ring.descs_dma));
ag71xx_hw_set_macaddr(ag, ag->dev->enetaddr);
if (ag->phyfixed) {
ag->link = 1;
ag->duplex = 1;
ag->speed = SPEED_1000;
} else {
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
if (ag71xx_getMiiSpeed(ag))
return -1;
#else
/* only fixed, without mii */
return -1;
#endif
}
ag71xx_link_adjust(ag);
DBG("%s: txdesc reg: %#08x rxdesc reg: %#08x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_TX_DESC),
ag71xx_rr(ag, AG71XX_REG_RX_DESC));
/* start RX engine */
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
return 0;
}
#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
FIFO_CFG4_VT)
#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
FIFO_CFG5_17 | FIFO_CFG5_SF)
static int ag71xx_hw_init(struct ag71xx *ag)
{
int ret = 0;
uint32_t reg;
uint32_t mask, mii_type;
if (ag->macNum == 0) {
mask = (RESET_MODULE_GE0_MAC | RESET_MODULE_GE0_PHY);
mii_type = 0x13;
} else {
mask = (RESET_MODULE_GE1_MAC | RESET_MODULE_GE1_PHY);
mii_type = 0x11;
}
// mac soft reset
ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
udelay(20);
// device stop
reg = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
udelay(100 * 1000);
// device start
reg = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
udelay(100 * 1000);
/* setup MAC configuration registers */
ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, (MAC_CFG1_RXE | MAC_CFG1_TXE));
ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
/* setup FIFO configuration register 0 */
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
/* setup MII interface type */
ag71xx_mii_ctrl_set_if(ag, ag->mii_if);
/* setup mdio clock divisor */
ag71xx_wr(ag, AG71XX_REG_MII_CFG, MII_CFG_CLK_DIV_20);
/* setup FIFO configuration registers */
ag71xx_sb(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
ag71xx_dma_reset(ag);
ret = ag71xx_rings_init(ag);
if (ret)
return -1;
ag71xx_wr(ag, AG71XX_REG_TX_DESC,
(u32) virt_to_phys(ag->tx_ring.descs_dma));
ag71xx_wr(ag, AG71XX_REG_RX_DESC,
(u32) virt_to_phys(ag->rx_ring.descs_dma));
ag71xx_hw_set_macaddr(ag, ag->dev->enetaddr);
return 0;
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#define AG71XX_MDIO_RETRY 1000
#define AG71XX_MDIO_DELAY 5
static inline struct ag71xx *ag71xx_name2mac(char *devname)
{
if (strcmp(devname, agtable[0].dev->name) == 0)
return &agtable[0];
else if (strcmp(devname, agtable[1].dev->name) == 0)
return &agtable[1];
else
return NULL;
}
static inline void ag71xx_mdio_wr(struct ag71xx *ag, unsigned reg,
u32 value)
{
uint32_t r;
r = ag->mac_base + reg;
writel(value, r);
/* flush write */
(void) readl(r);
}
static inline u32 ag71xx_mdio_rr(struct ag71xx *ag, unsigned reg)
{
return readl(ag->mac_base + reg);
}
static int ag71xx_mdio_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *val)
{
struct ag71xx *ag = ag71xx_name2mac(devname);
uint16_t regData;
int i;
ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
ag71xx_mdio_wr(ag, AG71XX_REG_MII_ADDR,
((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
i = AG71XX_MDIO_RETRY;
while (ag71xx_mdio_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
if (i-- == 0) {
printf("%s: mii_read timed out\n",
ag->dev->name);
return -1;
}
udelay(AG71XX_MDIO_DELAY);
}
regData = (uint16_t) ag71xx_mdio_rr(ag, AG71XX_REG_MII_STATUS) & 0xffff;
ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, regData);
if (val)
*val = regData;
return 0;
}
static int ag71xx_mdio_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short val)
{
struct ag71xx *ag = ag71xx_name2mac(devname);
int i;
if (ag == NULL)
return 1;
DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
ag71xx_mdio_wr(ag, AG71XX_REG_MII_ADDR,
((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
ag71xx_mdio_wr(ag, AG71XX_REG_MII_CTRL, val);
i = AG71XX_MDIO_RETRY;
while (ag71xx_mdio_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
if (i-- == 0) {
printf("%s: mii_write timed out\n",
ag->dev->name);
break;
}
udelay(AG71XX_MDIO_DELAY);
}
return 0;
}
#endif
int ag71xx_register(bd_t * bis, char *phyname[], uint16_t phyid[], uint16_t phyfixed[])
{
int i, num = 0;
u8 used_ports[MAX_AG71XX_DEVS] = CONFIG_AG71XX_PORTS;
for (i = 0; i < MAX_AG71XX_DEVS; i++) {
/*skip if port is configured not to use */
if (used_ports[i] == 0)
continue;
agtable[i].dev = malloc(sizeof(struct eth_device));
if (agtable[i].dev == NULL) {
puts("malloc failed\n");
return 0;
}
memset(agtable[i].dev, 0, sizeof(struct eth_device));
sprintf(agtable[i].dev->name, "eth%d", i);
agtable[i].dev->iobase = 0;
agtable[i].dev->init = ag71xx_hw_start;
agtable[i].dev->halt = ag71xx_halt;
agtable[i].dev->send = ag71xx_send;
agtable[i].dev->recv = ag71xx_recv;
agtable[i].dev->priv = (void *) (&agtable[i]);
agtable[i].macNum = i;
eth_register(agtable[i].dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
if ((phyname == NULL) || (phyid == NULL) || (phyfixed == NULL))
return -1;
agtable[i].phyname = strdup(phyname[i]);
agtable[i].phyid = phyid[i];
agtable[i].phyfixed = phyfixed[i];
miiphy_register(agtable[i].dev->name, ag71xx_mdio_read,
ag71xx_mdio_write);
#endif
if (ag71xx_hw_init(&agtable[i]))
continue;
num++;
}
return num;
}

374
package/boot/uboot-ar71xx/src/drivers/net/ag71xx.h
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@ -1,374 +0,0 @@
/*
* Atheros AR71xx built-in ethernet mac driver
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __AG71XX_H
#define __AG71XX_H
#include <linux/types.h>
#include <linux/bitops.h>
#include <asm/ar71xx.h>
// controller has 2 ports
#define MAX_AG71XX_DEVS 2
#define ETH_FCS_LEN 4
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
#define AG71XX_TX_FIFO_LEN 2048
#define AG71XX_TX_MTU_LEN 1536
#define AG71XX_RX_PKT_RESERVE 64
#define AG71XX_RX_PKT_SIZE \
(AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
#ifndef CONFIG_SYS_RX_ETH_BUFFER
#define AG71XX_TX_RING_SIZE 4
#define AG71XX_RX_RING_SIZE 4
#else
#define AG71XX_TX_RING_SIZE CONFIG_SYS_RX_ETH_BUFFER
#define AG71XX_RX_RING_SIZE CONFIG_SYS_RX_ETH_BUFFER
#endif
#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
#define AG71XX_TX_THRES_WAKEUP \
(AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
struct ag71xx_desc {
u32 data;
u32 ctrl;
#define DESC_EMPTY BIT(31)
#define DESC_MORE BIT(24)
#define DESC_PKTLEN_M 0xfff
u32 next;
u32 pad;
} __attribute__((aligned(4)));
struct ag71xx_buf {
struct sk_buff *skb;
struct ag71xx_desc *desc;
dma_addr_t dma_addr;
u32 pad;
};
struct ag71xx_ring {
struct ag71xx_buf *buf;
u8 *descs_cpu;
u8 *descs_dma;
unsigned int desc_size;
unsigned int curr;
unsigned int size;
};
struct ag71xx {
uint32_t mac_base;
uint32_t mii_ctrl;
struct eth_device *dev;
struct ag71xx_ring rx_ring;
struct ag71xx_ring tx_ring;
char *phyname;
u16 phyid;
u16 phyfixed;
uint32_t link;
uint32_t speed;
int32_t duplex;
uint32_t macNum;
uint32_t mii_if;
};
void ag71xx_link_adjust(struct ag71xx *ag);
int ag71xx_phy_connect(struct ag71xx *ag);
void ag71xx_phy_disconnect(struct ag71xx *ag);
void ag71xx_phy_start(struct ag71xx *ag);
void ag71xx_phy_stop(struct ag71xx *ag);
static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
{
return ((desc->ctrl & DESC_EMPTY) != 0);
}
static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
{
return (desc->ctrl & DESC_PKTLEN_M);
}
/* Register offsets */
#define AG71XX_REG_MAC_CFG1 0x0000
#define AG71XX_REG_MAC_CFG2 0x0004
#define AG71XX_REG_MAC_IPG 0x0008
#define AG71XX_REG_MAC_HDX 0x000c
#define AG71XX_REG_MAC_MFL 0x0010
#define AG71XX_REG_MII_CFG 0x0020
#define AG71XX_REG_MII_CMD 0x0024
#define AG71XX_REG_MII_ADDR 0x0028
#define AG71XX_REG_MII_CTRL 0x002c
#define AG71XX_REG_MII_STATUS 0x0030
#define AG71XX_REG_MII_IND 0x0034
#define AG71XX_REG_MAC_IFCTL 0x0038
#define AG71XX_REG_MAC_ADDR1 0x0040
#define AG71XX_REG_MAC_ADDR2 0x0044
#define AG71XX_REG_FIFO_CFG0 0x0048
#define AG71XX_REG_FIFO_CFG1 0x004c
#define AG71XX_REG_FIFO_CFG2 0x0050
#define AG71XX_REG_FIFO_CFG3 0x0054
#define AG71XX_REG_FIFO_CFG4 0x0058
#define AG71XX_REG_FIFO_CFG5 0x005c
#define AG71XX_REG_FIFO_RAM0 0x0060
#define AG71XX_REG_FIFO_RAM1 0x0064
#define AG71XX_REG_FIFO_RAM2 0x0068
#define AG71XX_REG_FIFO_RAM3 0x006c
#define AG71XX_REG_FIFO_RAM4 0x0070
#define AG71XX_REG_FIFO_RAM5 0x0074
#define AG71XX_REG_FIFO_RAM6 0x0078
#define AG71XX_REG_FIFO_RAM7 0x007c
#define AG71XX_REG_TX_CTRL 0x0180
#define AG71XX_REG_TX_DESC 0x0184
#define AG71XX_REG_TX_STATUS 0x0188
#define AG71XX_REG_RX_CTRL 0x018c
#define AG71XX_REG_RX_DESC 0x0190
#define AG71XX_REG_RX_STATUS 0x0194
#define AG71XX_REG_INT_ENABLE 0x0198
#define AG71XX_REG_INT_STATUS 0x019c
#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
#define MAC_CFG1_LB BIT(8) /* Loopback mode */
#define MAC_CFG1_SR BIT(31) /* Soft Reset */
#define MAC_CFG2_FDX BIT(0)
#define MAC_CFG2_CRC_EN BIT(1)
#define MAC_CFG2_PAD_CRC_EN BIT(2)
#define MAC_CFG2_LEN_CHECK BIT(4)
#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
#define MAC_CFG2_IF_1000 BIT(9)
#define MAC_CFG2_IF_10_100 BIT(8)
#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
| FIFO_CFG0_TXS | FIFO_CFG0_TXF)
#define FIFO_CFG0_ENABLE_SHIFT 8
#define FIFO_CFG4_DE BIT(0) /* Drop Event */
#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
#define FIFO_CFG4_FC BIT(2) /* False Carrier */
#define FIFO_CFG4_CE BIT(3) /* Code Error */
#define FIFO_CFG4_CR BIT(4) /* CRC error */
#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
#define FIFO_CFG4_LO BIT(6) /* Length out of range */
#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
#define FIFO_CFG4_DR BIT(10) /* Dribble */
#define FIFO_CFG4_LE BIT(11) /* Long Event */
#define FIFO_CFG4_CF BIT(12) /* Control Frame */
#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG5_DE BIT(0) /* Drop Event */
#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
#define FIFO_CFG5_FC BIT(2) /* False Carrier */
#define FIFO_CFG5_CE BIT(3) /* Code Error */
#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
#define FIFO_CFG5_DR BIT(9) /* Dribble */
#define FIFO_CFG5_CF BIT(10) /* Control Frame */
#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
#define FIFO_CFG5_LE BIT(14) /* Long Event */
#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
#define FIFO_CFG5_16 BIT(16) /* unknown */
#define FIFO_CFG5_17 BIT(17) /* unknown */
#define FIFO_CFG5_SF BIT(18) /* Short Frame */
#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
#define AG71XX_INT_TX_PS BIT(0)
#define AG71XX_INT_TX_UR BIT(1)
#define AG71XX_INT_TX_BE BIT(3)
#define AG71XX_INT_RX_PR BIT(4)
#define AG71XX_INT_RX_OF BIT(6)
#define AG71XX_INT_RX_BE BIT(7)
#define MAC_IFCTL_SPEED BIT(16)
#define MII_CFG_CLK_DIV_4 0
#define MII_CFG_CLK_DIV_6 2
#define MII_CFG_CLK_DIV_8 3
#define MII_CFG_CLK_DIV_10 4
#define MII_CFG_CLK_DIV_14 5
#define MII_CFG_CLK_DIV_20 6
#define MII_CFG_CLK_DIV_28 7
#define MII_CFG_RESET BIT(31)
#define MII_CMD_WRITE 0x0
#define MII_CMD_READ 0x1
#define MII_ADDR_SHIFT 8
#define MII_IND_BUSY BIT(0)
#define MII_IND_INVALID BIT(2)
#define TX_CTRL_TXE BIT(0) /* Tx Enable */
#define TX_STATUS_PS BIT(0) /* Packet Sent */
#define TX_STATUS_UR BIT(1) /* Tx Underrun */
#define TX_STATUS_BE BIT(3) /* Bus Error */
#define RX_CTRL_RXE BIT(0) /* Rx Enable */
#define RX_STATUS_PR BIT(0) /* Packet Received */
#define RX_STATUS_OF BIT(2) /* Rx Overflow */
#define RX_STATUS_BE BIT(3) /* Bus Error */
#define MII_CTRL_IF_MASK 3
#define MII_CTRL_SPEED_SHIFT 4
#define MII_CTRL_SPEED_MASK 3
#define MII_CTRL_SPEED_10 0
#define MII_CTRL_SPEED_100 1
#define MII_CTRL_SPEED_1000 2
static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
{
__raw_writel(value, ag->mac_base + reg);
/* flush write */
(void) __raw_readl(ag->mac_base + reg);
}
static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
{
return __raw_readl(ag->mac_base + reg);
}
static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
{
uint32_t r;
r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) | mask, r);
/* flush write */
(void)__raw_readl(r);
}
static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
{
uint32_t r;
r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) & ~mask, r);
/* flush write */
(void) __raw_readl(r);
}
static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
{
ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
}
static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
{
ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
}
static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
{
__raw_writel(value, ag->mii_ctrl);
/* flush write */
__raw_readl(ag->mii_ctrl);
}
static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
{
return __raw_readl(ag->mii_ctrl);
}
static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
unsigned int mii_if)
{
u32 t;
t = ag71xx_mii_ctrl_rr(ag);
t &= ~(MII_CTRL_IF_MASK);
t |= (mii_if & MII_CTRL_IF_MASK);
ag71xx_mii_ctrl_wr(ag, t);
}
static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
unsigned int speed)
{
u32 t;
t = ag71xx_mii_ctrl_rr(ag);
t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
ag71xx_mii_ctrl_wr(ag, t);
}
#ifdef CONFIG_AG71XX_AR8216_SUPPORT
void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
int pktlen);
static inline int ag71xx_has_ar8216(struct ag71xx *ag)
{
return ag71xx_get_pdata(ag)->has_ar8216;
}
#else
static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
struct sk_buff *skb)
{
}
static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
struct sk_buff *skb,
int pktlen)
{
return 0;
}
static inline int ag71xx_has_ar8216(struct ag71xx *ag)
{
return 0;
}
#endif
#endif /* _AG71XX_H */

188
package/boot/uboot-ar71xx/src/drivers/net/phy/rtl8366.h
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@ -1,188 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef RTL8366_MII_H
#define RTL8366_MII_H
#define MII_CONTROL_REG 0
#define MII_STATUS_REG 1
#define MII_PHY_ID0 2
#define MII_PHY_ID1 3
#define MII_LOCAL_CAP 4
#define MII_REMOTE_CAP 5
#define MII_EXT_AUTONEG 6
#define MII_LOCAL_NEXT_PAGE 7
#define MII_REMOTE_NEXT_PAGE 8
#define MII_GIGA_CONTROL 9
#define MII_GIGA_STATUS 10
#define MII_EXT_STATUS_REG 15
/* Control register */
#define MII_CONTROL_1000MBPS 6
#define MII_CONTROL_COLL_TEST 7
#define MII_CONTROL_FULLDUPLEX 8
#define MII_CONTROL_RENEG 9
#define MII_CONTROL_ISOLATE 10
#define MII_CONTROL_POWERDOWN 11
#define MII_CONTROL_AUTONEG 12
#define MII_CONTROL_100MBPS 13
#define MII_CONTROL_LOOPBACK 14
#define MII_CONTROL_RESET 15
/* Status/Extended status register */
/* Basic status */
#define MII_STATUS_CAPABILITY 0
#define MII_STATUS_JABBER 1
#define MII_STATUS_LINK_UP 2
#define MII_STATUS_AUTONEG_ABLE 3
#define MII_STATUS_REMOTE_FAULT 4
#define MII_STATUS_AUTONEG_DONE 5
#define MII_STATUS_NO_PREAMBLE 6
#define MII_STATUS_RESERVED 7
#define MII_STATUS_EXTENDED 8
#define MII_STATUS_100_T2_HALF 9
#define MII_STATUS_100_T2_FULL 10
#define MII_STATUS_10_TX_HALF 11
#define MII_STATUS_10_TX_FULL 12
#define MII_STATUS_100_TX_HALF 13
#define MII_STATUS_100_TX_FULL 14
#define MII_STATUS_100_T4 15
#define MII_GIGA_CONTROL_HALF 8
#define MII_GIGA_CONTROL_FULL 9
#define MII_GIGA_STATUS_HALF 10
#define MII_GIGA_STATUS_FULL 11
/* Extended status */
#define MII_STATUS_1000_T_HALF 12
#define MII_STATUS_1000_T_FULL 13
#define MII_STATUS_1000_X_HALF 14
#define MII_STATUS_1000_X_FULL 15
/* Local/Remmote capability register */
#define MII_CAP_10BASE_TX 5
#define MII_CAP_10BASE_TX_FULL 6
#define MII_CAP_100BASE_TX 7
#define MII_CAP_100BASE_TX_FULL 8
#define MII_CAP_100BASE_T4 9
#define MII_CAP_SYMM_PAUSE 10
#define MII_CAP_ASYMM_PAUSE 11
#define MII_CAP_RESERVED 12
#define MII_CAP_REMOTE_FAULT 13
#define MII_CAP_ACKNOWLEDGE 14
#define MII_CAP_NEXT_PAGE 15
#define MII_CAP_IEEE_802_3 0x0001
#define MII_LINK_MODE_MASK 0x1f
#define REALTEK_RTL8366_CHIP_ID0 0x001C
#define REALTEK_RTL8366_CHIP_ID1 0xC940
#define REALTEK_RTL8366_CHIP_ID1_MP 0xC960
#define REALTEK_MIN_PORT_ID 0
#define REALTEK_MAX_PORT_ID 5
#define REALTEK_MIN_PHY_ID REALTEK_MIN_PORT_ID
#define REALTEK_MAX_PHY_ID 4
#define REALTEK_CPU_PORT_ID REALTEK_MAX_PORT_ID
#define REALTEK_PHY_PORT_MASK ((1<<(REALTEK_MAX_PHY_ID+1)) - (1<<REALTEK_MIN_PHY_ID))
#define REALTEK_CPU_PORT_MASK (1<<REALTEK_CPU_PORT_ID)
#define REALTEK_ALL_PORT_MASK (REALTEK_PHY_PORT_MASK | REALTEK_CPU_PORT_MASK)
/* port ability */
#define RTL8366S_PORT_ABILITY_BASE 0x0011
/* port vlan control register */
#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
/* port linking status */
#define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
#define RTL8366S_PORT_STATUS_SPEED_BIT 0
#define RTL8366S_PORT_STATUS_SPEED_MSK 0x0003
#define RTL8366S_PORT_STATUS_DUPLEX_BIT 2
#define RTL8366S_PORT_STATUS_DUPLEX_MSK 0x0004
#define RTL8366S_PORT_STATUS_LINK_BIT 4
#define RTL8366S_PORT_STATUS_LINK_MSK 0x0010
#define RTL8366S_PORT_STATUS_TXPAUSE_BIT 5
#define RTL8366S_PORT_STATUS_TXPAUSE_MSK 0x0020
#define RTL8366S_PORT_STATUS_RXPAUSE_BIT 6
#define RTL8366S_PORT_STATUS_RXPAUSE_MSK 0x0040
#define RTL8366S_PORT_STATUS_AN_BIT 7
#define RTL8366S_PORT_STATUS_AN_MSK 0x0080
/* internal control */
#define RTL8366S_RESET_CONTROL_REG 0x0100
#define RTL8366S_RESET_QUEUE_BIT 2
#define RTL8366S_CHIP_ID_REG 0x0105
/* MAC control */
#define RTL8366S_MAC_FORCE_CTRL0_REG 0x0F04
#define RTL8366S_MAC_FORCE_CTRL1_REG 0x0F05
/* PHY registers control */
#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
#define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
#define RTL8366S_PHY_CTRL_READ 1
#define RTL8366S_PHY_CTRL_WRITE 0
#define RTL8366S_PHY_REG_MASK 0x1F
#define RTL8366S_PHY_PAGE_OFFSET 5
#define RTL8366S_PHY_PAGE_MASK (0x7<<5)
#define RTL8366S_PHY_NO_OFFSET 9
#define RTL8366S_PHY_NO_MASK (0x1F<<9)
#define RTL8366S_PHY_NO_MAX 4
#define RTL8366S_PHY_PAGE_MAX 7
#define RTL8366S_PHY_ADDR_MAX 31
/* cpu port control reg */
#define RTL8366S_CPU_CTRL_REG 0x004F
#define RTL8366S_CPU_DRP_BIT 14
#define RTL8366S_CPU_DRP_MSK 0x4000
#define RTL8366S_CPU_INSTAG_BIT 15
#define RTL8366S_CPU_INSTAG_MSK 0x8000
/* LED registers*/
#define RTL8366S_LED_BLINK_REG 0x420
#define RTL8366S_LED_BLINKRATE_BIT 0
#define RTL8366S_LED_BLINKRATE_MSK 0x0007
#define RTL8366S_LED_INDICATED_CONF_REG 0x421
#define RTL8366S_LED_0_1_FORCE_REG 0x422
#define RTL8366S_LED_2_3_FORCE_REG 0x423
#define RTL8366S_LEDCONF_LEDFORCE 0x1F
#define RTL8366S_LED_GROUP_MAX 4
#define RTL8366S_GREEN_FEATURE_REG 0x000A
#define RTL8366S_GREEN_FEATURE_TX_BIT 3
#define RTL8366S_GREEN_FEATURE_TX_MSK 0x0008
#define RTL8366S_GREEN_FEATURE_RX_BIT 4
#define RTL8366S_GREEN_FEATURE_RX_MSK 0x0010
#define RTL8366S_MODEL_ID_REG 0x5C
#define RTL8366S_REV_ID_REG 0x5D
#define RTL8366S_MODEL_8366SR 0x6027
#define RTL8366S_MODEL_8366RB 0x5937
#endif

786
package/boot/uboot-ar71xx/src/drivers/net/phy/rtl8366_mii.c
View File

@ -1,786 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include MII_GPIOINCLUDE
#include "rtl8366.h"
#ifdef DEBUG_RTL8366
#define DBG(fmt,args...) printf (fmt ,##args)
#else
#define DBG(fmt,args...)
#endif
//-------------------------------------------------------------------
// Soft SMI functions
//-------------------------------------------------------------------
#define DELAY 2
static void smi_init(void)
{
MII_SDAINPUT;
MII_SCKINPUT;
MII_SETSDA(1);
MII_SETSCK(1);
udelay(20);
}
static void smi_start(void)
{
/*
* rtl8366 chip needs a extra clock with
* SDA high before start condition
*/
/* set gpio pins output */
MII_SDAOUTPUT;
MII_SCKOUTPUT;
udelay(DELAY);
/* set initial state: SCK:0, SDA:1 */
MII_SETSCK(0);
MII_SETSDA(1);
udelay(DELAY);
/* toggle clock */
MII_SETSCK(1);
udelay(DELAY);
MII_SETSCK(0);
udelay(DELAY);
/* start condition */
MII_SETSCK(1);
udelay(DELAY);
MII_SETSDA(0);
udelay(DELAY);
MII_SETSCK(0);
udelay(DELAY);
MII_SETSDA(1);
}
static void smi_stop(void)
{
/*
* rtl8366 chip needs a extra clock with
* SDA high after stop condition
*/
/* stop condition */
udelay(DELAY);
MII_SETSDA(0);
MII_SETSCK(1);
udelay(DELAY);
MII_SETSDA(1);
udelay(DELAY);
MII_SETSCK(1);
udelay(DELAY);
MII_SETSCK(0);
udelay(DELAY);
/* toggle clock */
MII_SETSCK(1);
udelay(DELAY);
MII_SETSCK(0);
udelay(DELAY);
MII_SETSCK(1);
/* set gpio pins input */
MII_SDAINPUT;
MII_SCKINPUT;
}
static void smi_writeBits(uint32_t data, uint8_t length)
{
uint8_t test;
for( ; length > 0; length--) {
udelay(DELAY);
/* output data */
test = (((data & (1 << (length - 1))) != 0) ? 1 : 0);
MII_SETSDA(test);
udelay(DELAY);
/* toogle clock */
MII_SETSCK(1);
udelay(DELAY);
MII_SETSCK(0);
}
}
static uint32_t smi_readBits(uint8_t length)
{
uint32_t ret;
MII_SDAINPUT;
for(ret = 0 ; length > 0; length--) {
udelay(DELAY);
ret <<= 1;
/* toogle clock */
MII_SETSCK(1);
udelay(DELAY);
ret |= MII_GETSDA;
MII_SETSCK(0);
}
MII_SDAOUTPUT;
return ret;
}
static int smi_waitAck(void)
{
uint32_t retry = 0;
while (smi_readBits(1)) {
if (retry++ == 5)
return -1;
}
return 0;
}
static int smi_read(uint32_t reg, uint32_t *data)
{
uint32_t rawData;
/* send start condition */
smi_start();
/* send CTRL1 code: 0b1010*/
smi_writeBits(0x0a, 4);
/* send CTRL2 code: 0b100 */
smi_writeBits(0x04, 3);
/* send READ command */
smi_writeBits(0x01, 1);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* send address low */
smi_writeBits(reg & 0xFF, 8);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* send address high */
smi_writeBits((reg & 0xFF00) >> 8, 8);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* read data low */
rawData = (smi_readBits(8) & 0xFF);
/* send ACK */
smi_writeBits(0, 1);
/* read data high */
rawData |= (smi_readBits(8) & 0xFF) << 8;
/* send NACK */
smi_writeBits(1, 1);
/* send stop condition */
smi_stop();
if (data)
*data = rawData;
return 0;
}
static int smi_write(uint32_t reg, uint32_t data)
{
/* send start condition */
smi_start();
/* send CTRL1 code: 0b1010*/
smi_writeBits(0x0a, 4);
/* send CTRL2 code: 0b100 */
smi_writeBits(0x04, 3);
/* send WRITE command */
smi_writeBits(0x00, 1);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* send address low */
smi_writeBits(reg & 0xFF, 8);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* send address high */
smi_writeBits((reg & 0xFF00) >> 8, 8);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* send data low */
smi_writeBits(data & 0xFF, 8);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* send data high */
smi_writeBits((data & 0xFF00) >> 8, 8);
/* wait for ACK */
if (smi_waitAck())
return -1;
/* send stop condition */
smi_stop();
return 0;
}
//-------------------------------------------------------------------
// Switch register read / write functions
//-------------------------------------------------------------------
static int rtl8366_readRegister(uint32_t reg, uint16_t *data)
{
uint32_t regData;
DBG("rtl8366: read register=%#04x, data=", reg);
if (smi_read(reg, &regData)) {
printf("\nrtl8366 smi read failed!\n");
return -1;
}
if (data)
*data = regData;
DBG("%#04x\n", regData);
return 0;
}
static int rtl8366_writeRegister(uint32_t reg, uint16_t data)
{
DBG("rtl8366: write register=%#04x, data=%#04x\n", reg, data);
if (smi_write(reg, data)) {
printf("rtl8366 smi write failed!\n");
return -1;
}
return 0;
}
static int rtl8366_setRegisterBit(uint32_t reg, uint32_t bitNum, uint32_t value)
{
uint16_t regData;
if (bitNum >= 16)
return -1;
if (rtl8366_readRegister(reg, &regData))
return -1;
if (value)
regData |= (1 << bitNum);
else
regData &= ~(1 << bitNum);
if (rtl8366_writeRegister(reg, regData))
return -1;
return 0;
}
//-------------------------------------------------------------------
// MII PHY read / write functions
//-------------------------------------------------------------------
static int rtl8366_getPhyReg(uint32_t phyNum, uint32_t reg, uint16_t *data)
{
uint16_t phyAddr, regData;
if (phyNum > RTL8366S_PHY_NO_MAX) {
printf("rtl8366s: invalid phy number!\n");
return -1;
}
if (phyNum > RTL8366S_PHY_ADDR_MAX) {
printf("rtl8366s: invalid phy register number!\n");
return -1;
}
if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
RTL8366S_PHY_CTRL_READ))
return -1;
phyAddr = 0x8000 | (1 << (phyNum + RTL8366S_PHY_NO_OFFSET))
| (reg & RTL8366S_PHY_REG_MASK);
if (rtl8366_writeRegister(phyAddr, 0))
return -1;
if (rtl8366_readRegister(RTL8366S_PHY_ACCESS_DATA_REG, &regData))
return -1;
if (data)
*data = regData;
return 0;
}
static int rtl8366_setPhyReg(uint32_t phyNum, uint32_t reg, uint16_t data)
{
uint16_t phyAddr;
if (phyNum > RTL8366S_PHY_NO_MAX) {
printf("rtl8366s: invalid phy number!\n");
return -1;
}
if (phyNum > RTL8366S_PHY_ADDR_MAX) {
printf("rtl8366s: invalid phy register number!\n");
return -1;
}
if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
RTL8366S_PHY_CTRL_WRITE))
return -1;
phyAddr = 0x8000 | (1 << (phyNum + RTL8366S_PHY_NO_OFFSET))
| (reg & RTL8366S_PHY_REG_MASK);
if (rtl8366_writeRegister(phyAddr, data))
return -1;
return 0;
}
static int rtl8366_miiread(char *devname, uchar phy_adr, uchar reg, ushort *data)
{
uint16_t regData;
DBG("rtl8366_miiread: devname=%s, addr=%#02x, reg=%#02x\n",
devname, phy_adr, reg);
if (strcmp(devname, RTL8366_DEVNAME) != 0)
return -1;
if (rtl8366_getPhyReg(phy_adr, reg, &regData)) {
printf("rtl8366_miiread: write failed!\n");
return -1;
}
if (data)
*data = regData;
return 0;
}
static int rtl8366_miiwrite(char *devname, uchar phy_adr, uchar reg, ushort data)
{
DBG("rtl8366_miiwrite: devname=%s, addr=%#02x, reg=%#02x, data=%#04x\n",
devname, phy_adr, reg, data);
if (strcmp(devname, RTL8366_DEVNAME) != 0)
return -1;
if (rtl8366_setPhyReg(phy_adr, reg, data)) {
printf("rtl8366_miiwrite: write failed!\n");
return -1;
}
return 0;
}
int rtl8366_mii_register(bd_t *bis)
{
miiphy_register(strdup(RTL8366_DEVNAME), rtl8366_miiread,
rtl8366_miiwrite);
return 0;
}
//-------------------------------------------------------------------
// Switch management functions
//-------------------------------------------------------------------
int rtl8366s_setGreenFeature(uint32_t tx, uint32_t rx)
{
if (rtl8366_setRegisterBit(RTL8366S_GREEN_FEATURE_REG,
RTL8366S_GREEN_FEATURE_TX_BIT, tx))
return -1;
if (rtl8366_setRegisterBit(RTL8366S_GREEN_FEATURE_REG,
RTL8366S_GREEN_FEATURE_RX_BIT, rx))
return -1;
return 0;
}
int rtl8366s_setPowerSaving(uint32_t phyNum, uint32_t enabled)
{
uint16_t regData;
if (phyNum > RTL8366S_PHY_NO_MAX)
return -1;
if (rtl8366_getPhyReg(phyNum, 12, &regData))
return -1;
if (enabled)
regData |= (1 << 12);
else
regData &= ~(1 << 12);
if (rtl8366_setPhyReg(phyNum, 12, regData))
return -1;
return 0;
}
int rtl8366s_setGreenEthernet(uint32_t greenFeature, uint32_t powerSaving)
{
uint32_t phyNum, i;
uint16_t regData;
const uint16_t greenSettings[][2] =
{
{0xBE5B,0x3500},
{0xBE5C,0xB975},
{0xBE5D,0xB9B9},
{0xBE77,0xA500},
{0xBE78,0x5A78},
{0xBE79,0x6478}
};
if (rtl8366_readRegister(RTL8366S_MODEL_ID_REG, &regData))
return -1;
switch (regData)
{
case 0x0000:
for (i = 0; i < 6; i++) {
if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG, RTL8366S_PHY_CTRL_WRITE))
return -1;
if (rtl8366_writeRegister(greenSettings[i][0], greenSettings[i][1]))
return -1;
}
break;
case RTL8366S_MODEL_8366SR:
if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG, RTL8366S_PHY_CTRL_WRITE))
return -1;
if (rtl8366_writeRegister(greenSettings[0][0], greenSettings[0][1]))
return -1;
break;
default:
printf("rtl8366s_initChip: unsupported chip found!\n");
return -1;
}
if (rtl8366s_setGreenFeature(greenFeature, powerSaving))
return -1;
for (phyNum = 0; phyNum <= RTL8366S_PHY_NO_MAX; phyNum++) {
if (rtl8366s_setPowerSaving(phyNum, powerSaving))
return -1;
}
return 0;
}
int rtl8366s_setCPUPortMask(uint8_t port, uint32_t enabled)
{
if(port >= 6){
printf("rtl8366s_setCPUPortMask: invalid port number\n");
return -1;
}
return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG, port, enabled);
}
int rtl8366s_setCPUDisableInsTag(uint32_t enable)
{
return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG,
RTL8366S_CPU_INSTAG_BIT, enable);
}
int rtl8366s_setCPUDropUnda(uint32_t enable)
{
return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG,
RTL8366S_CPU_DRP_BIT, enable);
}
int rtl8366s_setCPUPort(uint8_t port, uint32_t noTag, uint32_t dropUnda)
{
uint32_t i;
if(port >= 6){
printf("rtl8366s_setCPUPort: invalid port number\n");
return -1;
}
/* reset register */
for(i = 0; i < 6; i++)
{
if(rtl8366s_setCPUPortMask(i, 0)){
printf("rtl8366s_setCPUPort: rtl8366s_setCPUPortMask failed\n");
return -1;
}
}
if(rtl8366s_setCPUPortMask(port, 1)){
printf("rtl8366s_setCPUPort: rtl8366s_setCPUPortMask failed\n");
return -1;
}
if(rtl8366s_setCPUDisableInsTag(noTag)){
printf("rtl8366s_setCPUPort: rtl8366s_setCPUDisableInsTag fail\n");
return -1;
}
if(rtl8366s_setCPUDropUnda(dropUnda)){
printf("rtl8366s_setCPUPort: rtl8366s_setCPUDropUnda fail\n");
return -1;
}
return 0;
}
int rtl8366s_setLedConfig(uint32_t ledNum, uint8_t config)
{
uint16_t regData;
if(ledNum >= RTL8366S_LED_GROUP_MAX) {
DBG("rtl8366s_setLedConfig: invalid led group\n");
return -1;
}
if(config > RTL8366S_LEDCONF_LEDFORCE) {
DBG("rtl8366s_setLedConfig: invalid led config\n");
return -1;
}
if (rtl8366_readRegister(RTL8366S_LED_INDICATED_CONF_REG, &regData)) {
printf("rtl8366s_setLedConfig: failed to get led register!\n");
return -1;
}
regData &= ~(0xF << (ledNum * 4));
regData |= config << (ledNum * 4);
if (rtl8366_writeRegister(RTL8366S_LED_INDICATED_CONF_REG, regData)) {
printf("rtl8366s_setLedConfig: failed to set led register!\n");
return -1;
}
return 0;
}
int rtl8366s_getLedConfig(uint32_t ledNum, uint8_t *config)
{
uint16_t regData;
if(ledNum >= RTL8366S_LED_GROUP_MAX) {
DBG("rtl8366s_getLedConfig: invalid led group\n");
return -1;
}
if (rtl8366_readRegister(RTL8366S_LED_INDICATED_CONF_REG, &regData)) {
printf("rtl8366s_getLedConfig: failed to get led register!\n");
return -1;
}
if (config)
*config = (regData >> (ledNum * 4)) & 0xF;
return 0;
}
int rtl8366s_setLedForceValue(uint32_t group0, uint32_t group1,
uint32_t group2, uint32_t group3)
{
uint16_t regData;
regData = (group0 & 0x3F) | ((group1 & 0x3F) << 6);
if (rtl8366_writeRegister(RTL8366S_LED_0_1_FORCE_REG, regData)) {
printf("rtl8366s_setLedForceValue: failed to set led register!\n");
return -1;
}
regData = (group2 & 0x3F) | ((group3 & 0x3F) << 6);
if (rtl8366_writeRegister(RTL8366S_LED_2_3_FORCE_REG, regData)) {
printf("rtl8366s_setLedForceValue: failed to set led register!\n");
return -1;
}
return 0;
}
int rtl8366s_initChip(void)
{
uint32_t ledGroup, i = 0;
uint16_t regData;
uint8_t ledData[RTL8366S_LED_GROUP_MAX];
const uint16_t (*chipData)[2];
const uint16_t chipB[][2] =
{
{0x0000, 0x0038},{0x8100, 0x1B37},{0xBE2E, 0x7B9F},{0xBE2B, 0xA4C8},
{0xBE74, 0xAD14},{0xBE2C, 0xDC00},{0xBE69, 0xD20F},{0xBE3B, 0xB414},
{0xBE24, 0x0000},{0xBE23, 0x00A1},{0xBE22, 0x0008},{0xBE21, 0x0120},
{0xBE20, 0x1000},{0xBE24, 0x0800},{0xBE24, 0x0000},{0xBE24, 0xF000},
{0xBE23, 0xDF01},{0xBE22, 0xDF20},{0xBE21, 0x101A},{0xBE20, 0xA0FF},
{0xBE24, 0xF800},{0xBE24, 0xF000},{0x0242, 0x02BF},{0x0245, 0x02BF},
{0x0248, 0x02BF},{0x024B, 0x02BF},{0x024E, 0x02BF},{0x0251, 0x02BF},
{0x0230, 0x0A32},{0x0233, 0x0A32},{0x0236, 0x0A32},{0x0239, 0x0A32},
{0x023C, 0x0A32},{0x023F, 0x0A32},{0x0254, 0x0A3F},{0x0255, 0x0064},
{0x0256, 0x0A3F},{0x0257, 0x0064},{0x0258, 0x0A3F},{0x0259, 0x0064},
{0x025A, 0x0A3F},{0x025B, 0x0064},{0x025C, 0x0A3F},{0x025D, 0x0064},
{0x025E, 0x0A3F},{0x025F, 0x0064},{0x0260, 0x0178},{0x0261, 0x01F4},
{0x0262, 0x0320},{0x0263, 0x0014},{0x021D, 0x9249},{0x021E, 0x0000},
{0x0100, 0x0004},{0xBE4A, 0xA0B4},{0xBE40, 0x9C00},{0xBE41, 0x501D},
{0xBE48, 0x3602},{0xBE47, 0x8051},{0xBE4C, 0x6465},{0x8000, 0x1F00},
{0x8001, 0x000C},{0x8008, 0x0000},{0x8007, 0x0000},{0x800C, 0x00A5},
{0x8101, 0x02BC},{0xBE53, 0x0005},{0x8E45, 0xAFE8},{0x8013, 0x0005},
{0xBE4B, 0x6700},{0x800B, 0x7000},{0xBE09, 0x0E00},
{0xFFFF, 0xABCD}
};
const uint16_t chipDefault[][2] =
{
{0x0242, 0x02BF},{0x0245, 0x02BF},{0x0248, 0x02BF},{0x024B, 0x02BF},
{0x024E, 0x02BF},{0x0251, 0x02BF},
{0x0254, 0x0A3F},{0x0256, 0x0A3F},{0x0258, 0x0A3F},{0x025A, 0x0A3F},
{0x025C, 0x0A3F},{0x025E, 0x0A3F},
{0x0263, 0x007C},{0x0100, 0x0004},
{0xBE5B, 0x3500},{0x800E, 0x200F},{0xBE1D, 0x0F00},{0x8001, 0x5011},
{0x800A, 0xA2F4},{0x800B, 0x17A3},{0xBE4B, 0x17A3},{0xBE41, 0x5011},
{0xBE17, 0x2100},{0x8000, 0x8304},{0xBE40, 0x8304},{0xBE4A, 0xA2F4},
{0x800C, 0xA8D5},{0x8014, 0x5500},{0x8015, 0x0004},{0xBE4C, 0xA8D5},
{0xBE59, 0x0008},{0xBE09, 0x0E00},{0xBE36, 0x1036},{0xBE37, 0x1036},
{0x800D, 0x00FF},{0xBE4D, 0x00FF},
{0xFFFF, 0xABCD}
};
DBG("rtl8366s_initChip\n");
/* save current led config and set to led force */
for (ledGroup = 0; ledGroup < RTL8366S_LED_GROUP_MAX; ledGroup++) {
if (rtl8366s_getLedConfig(ledGroup, &ledData[ledGroup]))
return -1;
if (rtl8366s_setLedConfig(ledGroup, RTL8366S_LEDCONF_LEDFORCE))
return -1;
}
if (rtl8366s_setLedForceValue(0,0,0,0))
return -1;
if (rtl8366_readRegister(RTL8366S_MODEL_ID_REG, &regData))
return -1;
switch (regData)
{
case 0x0000:
chipData = chipB;
break;
case RTL8366S_MODEL_8366SR:
chipData = chipDefault;
break;
default:
printf("rtl8366s_initChip: unsupported chip found!\n");
return -1;
}
DBG("rtl8366s_initChip: found %x chip\n", regData);
while ((chipData[i][0] != 0xFFFF) && (chipData[i][1] != 0xABCD)) {
/* phy settings*/
if ((chipData[i][0] & 0xBE00) == 0xBE00) {
if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
RTL8366S_PHY_CTRL_WRITE))
return -1;
}
if (rtl8366_writeRegister(chipData[i][0], chipData[i][1]))
return -1;
i++;
}
/* chip needs some time */
udelay(100 * 1000);
/* restore led config */
for (ledGroup = 0; ledGroup < RTL8366S_LED_GROUP_MAX; ledGroup++) {
if (rtl8366s_setLedConfig(ledGroup, ledData[ledGroup]))
return -1;
}
return 0;
}
int rtl8366s_initialize(void)
{
uint16_t regData;
DBG("rtl8366s_initialize: start setup\n");
smi_init();
rtl8366_readRegister(RTL8366S_CHIP_ID_REG, &regData);
DBG("Realtek 8366SR switch ID %#04x\n", regData);
if (regData != 0x8366) {
printf("rtl8366s_initialize: found unsupported switch\n");
return -1;
}
if (rtl8366s_initChip()) {
printf("rtl8366s_initialize: init chip failed\n");
return -1;
}
if (rtl8366s_setGreenEthernet(1, 1)) {
printf("rtl8366s_initialize: set green ethernet failed\n");
return -1;
}
/* Set port 5 noTag and don't dropUnda */
if (rtl8366s_setCPUPort(5, 1, 0)) {
printf("rtl8366s_initialize: set CPU port failed\n");
return -1;
}
return 0;
}

191
package/boot/uboot-ar71xx/src/drivers/spi/ar71xx_spi.c
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@ -1,191 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <asm/ar71xx.h>
/*-----------------------------------------------------------------------
* Definitions
*/
#ifdef DEBUG_SPI
#define PRINTD(fmt,args...) printf (fmt ,##args)
#else
#define PRINTD(fmt,args...)
#endif
struct ar71xx_spi_slave {
struct spi_slave slave;
unsigned int mode;
};
static inline struct ar71xx_spi_slave *to_ar71xx_spi(struct spi_slave *slave)
{
return container_of(slave, struct ar71xx_spi_slave, slave);
}
/*=====================================================================*/
/* Public Functions */
/*=====================================================================*/
/*-----------------------------------------------------------------------
* Initialization
*/
void spi_init()
{
PRINTD("ar71xx_spi: spi_init");
// Init SPI Hardware, disable remap, set clock
__raw_writel(0x43, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_CTRL));
PRINTD(" ---> out\n");
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct ar71xx_spi_slave *ss;
PRINTD("ar71xx_spi: spi_setup_slave");
if ((bus != 0) || (cs > 2))
return NULL;
ss = malloc(sizeof(struct ar71xx_spi_slave));
if (!ss)
return NULL;
ss->slave.bus = bus;
ss->slave.cs = cs;
ss->mode = mode;
/* TODO: Use max_hz to limit the SCK rate */
PRINTD(" ---> out\n");
return &ss->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave);
free(ss);
}
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave);
uint8_t *rx = din;
const uint8_t *tx = dout;
uint8_t curbyte, curbitlen, restbits;
uint32_t bytes = bitlen / 8;
uint32_t out;
uint32_t in;
PRINTD("ar71xx_spi: spi_xfer: slave:%p bitlen:%08x dout:%p din:%p flags:%08x\n", slave, bitlen, dout, din, flags);
if (flags & SPI_XFER_BEGIN) {
__raw_writel(SPI_FS_GPIO, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_FS));
__raw_writel(SPI_IOC_CS_ALL, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
}
restbits = (bitlen % 8);
if (restbits != 0)
bytes++;
// enable chip select
out = SPI_IOC_CS_ALL & ~(SPI_IOC_CS(slave->cs));
while (bytes--) {
curbyte = 0;
if (tx) {
curbyte = *tx++;
}
if (restbits != 0) {
curbitlen = restbits;
curbyte <<= 8 - restbits;
} else {
curbitlen = 8;
}
PRINTD("ar71xx_spi: sending: data:%02x length:%d\n", curbyte, curbitlen);
/* clock starts at inactive polarity */
for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
if (curbyte & (1 << 7))
out |= SPI_IOC_DO;
else
out &= ~(SPI_IOC_DO);
/* setup MSB (to slave) on trailing edge */
__raw_writel(out, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
__raw_writel(out | SPI_IOC_CLK, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
curbyte <<= 1;
}
in = __raw_readl(KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_RDS));
PRINTD("ar71xx_spi: received:%02x\n", in);
if (rx) {
if (restbits == 0) {
*rx++ = in;
} else {
*rx++ = (in << (8 - restbits));
}
}
}
if (flags & SPI_XFER_END) {
__raw_writel(SPI_IOC_CS(slave->cs), KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
__raw_writel(SPI_IOC_CS_ALL, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
__raw_writel(0, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_FS));
}
PRINTD(" ---> out\n");
return 0;
}

515
package/boot/uboot-ar71xx/src/include/asm-mips/ar71xx.h
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@ -1,515 +0,0 @@
/*
* Atheros AR71xx SoC specific definitions
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_AR71XX_H
#define __ASM_MACH_AR71XX_H
#include <linux/types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#ifndef __ASSEMBLER__
#define BIT(x) (1<<(x))
#define AR71XX_PCI_MEM_BASE 0x10000000
#define AR71XX_PCI_MEM_SIZE 0x08000000
#define AR71XX_APB_BASE 0x18000000
#define AR71XX_GE0_BASE 0x19000000
#define AR71XX_GE0_SIZE 0x01000000
#define AR71XX_GE1_BASE 0x1a000000
#define AR71XX_GE1_SIZE 0x01000000
#define AR71XX_EHCI_BASE 0x1b000000
#define AR71XX_EHCI_SIZE 0x01000000
#define AR71XX_OHCI_BASE 0x1c000000
#define AR71XX_OHCI_SIZE 0x01000000
#define AR7240_OHCI_BASE 0x1b000000
#define AR7240_OHCI_SIZE 0x01000000
#define AR71XX_SPI_BASE 0x1f000000
#define AR71XX_SPI_SIZE 0x01000000
#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
#define AR71XX_DDR_CTRL_SIZE 0x10000
#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR71XX_UART_SIZE 0x10000
#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
#define AR71XX_USB_CTRL_SIZE 0x10000
#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
#define AR71XX_GPIO_SIZE 0x10000
#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
#define AR71XX_PLL_SIZE 0x10000
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
#define AR71XX_RESET_SIZE 0x10000
#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
#define AR71XX_MII_SIZE 0x10000
#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
#define AR71XX_SLIC_SIZE 0x10000
#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
#define AR71XX_DMA_SIZE 0x10000
#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
#define AR71XX_STEREO_SIZE 0x10000
#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR724X_PCI_CRP_SIZE 0x100
#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
#define AR724X_PCI_CTRL_SIZE 0x100
#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR91XX_WMAC_SIZE 0x30000
#define AR71XX_MEM_SIZE_MIN 0x0200000
#define AR71XX_MEM_SIZE_MAX 0x10000000
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
#define AR71XX_MISC_IRQ_COUNT 8
#define AR71XX_GPIO_IRQ_BASE 16
#define AR71XX_GPIO_IRQ_COUNT 32
#define AR71XX_PCI_IRQ_BASE 48
#define AR71XX_PCI_IRQ_COUNT 8
#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
extern u32 ar71xx_ahb_freq;
extern u32 ar71xx_cpu_freq;
extern u32 ar71xx_ddr_freq;
enum ar71xx_soc_type {
AR71XX_SOC_UNKNOWN,
AR71XX_SOC_AR7130,
AR71XX_SOC_AR7141,
AR71XX_SOC_AR7161,
AR71XX_SOC_AR7240,
AR71XX_SOC_AR7241,
AR71XX_SOC_AR7242,
AR71XX_SOC_AR9130,
AR71XX_SOC_AR9132
};
extern enum ar71xx_soc_type ar71xx_soc;
/*
* PLL block
*/
#define AR71XX_PLL_REG_CPU_CONFIG 0x00
#define AR71XX_PLL_REG_SEC_CONFIG 0x04
#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
#define AR71XX_PLL_DIV_SHIFT 3
#define AR71XX_PLL_DIV_MASK 0x1f
#define AR71XX_CPU_DIV_SHIFT 16
#define AR71XX_CPU_DIV_MASK 0x3
#define AR71XX_DDR_DIV_SHIFT 18
#define AR71XX_DDR_DIV_MASK 0x3
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
#define AR71XX_ETH0_PLL_SHIFT 17
#define AR71XX_ETH1_PLL_SHIFT 19
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
#define AR724X_PLL_DIV_SHIFT 0
#define AR724X_PLL_DIV_MASK 0x3ff
#define AR724X_PLL_REF_DIV_SHIFT 10
#define AR724X_PLL_REF_DIV_MASK 0xf
#define AR724X_AHB_DIV_SHIFT 19
#define AR724X_AHB_DIV_MASK 0x1
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
#define AR91XX_PLL_REG_CPU_CONFIG 0x00
#define AR91XX_PLL_REG_ETH_CONFIG 0x04
#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
#define AR91XX_PLL_DIV_SHIFT 0
#define AR91XX_PLL_DIV_MASK 0x3ff
#define AR91XX_DDR_DIV_SHIFT 22
#define AR91XX_DDR_DIV_MASK 0x3
#define AR91XX_AHB_DIV_SHIFT 19
#define AR91XX_AHB_DIV_MASK 0x1
#define AR91XX_ETH0_PLL_SHIFT 20
#define AR91XX_ETH1_PLL_SHIFT 22
// extern void __iomem *ar71xx_pll_base;
// static inline void ar71xx_pll_wr(unsigned reg, u32 val)
// {
// __raw_writel(val, ar71xx_pll_base + reg);
// }
// static inline u32 ar71xx_pll_rr(unsigned reg)
// {
// return __raw_readl(ar71xx_pll_base + reg);
// }
/*
* USB_CONFIG block
*/
#define USB_CTRL_REG_FLADJ 0x00
#define USB_CTRL_REG_CONFIG 0x04
// extern void __iomem *ar71xx_usb_ctrl_base;
// static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
// {
// __raw_writel(val, ar71xx_usb_ctrl_base + reg);
// }
// static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
// {
// return __raw_readl(ar71xx_usb_ctrl_base + reg);
// }
/*
* GPIO block
*/
#define GPIO_REG_OE 0x00
#define GPIO_REG_IN 0x04
#define GPIO_REG_OUT 0x08
#define GPIO_REG_SET 0x0c
#define GPIO_REG_CLEAR 0x10
#define GPIO_REG_INT_MODE 0x14
#define GPIO_REG_INT_TYPE 0x18
#define GPIO_REG_INT_POLARITY 0x1c
#define GPIO_REG_INT_PENDING 0x20
#define GPIO_REG_INT_ENABLE 0x24
#define GPIO_REG_FUNC 0x28
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
#define AR71XX_GPIO_COUNT 16
#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
#define AR724X_GPIO_FUNC_UART_EN BIT(1)
#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
#define AR724X_GPIO_COUNT 18
#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
#define AR91XX_GPIO_FUNC_UART_EN BIT(8)
#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
#define AR91XX_GPIO_COUNT 22
// extern void __iomem *ar71xx_gpio_base;
// static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
// {
// __raw_writel(value, ar71xx_gpio_base + reg);
// }
// static inline u32 ar71xx_gpio_rr(unsigned reg)
// {
// return __raw_readl(ar71xx_gpio_base + reg);
// }
// void ar71xx_gpio_init(void) __init;
// void ar71xx_gpio_function_enable(u32 mask);
// void ar71xx_gpio_function_disable(u32 mask);
// void ar71xx_gpio_function_setup(u32 set, u32 clear);
/*
* DDR_CTRL block
*/
#define AR71XX_DDR_REG_PCI_WIN0 0x7c
#define AR71XX_DDR_REG_PCI_WIN1 0x80
#define AR71XX_DDR_REG_PCI_WIN2 0x84
#define AR71XX_DDR_REG_PCI_WIN3 0x88
#define AR71XX_DDR_REG_PCI_WIN4 0x8c
#define AR71XX_DDR_REG_PCI_WIN5 0x90
#define AR71XX_DDR_REG_PCI_WIN6 0x94
#define AR71XX_DDR_REG_PCI_WIN7 0x98
#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
#define AR71XX_DDR_REG_FLUSH_USB 0xa4
#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
#define AR724X_DDR_REG_FLUSH_GE0 0x7c
#define AR724X_DDR_REG_FLUSH_GE1 0x80
#define AR724X_DDR_REG_FLUSH_USB 0x84
#define AR724X_DDR_REG_FLUSH_PCIE 0x88
#define AR91XX_DDR_REG_FLUSH_GE0 0x7c
#define AR91XX_DDR_REG_FLUSH_GE1 0x80
#define AR91XX_DDR_REG_FLUSH_USB 0x84
#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
#define PCI_WIN0_OFFS 0x10000000
#define PCI_WIN1_OFFS 0x11000000
#define PCI_WIN2_OFFS 0x12000000
#define PCI_WIN3_OFFS 0x13000000
#define PCI_WIN4_OFFS 0x14000000
#define PCI_WIN5_OFFS 0x15000000
#define PCI_WIN6_OFFS 0x16000000
#define PCI_WIN7_OFFS 0x07000000
// extern void __iomem *ar71xx_ddr_base;
// static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
// {
// __raw_writel(val, ar71xx_ddr_base + reg);
// }
// static inline u32 ar71xx_ddr_rr(unsigned reg)
// {
// return __raw_readl(ar71xx_ddr_base + reg);
// }
// void ar71xx_ddr_flush(u32 reg);
/*
* PCI block
*/
#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
#define AR71XX_PCI_CFG_SIZE 0x100
#define PCI_REG_CRP_AD_CBE 0x00
#define PCI_REG_CRP_WRDATA 0x04
#define PCI_REG_CRP_RDDATA 0x08
#define PCI_REG_CFG_AD 0x0c
#define PCI_REG_CFG_CBE 0x10
#define PCI_REG_CFG_WRDATA 0x14
#define PCI_REG_CFG_RDDATA 0x18
#define PCI_REG_PCI_ERR 0x1c
#define PCI_REG_PCI_ERR_ADDR 0x20
#define PCI_REG_AHB_ERR 0x24
#define PCI_REG_AHB_ERR_ADDR 0x28
#define PCI_CRP_CMD_WRITE 0x00010000
#define PCI_CRP_CMD_READ 0x00000000
#define PCI_CFG_CMD_READ 0x0000000a
#define PCI_CFG_CMD_WRITE 0x0000000b
#define PCI_IDSEL_ADL_START 17
#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
#define AR724X_PCI_CFG_SIZE 0x1000
#define AR724X_PCI_REG_APP 0x00
#define AR724X_PCI_REG_RESET 0x18
#define AR724X_PCI_REG_INT_STATUS 0x4c
#define AR724X_PCI_REG_INT_MASK 0x50
#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
#define AR724X_PCI_RESET_LINK_UP BIT(0)
#define AR724X_PCI_INT_DEV0 BIT(14)
/*
* RESET block
*/
#define AR71XX_RESET_REG_TIMER 0x00
#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
#define AR71XX_RESET_REG_WDOG_CTRL 0x08
#define AR71XX_RESET_REG_WDOG 0x0c
#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
#define AR71XX_RESET_REG_RESET_MODULE 0x24
#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
#define AR71XX_RESET_REG_PERFC0 0x30
#define AR71XX_RESET_REG_PERFC1 0x34
#define AR71XX_RESET_REG_REV_ID 0x90
#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
#define AR91XX_RESET_REG_RESET_MODULE 0x1c
#define AR91XX_RESET_REG_PERF_CTRL 0x20
#define AR91XX_RESET_REG_PERFC0 0x24
#define AR91XX_RESET_REG_PERFC1 0x28
#define AR724X_RESET_REG_RESET_MODULE 0x1c
#define WDOG_CTRL_LAST_RESET BIT(31)
#define WDOG_CTRL_ACTION_MASK 3
#define WDOG_CTRL_ACTION_NONE 0 /* no action */
#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
#define MISC_INT_DMA BIT(7)
#define MISC_INT_OHCI BIT(6)
#define MISC_INT_PERFC BIT(5)
#define MISC_INT_WDOG BIT(4)
#define MISC_INT_UART BIT(3)
#define MISC_INT_GPIO BIT(2)
#define MISC_INT_ERROR BIT(1)
#define MISC_INT_TIMER BIT(0)
#define PCI_INT_CORE BIT(4)
#define PCI_INT_DEV2 BIT(2)
#define PCI_INT_DEV1 BIT(1)
#define PCI_INT_DEV0 BIT(0)
#define RESET_MODULE_EXTERNAL BIT(28)
#define RESET_MODULE_FULL_CHIP BIT(24)
#define RESET_MODULE_AMBA2WMAC BIT(22)
#define RESET_MODULE_CPU_NMI BIT(21)
#define RESET_MODULE_CPU_COLD BIT(20)
#define RESET_MODULE_DMA BIT(19)
#define RESET_MODULE_SLIC BIT(18)
#define RESET_MODULE_STEREO BIT(17)
#define RESET_MODULE_DDR BIT(16)
#define RESET_MODULE_GE1_MAC BIT(13)
#define RESET_MODULE_GE1_PHY BIT(12)
#define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
#define RESET_MODULE_GE0_MAC BIT(9)
#define RESET_MODULE_GE0_PHY BIT(8)
#define RESET_MODULE_USB_OHCI_DLL BIT(6)
#define RESET_MODULE_USB_HOST BIT(5)
#define RESET_MODULE_USB_PHY BIT(4)
#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
#define RESET_MODULE_PCI_BUS BIT(1)
#define RESET_MODULE_PCI_CORE BIT(0)
#define AR724X_RESET_GE1_MDIO BIT(23)
#define AR724X_RESET_GE0_MDIO BIT(22)
#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
#define AR724X_RESET_PCIE_PHY BIT(7)
#define AR724X_RESET_PCIE BIT(6)
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
#define REV_ID_MAJOR_AR7240 0x00c0
#define REV_ID_MAJOR_AR7241 0x0100
#define REV_ID_MAJOR_AR7242 0x1100
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
#define AR71XX_REV_ID_MINOR_AR7141 0x1
#define AR71XX_REV_ID_MINOR_AR7161 0x2
#define AR71XX_REV_ID_REVISION_MASK 0x3
#define AR71XX_REV_ID_REVISION_SHIFT 2
#define AR91XX_REV_ID_MINOR_MASK 0x3
#define AR91XX_REV_ID_MINOR_AR9130 0x0
#define AR91XX_REV_ID_MINOR_AR9132 0x1
#define AR91XX_REV_ID_REVISION_MASK 0x3
#define AR91XX_REV_ID_REVISION_SHIFT 2
#define AR724X_REV_ID_REVISION_MASK 0x3
// extern void __iomem *ar71xx_reset_base;
static inline void ar71xx_reset_wr(unsigned reg, u32 val)
{
__raw_writel(val, KSEG1ADDR(AR71XX_RESET_BASE) + reg);
}
static inline u32 ar71xx_reset_rr(unsigned reg)
{
return __raw_readl(KSEG1ADDR(AR71XX_RESET_BASE) + reg);
}
// void ar71xx_device_stop(u32 mask);
// void ar71xx_device_start(u32 mask);
// int ar71xx_device_stopped(u32 mask);
/*
* SPI block
*/
#define SPI_REG_FS 0x00 /* Function Select */
#define SPI_REG_CTRL 0x04 /* SPI Control */
#define SPI_REG_IOC 0x08 /* SPI I/O Control */
#define SPI_REG_RDS 0x0c /* Read Data Shift */
#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
#define SPI_CTRL_RD BIT(6) /* Remap Disable */
#define SPI_CTRL_DIV_MASK 0x3f
#define SPI_IOC_DO BIT(0) /* Data Out pin */
#define SPI_IOC_CLK BIT(8) /* CLK pin */
#define SPI_IOC_CS(n) BIT(16 + (n))
#define SPI_IOC_CS0 SPI_IOC_CS(0)
#define SPI_IOC_CS1 SPI_IOC_CS(1)
#define SPI_IOC_CS2 SPI_IOC_CS(2)
#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
// void ar71xx_flash_acquire(void);
// void ar71xx_flash_release(void);
/*
* MII_CTRL block
*/
#define MII_REG_MII0_CTRL 0x00
#define MII_REG_MII1_CTRL 0x04
#define MII0_CTRL_IF_GMII 0
#define MII0_CTRL_IF_MII 1
#define MII0_CTRL_IF_RGMII 2
#define MII0_CTRL_IF_RMII 3
#define MII1_CTRL_IF_RGMII 0
#define MII1_CTRL_IF_RMII 1
#endif /* __ASSEMBLER__ */
#endif /* __ASM_MACH_AR71XX_H */

65
package/boot/uboot-ar71xx/src/include/asm-mips/ar71xx_gpio.h
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@ -1,65 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _AR71XX_GPIO_H
#define _AR71XX_GPIO_H
#include <common.h>
#include <asm/ar71xx.h>
static inline void ar71xx_setpin(uint8_t pin, uint8_t state)
{
uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
if (state != 0) {
reg |= (1 << pin);
} else {
reg &= ~(1 << pin);
}
writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
}
static inline uint32_t ar71xx_getpin(uint8_t pin)
{
uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_IN));
return (((reg & (1 << pin)) != 0) ? 1 : 0);
}
static inline void ar71xx_setpindir(uint8_t pin, uint8_t direction)
{
uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
if (direction != 0) {
reg |= (1 << pin);
} else {
reg &= ~(1 << pin);
}
writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
}
#endif /* AR71XX_GPIO_H */

136
package/boot/uboot-ar71xx/src/include/configs/nbg460n.h
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@ -1,136 +0,0 @@
/*
* (C) Copyright 2010
* Michael Kurz <michi.kurz@googlemail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This file contains the configuration parameters for the zyxel nbg460n board. */
#ifndef _NBG460N_CONFIG_H
#define _NBG460N_CONFIG_H
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_AR71XX 1
#define CONFIG_AR91XX 1
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MIPS_TIMER_FREQ (400000000/2)
/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE 32768
#define CONFIG_SYS_ICACHE_SIZE 65536
#define CONFIG_SYS_CACHELINE_SIZE 32
/* Cache lock for stack */
#define CONFIG_SYS_INIT_SP_OFFSET 0x1000
#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {115200}
#define CONFIG_MISC_INIT_R
/* SPI-Flash support */
#define CONFIG_SPI_FLASH
#define CONFIG_AR71XX_SPI
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_SF_DEFAULT_HZ 25000000
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_ADDR 0xbfc20000
#define CONFIG_ENV_OFFSET 0x20000
#define CONFIG_ENV_SIZE 0x01000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 64
#define CONFIG_SYS_FLASH_BASE 0xbfc00000
/* Net support */
#define CONFIG_ETHADDR_ADDR 0xbfc0fff8
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_AG71XX
#define CONFIG_AG71XX_PORTS { 1, 1 }
#define CONFIG_AG71XX_MII0_IIF MII0_CTRL_IF_RGMII
#define CONFIG_AG71XX_MII1_IIF MII1_CTRL_IF_RGMII
#define CONFIG_NET_MULTI
#define CONFIG_IPADDR 192.168.1.254
#define CONFIG_SERVERIP 192.168.1.42
/* Switch support */
#define CONFIG_MII
#define CONFIG_RTL8366_MII
#define RTL8366_PIN_SDA 16
#define RTL8366_PIN_SCK 18
#define MII_GPIOINCLUDE <asm/ar71xx_gpio.h>
#define MII_SETSDA(x) ar71xx_setpin(RTL8366_PIN_SDA, x)
#define MII_GETSDA ar71xx_getpin(RTL8366_PIN_SDA)
#define MII_SETSCK(x) ar71xx_setpin(RTL8366_PIN_SCK, x)
#define MII_SDAINPUT ar71xx_setpindir(RTL8366_PIN_SDA, 0)
#define MII_SDAOUTPUT ar71xx_setpindir(RTL8366_PIN_SDA, 1)
#define MII_SCKINPUT ar71xx_setpindir(RTL8366_PIN_SCK, 0)
#define MII_SCKOUTPUT ar71xx_setpindir(RTL8366_PIN_SCK, 1)
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,115200 rootfstype==squashfs,jffs2 noinitrd machtype=NBG460N"
#define CONFIG_BOOTCOMMAND "bootm 0xbfc70000"
#define CONFIG_LZMA
/* Commands */
#define CONFIG_SYS_NO_FLASH
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_SF
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SPI
/* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * 0x10000 + 128*1024, 0x1000)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_LOAD_ADDR 0x80060000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x80000800
#define CONFIG_SYS_MEMTEST_END 0x81E00000
#endif /* _NBG460N_CONFIG_H */

115
package/boot/uboot-envtools/files/ar71xx
View File

@ -1,115 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2011-2014 OpenWrt.org
#
[ -e /etc/config/ubootenv ] && exit 0
touch /etc/config/ubootenv
. /lib/uboot-envtools.sh
. /lib/functions.sh
board=$(board_name)
case "$board" in
a40|\
a60|\
alfa-ap120c|\
all0258n|\
ap121f|\
ap90q|\
ap91-5g|\
arduino-yun|\
cap324|\
cap4200ag|\
carambola2|\
cpe830|\
cpe870|\
cr3000|\
cr5000|\
dw33d|\
e1700ac-v2|\
e600g-v2|\
e600gac-v2|\
eap300v2|\
ens202ext|\
gl-ar300m|\
gl-ar750|\
hornet-ub|\
hornet-ub-x2|\
jwap230|\
koala|\
mr1750|\
mr1750v2|\
mr600|\
mr600v2|\
mr900|\
mr900v2|\
n5q|\
nbg6616|\
nbg6716|\
om5p|\
om5p-ac|\
om5p-acv2|\
om5p-an|\
r36a|\
rme-eg200|\
sr3200|\
t830|\
tube2h|\
wam250|\
wnr1000-v2|\
wnr2000-v3|\
wnr2200|\
wnr612-v2|\
xd3200)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x10000"
;;
alfa-ap96|\
all0315n|\
om2p|\
om2p-hs|\
om2p-hsv2|\
om2p-hsv3|\
om2p-hsv4|\
om2p-lc|\
om2pv2|\
om2pv4)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x40000"
;;
dap-2695-a1|\
wzr-hp-ag300h)
ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000" "0x10000"
;;
dr342|\
dr531)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0xf800" "0x10000"
;;
gl-ar150|\
gl-domino|\
gl-mifi)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x8000" "0x10000"
;;
rambutan)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
ubootenv_add_uci_config "/dev/mtd1" "0x100000" "0x20000" "0x20000"
;;
qihoo-c301)
ubootenv_add_uci_config "/dev/mtd9" "0x0" "0x10000" "0x10000"
;;
wi2a-ac200i)
ubootenv_add_uci_config "/dev/mtd4" "0x0" "0x8000" "0x10000"
;;
wndr3700)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x10000"
;;
wndr4300)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x20000"
;;
esac
config_load ubootenv
config_foreach ubootenv_add_app_config ubootenv
exit 0

68
package/firmware/vsc73x5-ucode/Makefile
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@ -1,68 +0,0 @@
#
# Copyright (C) 2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=vsc73x5-ucode
PKG_RELEASE:=1
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
PKG_SOURCE:=vsc73x5-ucode.tar.bz2
PKG_BUILD_DIR:=$(BUILD_DIR)/vsc73x5-ucode
PKG_HASH:=9728cec2b5d49ddd52578a8c600f1fd9f878a34e7e00ed51c248e0d608dd763a
PKG_FLAGS:=nonshared
include $(INCLUDE_DIR)/package.mk
define Package/vsc73x5-defaults
SECTION:=net
CATEGORY:=Network
DEPENDS:=@TARGET_ar71xx
DEFAULT:=n
TITLE:=$(1)
endef
define Package/vsc73x5/install
$(INSTALL_DIR) $(1)/lib/firmware
$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(2) $(1)/lib/firmware/$(3)
endef
define Package/vsc7385-ucode-pb44
$(call Package/vsc73x5-defaults, Vitesse VSC7395 microcode for the Atheros PB44 boards)
endef
define Package/vsc7385-ucode-pb44/description
This package contains the Atheros PB44 board specific microcode for
the Vitesse VSC7385 ethernet switch.
endef
define Package/vsc7385-ucode-pb44/install
$(call Package/vsc73x5/install,$(1),g5_Plus1_2_29b_unmanaged_Atheros_v5.bin,vsc7385_ucode_pb44.bin)
endef
define Package/vsc7395-ucode-pb44
$(call Package/vsc73x5-defaults, Vitesse VSC7395 microcode for the Atheros PB44 boards)
endef
define Package/vsc7395-ucode-pb44/description
This package contains the Atheros PB44 board specific microcode for
the Vitesse VSC7395 ethernet switch.
endef
define Package/vsc7395-ucode-pb44/install
$(call Package/vsc73x5/install,$(1),g5e_Plus1_2_29a_unmanaged_Atheros_v3.bin,vsc7395_ucode_pb44.bin)
endef
define Build/Compile
endef
$(eval $(call BuildPackage,vsc7385-ucode-pb44))
$(eval $(call BuildPackage,vsc7395-ucode-pb44))

20
package/firmware/vsc73x5-ucode/files/Makefile
View File

@ -1,20 +0,0 @@
#
# Copyright (C) 2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
CC:=gcc
OBJCOPY:=objcopy
all: g5_Plus1_2_31_unmanaged_Atheros_v3.bin \
g5_Plus1_2_31_unmanaged_Atheros_v4.bin \
g5_Plus1_2_29b_unmanaged_Atheros_v5.bin \
g5e_Plus1_2_29a_unmanaged_Atheros_v3.bin
%.o: %.c
$(CC) $(CFLAGS) -c $^ -o $@
%.bin: %.o
$(OBJCOPY) -O binary -j .data $^ $@

2
package/kernel/linux/modules/usb.mk
View File

@ -1576,7 +1576,7 @@ $(eval $(call KernelPackage,usbip-server))
define KernelPackage/usb-chipidea
TITLE:=Host and device support for Chipidea controllers
DEPENDS:=+USB_GADGET_SUPPORT:kmod-usb-gadget @TARGET_ar71xx||TARGET_ath79 +kmod-usb-ehci +kmod-usb-phy-nop
DEPENDS:=+USB_GADGET_SUPPORT:kmod-usb-gadget @TARGET_ath79 +kmod-usb-ehci +kmod-usb-phy-nop
KCONFIG:= \
CONFIG_EXTCON \
CONFIG_USB_CHIPIDEA \

9
package/kernel/mac80211/ath.mk
View File

@ -40,7 +40,6 @@ config-$(CONFIG_PACKAGE_ATH_DYNACK) += ATH9K_DYNACK
config-$(call config_package,ath9k) += ATH9K
config-$(call config_package,ath9k-common) += ATH9K_COMMON
config-$(call config_package,owl-loader) += ATH9K_PCI_NO_EEPROM
config-$(CONFIG_TARGET_ar71xx) += ATH9K_AHB
config-$(CONFIG_TARGET_ath79) += ATH9K_AHB
config-$(CONFIG_TARGET_ipq40xx) += ATH10K_AHB
config-$(CONFIG_PCI) += ATH9K_PCI
@ -122,7 +121,7 @@ endef
define KernelPackage/ath
$(call KernelPackage/mac80211/Default)
TITLE:=Atheros common driver part
DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ar71xx||TARGET_ath79||TARGET_ath25 +kmod-mac80211
DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ath79||TARGET_ath25 +kmod-mac80211
FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath.ko
MENU:=1
endef
@ -187,7 +186,7 @@ define KernelPackage/ath9k-common
TITLE:=Atheros 802.11n wireless devices (common code for ath9k and ath9k_htc)
URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath9k
HIDDEN:=1
DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ar71xx||TARGET_ath79 +kmod-ath +@DRIVER_11N_SUPPORT +@DRIVER_11W_SUPPORT
DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ath79 +kmod-ath +@DRIVER_11N_SUPPORT +@DRIVER_11W_SUPPORT
FILES:= \
$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k_common.ko \
$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k_hw.ko
@ -197,7 +196,7 @@ define KernelPackage/ath9k
$(call KernelPackage/mac80211/Default)
TITLE:=Atheros 802.11n PCI wireless cards support
URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath9k
DEPENDS+= @PCI_SUPPORT||TARGET_ar71xx||TARGET_ath79 +kmod-ath9k-common
DEPENDS+= @PCI_SUPPORT||TARGET_ath79 +kmod-ath9k-common
FILES:= \
$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k.ko
AUTOLOAD:=$(call AutoProbe,ath9k)
@ -226,7 +225,7 @@ define KernelPackage/ath9k/config
config ATH9K_UBNTHSR
bool "Support for Ubiquiti UniFi Outdoor+ access point"
depends on PACKAGE_kmod-ath9k && (TARGET_ar71xx_generic||TARGET_ath79)
depends on PACKAGE_kmod-ath9k && TARGET_ath79
default y
endef

2
package/kernel/om-watchdog/Makefile
View File

@ -8,7 +8,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=om-watchdog
PKG_RELEASE:=3
PKG_RELEASE:=4
include $(INCLUDE_DIR)/package.mk

36
package/kernel/om-watchdog/files/om-watchdog.init
View File

@ -13,41 +13,7 @@ PROG=/sbin/om-watchdog
get_gpio() {
local board=$(board_name)
if [ -r /lib/ar71xx.sh ]; then
case "$board" in
"a40"|\
"a60"|\
"mr1750"|\
"mr1750v2"|\
"mr900"|\
"mr900v2")
return 16
;;
"mr600v2")
return 15
;;
"om2p"|\
"om2p-hs"|\
"om2p-hsv2"|\
"om2p-hsv3"|\
"om2p-hsv4"|\
"om2pv4"|\
"om5p-acv2")
return 12
;;
"om2p-lc"|\
"om2pv2")
return 26
;;
"om5p"|\
"om5p-an")
return 11
;;
"om5p-ac")
return 17
;;
esac
elif [ "$board" = "teltonika,rut5xx" ]; then
if [ "$board" = "teltonika,rut5xx" ]; then
# ramips
return 11
else

2
package/system/mtd/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=mtd
PKG_RELEASE:=25
PKG_RELEASE:=26
PKG_BUILD_DIR := $(KERNEL_BUILD_DIR)/$(PKG_NAME)
STAMP_PREPARED := $(STAMP_PREPARED)_$(call confvar,CONFIG_MTD_REDBOOT_PARTS)

1
package/system/mtd/src/Makefile
View File

@ -7,7 +7,6 @@ obj.seama = seama.o md5.o
obj.wrg = wrg.o md5.o
obj.wrgg = wrgg.o md5.o
obj.tpl = tpl_ramips_recoveryflag.o
obj.ar71xx = trx.o $(obj.seama) $(obj.wrgg)
obj.ath79 = $(obj.seama) $(obj.wrgg)
obj.gemini = $(obj.wrgg)
obj.brcm = trx.o

2
package/system/mtd/src/trx.c
View File

@ -110,7 +110,6 @@ err:
return -1;
}
#ifndef target_ar71xx
int
trx_check(int imagefd, const char *mtd, char *buf, int *len)
{
@ -153,7 +152,6 @@ trx_check(int imagefd, const char *mtd, char *buf, int *len)
close(fd);
return 1;
}
#endif
int
mtd_fixtrx(const char *mtd, size_t offset, size_t data_size)

2
package/utils/nvram/Makefile
View File

@ -21,7 +21,7 @@ define Package/nvram
CATEGORY:=Base system
TITLE:=Userspace port of the Broadcom NVRAM manipulation tool
MAINTAINER:=Jo-Philipp Wich <xm@subsignal.org>
DEPENDS:=@(TARGET_bcm47xx||TARGET_bcm53xx||TARGET_ar71xx||TARGET_ath79)
DEPENDS:=@(TARGET_bcm47xx||TARGET_bcm53xx||TARGET_ath79)
endef
define Package/nvram/description

24
target/linux/ar71xx/Makefile
View File

@ -1,24 +0,0 @@
#
# Copyright (C) 2008-2011 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
ARCH:=mips
BOARD:=ar71xx
BOARDNAME:=Atheros AR7xxx/AR9xxx
FEATURES:=usbgadget source-only
CPU_TYPE:=24kc
SUBTARGETS:=generic tiny nand mikrotik
KERNEL_PATCHVER:=4.14
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
kmod-gpio-button-hotplug swconfig \
kmod-ath9k uboot-envtools
$(eval $(call BuildTarget))

1130
target/linux/ar71xx/base-files/etc/board.d/01_leds
View File

File diff suppressed because it is too large Load Diff

711
target/linux/ar71xx/base-files/etc/board.d/02_network
View File

@ -1,711 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2011-2015 OpenWrt.org
#
. /lib/functions/system.sh
. /lib/functions/uci-defaults.sh
ar71xx_setup_interfaces()
{
local board="$1"
case "$board" in
airgatewaypro)
ucidef_add_switch "switch0" \
"0@eth0" "4:lan" "5:wan"
;;
airrouter|\
ap121|\
ap121-mini|\
ap96|\
dir-600-a1|\
dir-615-c1|\
dir-615-e1|\
dir-615-e4|\
hiwifi-hc6361|\
ja76pf|\
mc-mac1200r|\
minibox-v1|\
mynet-n600|\
oolite-v1|\
oolite-v5.2|\
oolite-v5.2-dev|\
qihoo-c301|\
r602n|\
rb-750|\
rb-751|\
som9331|\
t830|\
tew-632brp|\
tew-712br|\
tew-732br|\
tl-mr3220|\
tl-mr3420|\
tl-wdr3320-v2|\
tl-wdr3500|\
tl-wr740n-v6|\
tl-wr840n-v2|\
tl-wr840n-v3|\
tl-wr841n-v11|\
tl-wr841n-v9|\
tl-wr842n-v3|\
whr-g301n|\
whr-hp-g300n|\
whr-hp-gn|\
wzr-hp-ag300h|\
zbt-we1526)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1"
;;
alfa-ap120c|\
all0305|\
antminer-s1|\
antminer-s3|\
antrouter-r1|\
ap121f|\
ap91-5g|\
aw-nr580|\
bullet-m|\
bullet-m-xw|\
c-55|\
cap324|\
cap4200ag|\
cf-e380ac-v1|\
cf-e380ac-v2|\
cpe210-v2|\
cpe210-v3|\
cpe510-v2|\
dr342|\
eap120|\
eap300v2|\
eap7660d|\
el-mini|\
fritz300e|\
fritz450e|\
gl-usb150|\
hiveap-121|\
koala|\
lbe-m5|\
loco-m-xw|\
mr12|\
mr16|\
mr1750|\
mr1750v2|\
mr18|\
mr600|\
mr600v2|\
mr900|\
mr900v2|\
mynet-rext|\
pqi-air-pen|\
rb-411|\
rb-411u|\
rb-911-2hn|\
rb-911-5hn|\
rb-911g-2hpnd|\
rb-911g-5hpacd|\
rb-911g-5hpnd|\
rb-912uag-2hpnd|\
rb-912uag-5hpnd|\
rb-921gs-5hpacd-r2|\
rb-922uags-5hpacd|\
rb-lhg-5nd|\
rb-mapl-2nd|\
rb-sxt2n|\
rb-sxt-2nd-r3|\
rb-sxt5n|\
rb-wap-2nd|\
rb-wapr-2nd|\
rb-wapg-5hact2hnd|\
re355|\
re450|\
rocket-m-xw|\
sc300m |\
tl-mr10u|\
tl-mr11u|\
tl-mr12u|\
tl-mr13u|\
tl-mr3020|\
tl-mr3040|\
tl-mr3040-v2|\
tl-wa701nd-v2|\
tl-wa7210n-v2|\
tl-wa750re|\
tl-wa801nd-v2|\
tl-wa830re-v2|\
tl-wa850re|\
tl-wa850re-v2|\
tl-wa855re-v1|\
tl-wa901nd|\
tl-wa901nd-v2|\
tl-wa901nd-v3|\
tl-wa901nd-v4|\
tl-wa901nd-v5|\
tl-wr703n|\
tl-wr802n-v1|\
tl-wr802n-v2|\
tl-wr902ac-v1|\
ts-d084|\
tube2h|\
unifi|\
unifiac-lite|\
wi2a-ac200i|\
wifi-pineapple-nano|\
wndap360|\
wp543)
ucidef_set_interface_lan "eth0"
;;
a40|\
a60|\
alfa-ap96|\
alfa-nx|\
dr344|\
gl-ar150|\
gl-ar300m|\
gl-domino|\
gl-inet|\
gl-mifi|\
jwap003|\
om2p-hsv4|\
om2pv4|\
pb42|\
pb44|\
rb-951ui-2hnd|\
routerstation|\
tl-wr710n|\
tl-wr720n-v3|\
tl-wr810n|\
tl-wr810n-v2|\
wpe72|\
wrtnode2q)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
all0258n|\
all0315n|\
dlan-hotspot|\
dlan-pro-500-wp|\
ja76pf2|\
rocket-m-ti|\
ubnt-unifi-outdoor)
ucidef_set_interface_lan "eth0 eth1"
;;
wzr-hp-g300nh2)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "2:wan"
;;
ap132|\
ap136|\
ap152|\
rb-750gl|\
rb-751g|\
rb-951g-2hnd|\
rb-962uigs-5hact2hnt|\
wlr8100|\
wzr-hp-g450h)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "3:lan" "4:lan" "5:lan" "1:wan"
;;
ap135-020|\
ap136-020|\
bhr-4grv2|\
tew-823dru|\
tl-wr1043nd-v2|\
wzr-450hp2)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0.2"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan" "6@eth0"
;;
ap136-010|\
ap147-010|\
nbg6616|\
nbg6716)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1.2"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "6@eth1"
;;
ap143|\
rb-433|\
rb-433u)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"1:lan" "2:lan" "5@eth1"
;;
archer-c5|\
archer-c7|\
tl-wdr4900-v2)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0.2"
ucidef_add_switch "switch0" \
"0@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth0" "1:wan"
;;
archer-c25-v1|\
archer-c60-v1|\
archer-c60-v2|\
rb-750-r2|\
rb-750p-pbr2|\
rb-750up-r2|\
rb-951ui-2nd|\
rb-952ui-5ac2nd)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1"
;;
archer-c58-v1|\
archer-c59-v1|\
archer-c59-v2|\
fritz4020|\
rb-450g)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan:1" "2:lan:4" "3:lan:3" "4:lan:2"
;;
arduino-yun|\
dir-505-a1|\
tl-wa801nd-v3)
ucidef_set_interface_lan "eth1"
;;
bsb)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan" "3:lan"
;;
c-60)
ucidef_add_switch "switch0" \
"0@eth0" "3:wan" "4:lan"
;;
rme-eg200)
ucidef_set_interface_lan "eth0" "dhcp"
;;
cf-e375ac|\
rb-map-2nd)
ucidef_add_switch "switch0" \
"0@eth0" "1:wan" "2:lan"
;;
cf-e385ac)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1.2"
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "1:wan" "6@eth1"
;;
cpe210|\
cpe510|\
wbs210|\
wbs510)
ucidef_add_switch "switch0" \
"0@eth0" "5:lan" "4:wan"
;;
cr3000)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:1" "2:lan:4" "3:lan:3" "4:lan:2"
;;
cr5000|\
dgl-5500-a1|\
dhp-1565-a1|\
dir-825-c1|\
dir-835-a1|\
esr900|\
mynet-n750|\
sr3200)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
;;
tl-wr1043n-v5)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan"
;;
dap-2695-a1)
ucidef_add_switch "switch0" "0@eth0" "2:lan" "3:wan" "6@eth1"
;;
rb-931-2nd)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:3" "2:lan:2" "3:wan:1"
;;
rb-941-2nd)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:wan:1"
;;
db120|\
rb-2011il|\
rb-2011ils|\
rb-2011l|\
rb-2011uas|\
rb-2011uas-2hnd|\
rb-2011uias|\
rb-2011uias-2hnd|\
rb-2011uias-2hnd-r2)
case "$board" in
rb-2011ils|\
rb-2011uas*|\
rb-2011uias|\
rb-2011uias-2hnd|\
rb-2011uias-2hnd-r2)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "3:lan" "4:lan" "5:lan" "1:wan" "6:sfp"
;;
*)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "3:lan" "4:lan" "5:lan" "1:wan"
;;
esac
ucidef_add_switch "switch1" \
"0@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:lan"
;;
dir-615-i1|\
omy-g1|\
r6100|\
smart-300|\
tl-wdr6500-v2|\
tl-wr940n-v4|\
tl-wr940n-v6|\
tl-wr941nd-v6|\
wnr1000-v2|\
wnr2000-v4|\
wnr2200|\
wnr612-v2|\
wpn824n)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4"
;;
tl-mr6400)
ucidef_set_interfaces_lan_wan "eth0.1 eth1" "usb0"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan" "2:lan" "3:lan"
;;
dir-825-b1|\
nbg460n_550n_550nh|\
tew-673gru|\
wzr-hp-g300nh)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "3:lan" "5@eth0"
;;
dlan-pro-1200-ac)
ucidef_set_interface_lan "eth0"
ucidef_add_switch "switch0" \
"0u@eth0" "2:lan" "3:lan" "4:lan"
ucidef_add_switch_attr "switch0" "enable" "false"
;;
e1700ac-v2|\
e750g-v8|\
unifiac-pro|\
xd3200)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "3:wan"
;;
e558-v2)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0.2"
ucidef_add_switch "switch0" \
"0@eth1" "4:lan" "5:lan" "6@eth0" "3:wan"
;;
ebr-2310-c1)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4"
;;
el-m150)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "3@eth1"
;;
dir-869-a1|\
epg5000|\
esr1750|\
tl-wr1043nd-v4|\
wndr3700v4|\
wndr4300)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan"
;;
ew-balin)
ucidef_set_interface "usb2" ifname "usb0" protocol "static"
ucidef_add_switch "switch0" \
"0@eth0" "5:lan:4" "4:lan:5" "3:wan"
;;
ew-dorin)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan" "2:lan" "3:wan"
;;
ew-dorin-router)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "3:lan"
;;
dw33d|\
f9k1115v2)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0.2"
ucidef_add_switch "switch0" \
"2:lan" "3:lan" "4:lan" "5:lan" "6@eth1" "0@eth0" "1:wan"
;;
gl-ar300|\
wnr2000-v3)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan" "2:lan" "3:lan" "4:lan"
;;
gl-ar750|\
rb-435g)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan" "2:lan"
;;
gl-ar750s)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:2" "3:lan:1" "1:wan"
;;
jwap230)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1.2"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan" "5:wan" "6@eth1"
;;
nanostation-m-xw)
ucidef_add_switch "switch0" \
"0@eth0" "5:lan" "1:wan"
;;
onion-omega)
ucidef_set_interface_lan "wlan0"
;;
rb-450)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5@eth1"
;;
routerstation-pro)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "2:lan:3" "3:lan:2" "4:lan:1"
;;
rb-493g)
ucidef_set_interfaces_lan_wan "eth0.1 eth1.1" "eth1.2"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:4" "2:lan:1" "3:lan:2" "4:lan:3"
ucidef_add_switch "switch1" \
"0@eth1" "1:lan:4" "2:lan:1" "3:lan:3" "4:lan:2" "5:wan"
;;
rut900)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:3" "3:lan:2" "4:lan:1"
;;
tellstick-znet-lite)
ucidef_set_interface_wan "eth0"
ucidef_set_interface "wlan" ifname "wlan0" protocol "dhcp"
;;
tl-mr3420-v2|\
tl-wr841n-v8|\
tl-wr842n-v2|\
tl-wr941nd-v5|\
tl-wr942n-v1)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan:4" "2:lan:1" "3:lan:2" "4:lan:3"
;;
archer-c7-v4|\
archer-c7-v5|\
tl-wdr4300|\
tl-wr1041n-v2)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "1:wan"
;;
tl-wpa8630)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:3" "3:lan:2" "4:lan:1" "5:lan:4"
;;
tl-wr1043nd)
ucidef_add_switch "switch0" \
"1:lan" "2:lan" "3:lan" "4:lan" "0:wan" "5@eth0"
;;
tl-wr2543n)
ucidef_add_switch "switch0" \
"1:lan" "2:lan" "3:lan" "4:lan" "0:wan" "9@eth0"
;;
tl-mr3220-v2|\
tl-wr741nd-v4)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:4" "2:lan:1" "3:lan:2" "4:lan:3"
;;
tl-wr841n-v1|\
tl-wr941nd)
ucidef_set_interface "eth" ifname "eth0"
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
tl-wr741nd|\
tl-wr841n-v7)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4"
;;
uap-pro|\
wpj342)
ucidef_add_switch "switch0" \
"0@eth0" "1:lan" "2:wan"
;;
wndr3700|\
wndr3700v2|\
wndr3800|\
wndr3800ch)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5@eth0"
ucidef_add_switch_attr "switch0" "blinkrate" 2
ucidef_add_switch_port_attr "switch0" 1 led 6
ucidef_add_switch_port_attr "switch0" 2 led 9
ucidef_add_switch_port_attr "switch0" 5 led 2
;;
wpj344)
ucidef_add_switch "switch0" \
"0@eth0" "3:lan" "2:wan"
;;
wpj558)
ucidef_add_switch "switch0" \
"5:lan" "1:wan" "6@eth0"
;;
wpj563)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan" "3:wan"
;;
wrt160nl)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "4@eth0"
;;
wzr-hp-g450h)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:1 3:lan:2 4:lan:3 5:lan:4" "1:wan"
;;
z1)
ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4" "5:wan"
;;
ens202ext)
ucidef_set_interfaces_lan_wan "eth1.1" "eth1.2"
ucidef_add_switch "switch0" \
"0@eth1" "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "1:wan"
;;
*)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
esac
}
ar71xx_setup_macs()
{
local board="$1"
local lan_mac=""
local wan_mac=""
case $board in
archer-c7-v4)
base_mac=$(mtd_get_mac_binary config 0x8)
wan_mac=$(macaddr_add "$base_mac" 1)
;;
archer-c7-v5)
base_mac=$(mtd_get_mac_binary info 0x8)
wan_mac=$(macaddr_add "$base_mac" 1)
;;
dgl-5500-a1|\
dir-825-c1)
wan_mac=$(mtd_get_mac_ascii nvram "wan_mac")
;;
dhp-1565-a1|\
dir-835-a1|\
wndr3700v4|\
wndr4300)
lan_mac=$(mtd_get_mac_binary caldata 0x0)
wan_mac=$(mtd_get_mac_binary caldata 0x6)
;;
dir-869-a1|\
mynet-n750)
wan_mac=$(mtd_get_mac_ascii devdata "wanmac")
;;
esr900)
wan_mac=$(mtd_get_mac_ascii u-boot-env "wanaddr")
;;
fritz300e)
lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)"))
;;
tl-wdr4300)
base_mac=$(mtd_get_mac_binary u-boot 0x1fc00)
wan_mac=$(macaddr_add "$base_mac" 1)
;;
tl-wr1043n-v5|\
tl-wr1043nd-v4)
lan_mac=$(mtd_get_mac_binary product-info 0x8)
wan_mac=$(macaddr_add "$lan_mac" 1)
;;
wlr8100)
lan_mac=$(mtd_get_mac_ascii u-boot-env "ethaddr")
wan_mac=$(mtd_get_mac_ascii u-boot-env "wanaddr")
;;
wpj344|\
wpj558)
wan_mac=$(mtd_get_mac_binary u-boot 0x2e018)
;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
}
ar71xx_setup_ar8xxx_switch()
{
local board="$1"
case $board in
ap147-010|\
archer-c25-v1|\
archer-c58-v1|\
archer-c59-v1|\
archer-c59-v2|\
archer-c60-v1|\
archer-c60-v2|\
archer-c7-v4|\
archer-c7-v5|\
cf-e375ac|\
cf-e385ac|\
cr3000|\
dhp-1565-a1|\
mynet-n600|\
rb-2011il|\
rb-2011ils|\
rb-2011l|\
rb-2011uas|\
rb-2011uas-2hnd|\
rb-2011uias|\
rb-2011uias-2hnd|\
rb-2011uias-2hnd-r2|\
rb-750|\
rb-750p-pbr2|\
rb-750-r2|\
rb-750up-r2|\
rb-951ui-2nd|\
rb-952ui-5ac2nd|\
rb-map-2nd|\
tl-wr1043nd-v4|\
tl-wr1043n-v5|\
wndr3700v4|\
wndr3700v4|\
wndr4300|\
wnr1000-v2|\
wnr2000-v3|\
wnr2200|\
wnr612-v2|\
wpn824n)
ucidef_set_ar8xxx_switch_mib "switch0" 0 500
;;
esac
}
board_config_update
board=$(board_name)
ar71xx_setup_interfaces $board
ar71xx_setup_macs $board
ar71xx_setup_ar8xxx_switch $board
board_config_flush
exit 0

42
target/linux/ar71xx/base-files/etc/board.d/03_gpio_switches
View File

@ -1,42 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2015 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
cpe210|\
cpe510|\
wbs210|\
wbs510)
ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "20"
;;
nanostation-m)
ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "8"
;;
nanostation-m-xw)
ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "2"
;;
rb-912uag-2hpnd|\
rb-912uag-5hpnd)
ucidef_add_gpio_switch "usb_power_switch" "USB Power Switch" "61" "1"
;;
rb-750up-r2|\
rb-951ui-2nd|\
rb-952ui-5ac2nd)
ucidef_add_gpio_switch "usb_power_switch" "USB Power Switch" "45" "1"
ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "14"
;;
rb-750p-pbr2)
ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "14"
;;
esac
board_config_flush
exit 0

599
target/linux/ar71xx/base-files/etc/diag.sh
View File

@ -1,599 +0,0 @@
#!/bin/sh
# Copyright (C) 2009-2013 OpenWrt.org
. /lib/functions.sh
. /lib/functions/leds.sh
get_status_led() {
local board=$(board_name)
case $board in
a40)
status_led="a40:green:status"
;;
a60)
status_led="a60:green:status"
;;
alfa-nx)
status_led="alfa:green:led_8"
;;
all0305)
status_led="eap7660d:green:ds4"
;;
antminer-s1|\
antminer-s3|\
antminer-r1|\
e1700ac-v2|\
e558-v2|\
e600gac-v2|\
e750a-v4|\
e750g-v8|\
eap120|\
minibox-v1|\
minibox-v3.2|\
packet-squirrel|\
som9331|\
sr3200|\
tl-wr802n-v2|\
xd3200)
status_led="$board:green:system"
;;
ap121f)
status_led="$board:green:vpn"
;;
ap132|\
ap531b0|\
cpe505n|\
db120|\
dr342|\
dr344|\
rut900|\
tew-632brp|\
tl-wr942n-v1|\
wpj344|\
zbt-we1526)
status_led="$board:green:status"
;;
ap136-010|\
ap136-020)
status_led="ap136:green:status"
;;
ap147-010)
status_led="ap147:green:status"
;;
ap135-020)
status_led="ap135:green:status"
;;
archer-c25-v1|\
archer-c58-v1|\
archer-c59-v1|\
archer-c59-v2|\
archer-c60-v1|\
archer-c60-v2|\
archer-c7-v4|\
archer-c7-v5|\
fritz300e|\
fritz4020|\
fritz450e|\
gl-ar750s|\
gl-usb150|\
mr12|\
mr16|\
nbg6616|\
sc1750|\
sc450|\
tl-wpa8630|\
tl-wr902ac-v1)
status_led="$board:green:power"
;;
tl-mr10u|\
tl-mr12u|\
tl-mr13u|\
tl-wdr4300|\
tl-wdr4900-v2|\
tl-wr703n|\
tl-wr710n|\
tl-wr720n-v3|\
tl-wr802n-v1|\
tl-wr810n|\
tl-wr810n-v2|\
tl-wr940n-v4|\
tl-wr941nd-v6)
status_led="tp-link:blue:system"
;;
ap90q|\
cpe830|\
cpe870|\
gl-ar300m|\
gl-inet|\
gl-mifi)
status_led="$board:green:lan"
;;
ap91-5g|\
n5q)
status_led="$board:green:signal4"
;;
ap96)
status_led="$board:green:led2"
;;
aw-nr580)
status_led="$board:green:ready"
;;
bhr-4grv2|\
wzr-hp-ag300h|\
wzr-hp-g300nh2)
status_led="buffalo:red:diag"
;;
bsb)
status_led="$board:red:sys"
;;
bullet-m|\
bullet-m-xw|\
loco-m-xw|\
nano-m|\
nanostation-m|\
nanostation-m-xw|\
rocket-m|\
rocket-m-xw)
status_led="ubnt:green:link4"
;;
bxu2000n-2-a1)
status_led="bhu:green:status"
;;
cap324)
status_led="pcs:green:power"
;;
c-55|\
c-60)
status_led="$board:green:pwr"
;;
cap4200ag)
status_led="senao:green:pwr"
;;
cf-e316n-v2|\
cf-e520n|\
cf-e530n)
status_led="$board:blue:wan"
;;
cf-e320n-v2)
status_led="$board:blue:wlan"
;;
cf-e375ac|\
cf-e380ac-v1|\
cf-e380ac-v2|\
cf-e385ac)
status_led="$board:blue:wlan2g"
;;
cpe510)
status_led="tp-link:green:link4"
;;
cr3000|\
cr5000)
status_led="pcs:amber:power"
;;
dap-1330-a1|\
dgl-5500-a1|\
dhp-1565-a1|\
dir-505-a1|\
dir-600-a1|\
dir-615-e1|\
dir-615-i1|\
dir-615-e4)
status_led="d-link:green:power"
;;
dir-615-c1)
status_led="d-link:green:status"
;;
dir-825-b1)
status_led="d-link:orange:power"
;;
dir-825-c1|\
dir-835-a1)
status_led="d-link:amber:power"
;;
dir-869-a1)
status_led="d-link:white:status"
;;
dlan-hotspot)
status_led="devolo:green:wifi"
;;
dlan-pro-500-wp)
status_led="devolo:green:wlan-2g"
;;
dlan-pro-1200-ac)
status_led="devolo:status:wlan"
;;
dr531)
status_led="$board:green:sig4"
;;
dragino2|\
oolite-v1)
status_led="$board:red:system"
;;
dw33d|\
r36a)
status_led="$board:blue:status"
;;
e600g-v2|\
oolite-v5.2-dev|\
ts-d084|\
wifi-pineapple-nano)
status_led="$board:blue:system"
;;
eap300v2)
status_led="engenius:blue:power"
;;
ens202ext|\
esr900)
status_led="engenius:amber:power"
;;
eap7660d)
status_led="$board:green:ds4"
;;
el-m150|\
el-mini)
status_led="easylink:green:system"
;;
ew-balin)
status_led="balin:green:status"
;;
ew-dorin|\
ew-dorin-router)
status_led="dorin:green:status"
;;
f9k1115v2)
status_led="belkin:blue:status"
;;
epg5000|\
esr1750)
status_led="$board:amber:power"
;;
gl-ar750|\
hiveap-121|\
nbg6716|\
wam250)
status_led="$board:white:power"
;;
hiwifi-hc6361)
status_led="hiwifi:blue:system"
;;
hornet-ub|\
hornet-ub-x2)
status_led="alfa:blue:wps"
;;
ja76pf|\
ja76pf2)
status_led="jjplus:green:led1"
;;
jwap230)
status_led="$board:green:led1"
;;
koala)
status_led="$board:blue:sys"
;;
lan-turtle)
status_led="$board:orange:system"
;;
lbe-m5)
status_led="ubnt:green:sys"
;;
ls-sr71)
status_led="ubnt:green:d22"
;;
mc-mac1200r)
status_led="mercury:green:system"
;;
mr18|\
z1)
status_led="$board:green:tricolor0"
;;
mr600)
status_led="$board:orange:power"
;;
mr600v2)
status_led="mr600:blue:power"
;;
mr1750|\
mr1750v2)
status_led="mr1750:blue:power"
;;
mr900|\
mr900v2)
status_led="mr900:blue:power"
;;
mynet-n600|\
mynet-n750|\
mynet-rext)
status_led="wd:blue:power"
;;
mzk-w04nu|\
mzk-w300nh)
status_led="planex:green:status"
;;
nbg460n_550n_550nh)
status_led="nbg460n:green:power"
;;
om2p|\
om2p-hs|\
om2p-hsv2|\
om2p-hsv3|\
om2p-hsv4|\
om2p-lc|\
om2pv2|\
om2pv4)
status_led="om2p:blue:power"
;;
om5p|\
om5p-an)
status_led="om5p:blue:power"
;;
om5p-ac|\
om5p-acv2)
status_led="om5pac:blue:power"
;;
omy-g1)
status_led="omy:green:wlan"
;;
omy-x1)
status_led="omy:green:power"
;;
onion-omega)
status_led="onion:amber:system"
;;
pb44)
status_led="$board:amber:jump1"
;;
r602n)
status_led="$board:green:wan"
;;
rb-2011il|\
rb-2011ils|\
rb-2011l|\
rb-2011uas|\
rb-2011uas-2hnd)
status_led="rb:green:usr"
;;
rb-411|\
rb-411u|\
rb-433|\
rb-433u|\
rb-450|\
rb-450g|\
rb-493)
status_led="rb4xx:yellow:user"
;;
rb-750)
status_led="rb750:green:act"
;;
rb-750-r2|\
rb-750p-pbr2|\
rb-750up-r2|\
rb-911-2hn|\
rb-911-5hn|\
rb-911g-2hpnd|\
rb-911g-5hpacd|\
rb-911g-5hpnd|\
rb-931-2nd|\
rb-941-2nd|\
rb-951ui-2nd|\
rb-952ui-5ac2nd|\
rb-962uigs-5hact2hnt|\
rb-lhg-5nd|\
rb-map-2nd|\
rb-mapl-2nd|\
rb-sxt-2nd-r3|\
rb-wap-2nd|\
rb-wapr-2nd)
status_led="rb:green:user"
;;
rb-951ui-2hnd)
status_led="rb:green:act"
;;
rb-912uag-2hpnd|\
rb-912uag-5hpnd|\
rb-sxt2n|\
rb-sxt5n|\
rb-wapg-5hact2hnd)
status_led="rb:green:power"
;;
re355|\
re450|\
sc300m)
status_led="$board:blue:power"
;;
rocket-m-ti)
status_led="ubnt:green:link6"
;;
routerstation|\
routerstation-pro)
status_led="ubnt:green:rf"
;;
rw2458n)
status_led="$board:green:d3"
;;
smart-300)
status_led="nc-link:green:system"
;;
qihoo-c301)
status_led="qihoo:green:status"
;;
t830)
status_led="$board:green:usb"
;;
tellstick-znet-lite)
status_led="tellstick:white:system"
;;
tew-673gru)
status_led="trendnet:blue:wps"
;;
tew-712br|\
tew-732br|\
tew-823dru)
status_led="trendnet:green:power"
;;
tl-mr3020|\
tl-wr2543n)
status_led="tp-link:green:wps"
;;
tl-wa750re)
status_led="tp-link:orange:re"
;;
tl-wa850re|\
tl-wa850re-v2)
status_led="tp-link:blue:re"
;;
tl-wa855re-v1|\
tl-wa860re)
status_led="tp-link:green:power"
;;
tl-mr6400)
status_led="tp-link:white:power"
;;
archer-c5|\
archer-c7|\
tl-mr3220|\
tl-mr3220-v2|\
tl-mr3420|\
tl-mr3420-v2|\
tl-wa701nd-v2|\
tl-wa801nd-v2|\
tl-wa801nd-v3|\
tl-wa830re-v2|\
tl-wa901nd|\
tl-wa901nd-v2|\
tl-wa901nd-v3|\
tl-wa901nd-v4|\
tl-wa901nd-v5|\
tl-wdr3320-v2|\
tl-wdr3500|\
tl-wr1041n-v2|\
tl-wr1043n-v5|\
tl-wr1043nd|\
tl-wr1043nd-v2|\
tl-wr1043nd-v4|\
tl-wr740n-v6|\
tl-wr741nd|\
tl-wr741nd-v4|\
tl-wr840n-v2|\
tl-wr840n-v3|\
tl-wr841n-v1|\
tl-wr841n-v7|\
tl-wr841n-v8|\
tl-wr841n-v11|\
tl-wr842n-v2|\
tl-wr842n-v3|\
tl-wr941nd|\
tl-wr941nd-v5)
status_led="tp-link:green:system"
;;
tl-wr841n-v9)
status_led="tp-link:green:qss"
;;
tl-wr940n-v6)
status_led="tp-link:orange:diag"
;;
tl-wdr6500-v2)
status_led="tp-link:white:system"
;;
tube2h)
status_led="alfa:green:signal4"
;;
unifi)
status_led="ubnt:green:dome"
;;
uap-pro|\
unifiac-lite|\
unifiac-pro)
status_led="ubnt:white:dome"
;;
unifi-outdoor-plus)
status_led="ubnt:white:front"
;;
airgateway|\
airgatewaypro)
status_led="ubnt:white:status"
;;
wi2a-ac200i)
status_led="nokia:green:ctrl"
;;
whr-g301n|\
whr-hp-g300n|\
whr-hp-gn|\
wzr-hp-g300nh)
status_led="buffalo:green:router"
;;
wlae-ag300n)
status_led="buffalo:green:status"
;;
r6100|\
wndap360|\
wndr3700|\
wndr3700v4|\
wndr4300|\
wnr2000|\
wnr2000-v3|\
wnr2200|\
wnr612-v2|\
wnr1000-v2|\
wpn824n)
status_led="netgear:green:power"
;;
wp543)
status_led="$board:green:diag"
;;
wpj342|\
wpj531|\
wpj558)
status_led="$board:green:sig3"
;;
wpj563)
status_led="$board:green:sig1"
;;
wrt160nl|\
wrt400n)
status_led="$board:blue:wps"
;;
zcn-1523h-2|\
zcn-1523h-5)
status_led="zcn-1523h:amber:init"
;;
wlr8100)
status_led="sitecom:amber:status"
;;
esac
}
set_state() {
get_status_led
case "$1" in
preinit)
status_led_blink_preinit
;;
failsafe)
status_led_blink_failsafe
;;
preinit_regular)
status_led_blink_preinit_regular
;;
upgrade)
status_led_blink_preinit_regular
;;
done)
status_led_on
case $(board_name) in
gl-ar300m|\
gl-ar750)
fw_printenv lc >/dev/null 2>&1 && fw_setenv "bootcount" 0
;;
qihoo-c301)
local n=$(fw_printenv activeregion | cut -d = -f 2)
fw_setenv "image${n}trynum" 0
;;
wi2a-ac200i)
fw_setenv PKRstCnt 0
;;
esac
;;
esac
}

178
target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
View File

@ -1,178 +0,0 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions.sh
. /lib/functions/system.sh
ath9k_eeprom_die() {
echo "ath9k eeprom: " "$*"
exit 1
}
ath9k_eeprom_extract() {
local part=$1
local offset=$(($2))
local count=$(($3))
local mtd
mtd=$(find_mtd_chardev $part)
[ -n "$mtd" ] || \
ath9k_eeprom_die "no mtd device found for partition $part"
dd if=$mtd of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
ath9k_eeprom_die "failed to extract from $mtd"
}
ath9k_ubi_eeprom_extract() {
local part=$1
local offset=$(($2))
local count=$(($3))
local ubidev=$(nand_find_ubi $CI_UBIPART)
local ubi
ubi=$(nand_find_volume $ubidev $part)
[ -n "$ubi" ] || \
ath9k_eeprom_die "no UBI volume found for $part"
dd if=/dev/$ubi of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
ath9k_eeprom_die "failed to extract from $ubi"
}
ath9k_eeprom_extract_reverse() {
local part=$1
local offset=$2
local count=$(($3))
local mtd
local reversed
local caldata
mtd=$(find_mtd_chardev "$part")
reversed=$(hexdump -v -s $offset -n $count -e '/1 "%02x "' $mtd)
for byte in $reversed; do
caldata="\x${byte}${caldata}"
done
printf "%b" "$caldata" > /lib/firmware/$FIRMWARE
}
ath9k_patch_firmware_mac() {
local mac=$1
[ -z "$mac" ] && return
macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc oflag=seek_bytes bs=6 seek=2 count=1
}
board=$(board_name)
case "$FIRMWARE" in
"soc_wmac.eeprom")
case $board in
c-55|\
c-60)
ath9k_eeprom_extract "art" 0x1000 0x800
ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +1)
;;
fritz4020|\
fritz450e)
ath9k_eeprom_extract_reverse "urlader" 0x1541 0x440
;;
mr18)
. /lib/upgrade/nand.sh
if [ -n "$(nand_find_volume ubi0 caldata)" ]; then
ath9k_ubi_eeprom_extract "caldata" 0x1000 0x800
else
ath9k_eeprom_extract "odm-caldata" 0x1000 0x800
fi
ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary_ubi board-config 0x66) +1)
;;
r6100 | \
wndr3700v4 | \
wndr4300)
ath9k_eeprom_extract "caldata" 0x1000 0x800
ath9k_patch_firmware_mac $(mtd_get_mac_binary caldata 0x0)
;;
rambutan)
ath9k_eeprom_extract "art" 0x1000 0x800
;;
wlr8100)
ath9k_eeprom_extract "art" 0x1000 0x800
ath9k_patch_firmware_mac $(mtd_get_mac_ascii u-boot-env "ethaddr")
;;
z1)
. /lib/upgrade/nand.sh
if [ -n "$(nand_find_volume ubi0 caldata)" ]; then
ath9k_ubi_eeprom_extract "caldata" 0x1000 0x800
else
ath9k_eeprom_extract "origcaldata" 0x1000 0x800
fi
ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary_ubi board-config 0x66) +2)
;;
*)
ath9k_eeprom_die "board $board is not supported yet"
;;
esac
;;
"pci_wmac0.eeprom")
case $board in
c-55)
ath9k_eeprom_extract "art" 0x5000 0x800
ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +2)
;;
fritz300e)
ath9k_eeprom_extract_reverse "urloader" 0x1541 0x440
;;
mr18)
. /lib/upgrade/nand.sh
if [ -n "$(nand_find_volume ubi0 caldata)" ]; then
ath9k_ubi_eeprom_extract "caldata" 0x5000 0x800
else
ath9k_eeprom_extract "odm-caldata" 0x5000 0x800
fi
ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary_ubi board-config 0x66) +2)
;;
wndr3700v4 | \
wndr4300)
ath9k_eeprom_extract "caldata" 0x5000 0x800
ath9k_patch_firmware_mac $(mtd_get_mac_binary caldata 0xc)
;;
z1)
. /lib/upgrade/nand.sh
if [ -n "$(nand_find_volume ubi0 caldata)" ]; then
ath9k_ubi_eeprom_extract "caldata" 0x15000 0x1000
else
ath9k_eeprom_extract "origcaldata" 0x15000 0x1000
fi
ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary_ubi board-config 0x66) +3)
;;
*)
ath9k_eeprom_die "board $board is not supported yet"
;;
esac
;;
"pci_wmac1.eeprom")
case $board in
mr18)
. /lib/upgrade/nand.sh
if [ -n "$(nand_find_volume ubi0 caldata)" ]; then
ath9k_ubi_eeprom_extract "caldata" 0x9000 0x800
else
ath9k_eeprom_extract "odm-caldata" 0x9000 0x800
fi
ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary_ubi board-config 0x66) +3)
;;
*)
ath9k_eeprom_die "board $board is not supported yet"
;;
esac
;;
esac

195
target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@ -1,195 +0,0 @@
#!/bin/sh
ath10kcal_die() {
echo "ath10cal: " "$*"
exit 1
}
ath10kcal_from_file() {
local source=$1
local offset=$(($2))
local count=$(($3))
dd if=$source of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
ath10kcal_die "failed to extract calibration data from $source"
}
ath10kcal_extract() {
local part=$1
local offset=$(($2))
local count=$(($3))
local mtd cal_size
mtd=$(find_mtd_chardev $part)
[ -n "$mtd" ] || \
ath10kcal_die "no mtd device found for partition $part"
# Check that the calibration data size in header equals the desired size
cal_size=$(dd if=$mtd bs=2 count=1 skip=$(( $offset / 2 )) conv=swab 2>/dev/null | hexdump -ve '1/2 "%d"')
[ "$count" = "$cal_size" ] || \
ath10kcal_die "no calibration data found in $part"
dd if=$mtd of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
ath10kcal_die "failed to extract calibration data from $mtd"
}
ath10kcal_patch_mac() {
local mac=$1
[ -z "$mac" ] && return
macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc oflag=seek_bytes bs=6 seek=6 count=1
}
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions.sh
. /lib/functions/system.sh
board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:00:00.0.bin")
case $board in
a40|\
a60|\
mr1750|\
mr1750v2|\
om5p-acv2)
ath10kcal_extract "ART" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16)
;;
archer-c25-v1|\
tl-wdr6500-v2)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -2)
;;
archer-c7-v4|\
archer-c7-v5)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -1)
;;
cf-e355ac-v1|\
cf-e380ac-v1|\
cf-e380ac-v2|\
dlan-pro-1200-ac|\
e1700ac-v2|\
e600gac-v2|\
minibox-v3.2|\
oolite-v5.2|\
oolite-v5.2-dev|\
sr3200|\
xd3200)
ath10kcal_extract "art" 0x5000 0x844
;;
dap-2695-a1)
ath10kcal_extract "radiocfg" 0x5000 0x844
ath10kcal_patch_mac $(mtd_get_mac_ascii bdcfg wlanmac_a)
;;
dir-869-a1|\
qihoo-c301)
ath10kcal_extract "radiocfg" 0x5000 0x844
ath10kcal_patch_mac $(mtd_get_mac_ascii devdata wlan5mac)
;;
dw33d)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(mtd_get_mac_binary art 0x12)
;;
epg5000|\
esr1750)
ath10kcal_extract "caldata" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +1)
;;
gl-ar750s|\
gl-ar750|\
tl-wpa8630)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +1)
;;
koala)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0xc) +0)
;;
mc-mac1200r)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -1)
;;
r6100)
ath10kcal_extract "caldata" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) +2)
;;
rb-952ui-5ac2nd|\
rb-wapg-5hact2hnd)
ath10kcal_from_file "/sys/firmware/mikrotik/hard_config/wlan_data" 0x5000 0x844
;;
re355|\
re450|\
tl-wr902ac-v1)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -2)
;;
unifiac-lite|\
unifiac-pro)
ath10kcal_extract "EEPROM" 0x5000 0x844
;;
wi2a-ac200i)
ath10kcal_extract "ART" 0x5000 0x844
;;
esac
;;
"ath10k/cal-pci-0000:01:00.0.bin")
case $board in
archer-c5|\
archer-c7)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -1)
;;
nbg6616|\
nbg6716)
ath10kcal_extract "RFdata" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -2)
;;
om5p-ac)
ath10kcal_extract "ART" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16)
;;
rb-911g-5hpacd|\
rb-921gs-5hpacd-r2|\
rb-922uags-5hpacd|\
rb-962uigs-5hact2hnt)
ath10kcal_from_file "/sys/firmware/mikrotik/hard_config/wlan_data" 0x5000 0x844
;;
wlr8100)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +1)
;;
esac
;;
"ath10k/pre-cal-pci-0000:00:00.0.bin")
case $board in
archer-c58-v1|\
archer-c59-v1|\
archer-c59-v2|\
archer-c60-v1|\
cf-e355ac-v2|\
cf-e375ac)
ath10kcal_extract "art" 0x5000 0x2f20
ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
;;
archer-c60-v2)
ath10kcal_extract "art" 0x5000 0x2f20
ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -1)
;;
cf-e385ac)
ath10kcal_extract "art" 0x5000 0x2f20
;;
esac
;;
*)
exit 1
;;
esac

24
target/linux/ar71xx/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
View File

@ -1,24 +0,0 @@
#!/bin/ash
[ "$ACTION" == "add" ] || exit 0
PHYNBR=${DEVPATH##*/phy}
[ -n $PHYNBR ] || exit 0
. /lib/functions.sh
. /lib/functions/system.sh
board=$(board_name)
case "$board" in
archer-c58-v1|\
archer-c59-v1|\
archer-c59-v2|\
archer-c60-v1)
echo $(macaddr_add $(mtd_get_mac_binary mac 0x8) $(($PHYNBR - 1)) ) > /sys${DEVPATH}/macaddress
;;
*)
;;
esac

52
target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix
View File

@ -1,52 +0,0 @@
#!/bin/sh
# For AR9220 and AR9223, GPIO JTAG must explicit be disabled
# before LEDs start working. Do this when wifi device is
# detected.
#
# $DEVPATH is not valid for some boards (including WZR-HP-AG300H).
# Manipulate the $DEVPATH to reach the corresponding phyN.
#
devdir=$(dirname $DEVPATH)
devdir=$(dirname $devdir)
phydir=/sys$devdir/ieee80211
[ -d $phydir ] || exit 0
phyname=$(cat $phydir/phy*/name)
[ -z $phyname -o $ACTION != "add" ] && exit 0
#
# ar922x_disable_gpio_jtag():
#
# Emulate
# REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
# for AR9220 and AR9223.
#
ar922x_disable_gpio_jtag() {
local regidx=0x4054
[ -f /sys/kernel/debug/ieee80211/$1/ath9k/regidx ] || return
echo $regidx > /sys/kernel/debug/ieee80211/$1/ath9k/regidx
regval=$(cat /sys/kernel/debug/ieee80211/$1/ath9k/regval)
regval=$((regval | 0x20000))
echo regval $regval
echo $regval > /sys/kernel/debug/ieee80211/$1/ath9k/regval
}
[ $phyname -a $ACTION = "add" ] && {
. /lib/functions.sh
case $(board_name) in
wzr-hp-ag300h)
ar922x_disable_gpio_jtag $phyname
;;
esac;
}
exit 0

3
target/linux/ar71xx/base-files/etc/inittab
View File

@ -1,3 +0,0 @@
::sysinit:/etc/init.d/rcS S boot
::shutdown:/etc/init.d/rcS K shutdown
::askconsole:/usr/libexec/login.sh

108
target/linux/ar71xx/base-files/etc/uci-defaults/03_network-switchX-migration
View File

@ -1,108 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2013 OpenWrt.org
#
SWITCH_NAME_CHANGED=
. /lib/functions.sh
do_change_switch_name() {
local config="$1"
local option=$2
local oldname=$3
local newname=$4
local val
config_get val "$config" $option
[ "$val" != "$oldname" ] && return 0
uci_set network "$config" $option $newname
SWITCH_NAME_CHANGED=1
return 0
}
migrate_switch_name() {
local oldname=$1
local newname=$2
config_load network
logger -t migrate-switchX "Updating switch names in network configuration"
config_foreach do_change_switch_name switch name $oldname $newname
config_foreach do_change_switch_name switch_vlan device $oldname $newname
[ "$SWITCH_NAME_CHANGED" = "1" ] && {
logger -t migrate-switchX "Switch names updated, saving network configuration"
uci commit network
}
}
board=$(board_name)
case "$board" in
airrouter|\
ap121|\
ap121-mini|\
ap96|\
dir-600-a1|\
dir-615-c1|\
dir-615-e1|\
dir-615-e4|\
dir-825-c1|\
ebr-2310-c1|\
ew-dorin|\
ew-dorin-router|\
ja76pf|\
rb-750|\
rb-751|\
tew-632brp|\
tew-712br|\
tl-mr3220|\
tl-mr3220-v2 |\
tl-mr3420|\
tl-wdr4300|\
tl-wr741nd|\
tl-wr741nd-v4|\
tl-wr841n-v7|\
tl-wr1041n-v2|\
whr-g301n|\
whr-hp-g300n|\
whr-hp-gn|\
wrt160nl|\
wzr-hp-ag300h|\
wzr-hp-g300nh2|\
wzr-hp-g450h|\
z1)
migrate_switch_name "eth0" "switch0"
;;
el-m150|\
rb-450)
migrate_switch_name "eth1" "switch0"
;;
db120|\
rb-2011il|\
rb-2011ils|\
rb-2011l|\
rb-2011uas-2hnd)
migrate_switch_name "eth0" "switch0"
migrate_switch_name "eth1" "switch1"
;;
dir-825-b1|\
nbg460n_550n_550nh|\
tew-673gru)
migrate_switch_name "rtl8366s" "switch0"
;;
tl-wr1043nd)
migrate_switch_name "rtl8366rb" "switch0"
;;
esac
exit 0

13
target/linux/ar71xx/base-files/etc/uci-defaults/03_network-vlan-migration
View File

@ -1,13 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2010 OpenWrt.org
#
dev="$(uci -q get network.@switch_vlan[0].device)"
vlan="$(uci -q get network.@switch_vlan[0].vlan)"
if [ "$dev" = "rtl8366s" ] && [ "$vlan" = 0 ]; then
logger -t vlan-migration "VLAN 0 is invalid for RTL8366s, changing to 1"
uci set network.@switch_vlan[0].vlan=1
uci commit network
fi

84
target/linux/ar71xx/base-files/etc/uci-defaults/04_led_migration
View File

@ -1,84 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2013 OpenWrt.org
#
LED_OPTIONS_CHANGED=0
. /lib/functions.sh
do_led_update_sysfs()
{
local cfg=$1; shift
local tuples="$@"
local sysfs
local name
config_get sysfs $cfg sysfs
config_get name $cfg name
[ -z "$sysfs" ] && return
for tuple in $tuples; do
local old=${tuple%=*}
local new=${tuple#*=}
local new_sysfs
new_sysfs=$(echo ${sysfs} | sed "s/${old}/${new}/")
[ "$new_sysfs" = "$sysfs" ] && continue
uci set system.${cfg}.sysfs="${new_sysfs}"
LED_OPTIONS_CHANGED=1
logger -t led-migration "sysfs option of LED \"${name}\" updated to ${new_sysfs}"
done;
}
migrate_leds()
{
config_load system
config_foreach do_led_update_sysfs led "$@"
}
board=$(board_name)
case "$board" in
archer-c7)
migrate_leds ":blue:=:green:"
;;
dhp-1565-a1|\
dir-825-c1|\
dir-835-a1)
migrate_leds ":orange:=:amber:" ":wifi_bgn=:wlan2g"
;;
dr344)
migrate_leds ":red:=:green:" ":yellow:=:green:"
;;
gl-ar150)
migrate_leds "gl-ar150:wlan=gl-ar150:orange:wlan" "gl-ar150:lan=gl-ar150:green:lan" "gl-ar150:wan=gl-ar150:green:wan"
;;
oolite-v1)
migrate_leds "oolite:=${board}"
;;
wndap360|\
wndr3700|\
wnr2000|\
wnr2200)
migrate_leds "${board}:=netgear:"
;;
wndr3700v4|\
wndr4300)
migrate_leds ":orange:=:amber:"
;;
wnr1000-v2)
migrate_leds "wnr1000v2:=netgear:"
;;
wnr612-v2)
migrate_leds "wnr612v2:=netgear:"
;;
esac
[ "$LED_OPTIONS_CHANGED" = "1" ] && uci commit system
exit 0

28
target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-checksum
View File

@ -1,28 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2010 OpenWrt.org
#
. /lib/functions.sh
board=$(board_name)
fixtrx() {
mtd -o 32 fixtrx firmware
}
fixwrgg() {
local kernel_size=$(sed -n 's/mtd[0-9]*: \([0-9a-f]*\).*"kernel".*/\1/p' /proc/mtd)
[ "$kernel_size" ] && mtd -c 0x$kernel_size fixwrgg firmware
}
case "$board" in
mynet-rext |\
wrt160nl)
fixtrx
;;
dap-2695-a1)
fixwrgg
;;
esac

17
target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-seama-header
View File

@ -1,17 +0,0 @@
#!/bin/sh
. /lib/functions.sh
fix_seama_header() {
local kernel_size=$(sed -n 's/mtd[0-9]*: \([0-9a-f]*\).*"kernel".*/\1/p' /proc/mtd)
[ "$kernel_size" ] && mtd -c 0x$kernel_size fixseama firmware
}
board=$(board_name)
case "$board" in
dir-869-a1)
fix_seama_header
;;
esac

1589
target/linux/ar71xx/base-files/lib/ar71xx.sh
View File

File diff suppressed because it is too large Load Diff

9
target/linux/ar71xx/base-files/lib/preinit/01_preinit_do_ar71xx.sh
View File

@ -1,9 +0,0 @@
#!/bin/sh
do_ar71xx() {
. /lib/ar71xx.sh
ar71xx_board_detect
}
boot_hook_add preinit_main do_ar71xx

60
target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx
View File

@ -1,60 +0,0 @@
#
# Copyright (C) 2009 OpenWrt.org
#
fetch_mac_from_mtd() {
local mtd_part=$1
local lan_env=$2
local wan_env=$3
local mtd mac
mtd=$(grep $mtd_part /proc/mtd | cut -d: -f1)
[ -z $mtd ] && return
mac=$(grep $lan_env /dev/$mtd | cut -d= -f2)
[ ! -z $mac ] && ifconfig eth0 hw ether $mac 2>/dev/null
mac=$(grep $wan_env /dev/$mtd | cut -d= -f2)
[ ! -z $mac ] && ifconfig eth1 hw ether $mac 2>/dev/null
}
preinit_set_mac_address() {
. /lib/functions.sh
case $(board_name) in
c-55|\
c-60)
mac_lan=$(mtd_get_mac_binary art 0x0)
[ -n "$mac_lan" ] && ifconfig eth0 hw ether "$mac_lan"
;;
dir-615-c1|\
tew-632brp)
fetch_mac_from_mtd config lan_mac wan_mac
;;
dir-615-i1)
fetch_mac_from_mtd nvram sys_lan_mac sys_wan_mac
;;
mr18|\
z1)
mac_lan=$(mtd_get_mac_binary_ubi board-config 0x66)
[ -n "$mac_lan" ] && ifconfig eth0 hw ether "$mac_lan"
;;
r6100)
mac_lan=$(mtd_get_mac_binary caldata 0x0)
[ -n "$mac_lan" ] && ifconfig eth1 hw ether "$mac_lan"
mac_wan=$(mtd_get_mac_binary caldata 0x6)
[ -n "$mac_wan" ] && ifconfig eth0 hw ether "$mac_wan"
;;
rambutan)
mac_lan=$(mtd_get_mac_binary art 0x0)
[ -n "$mac_lan" ] && ifconfig eth0 hw ether "$mac_lan"
mac_wan=$(mtd_get_mac_binary art 0x6)
[ -n "$mac_wan" ] && ifconfig eth1 hw ether "$mac_wan"
;;
wrt160nl)
fetch_mac_from_mtd nvram lan_hwaddr wan_hwaddr
;;
esac
}
boot_hook_add preinit_main preinit_set_mac_address

57
target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx
View File

@ -1,57 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2009 OpenWrt.org
#
set_preinit_iface() {
. /lib/functions.sh
case $(board_name) in
alfa-ap96|\
alfa-nx|\
ap135-020|\
ap136-020|\
ap147-010|\
archer-c5|\
archer-c7|\
bhr-4grv2|\
dir-505-a1|\
gl-ar750|\
gl-inet|\
jwap003|\
pb42|\
pb44|\
rb-433|\
rb-433u|\
rb-435g|\
rb-450|\
rb-450g|\
routerstation|\
routerstation-pro|\
smart-300|\
tl-mr3420-v2|\
tl-wdr4900-v2|\
tl-wr1043nd-v2|\
tl-wr710n|\
tl-wr720n-v3|\
tl-wr841n-v8|\
tl-wr842n-v2|\
tl-wr940n-v4|\
tl-wr940n-v6|\
tl-wr941nd-v6|\
wnr1000-v2|\
wnr2000-v3|\
wnr2200|\
wnr612-v2|\
wpe72|\
wpn824n)
ifname=eth1
;;
*)
ifname=eth0
;;
esac
}
boot_hook_add preinit_main set_preinit_iface

50
target/linux/ar71xx/base-files/lib/preinit/82_patch_ath10k
View File

@ -1,50 +0,0 @@
#!/bin/sh
. /lib/functions.sh
. /lib/functions/system.sh
do_patch_ath10k_firmware() {
local firmware_file="/lib/firmware/ath10k/QCA988X/hw2.0/firmware-5.bin"
# bail out if firmware does not exist
[ -f "$firmware_file" ] || return
local mac_offset=276
local mac_length=6
local default_mac="00:03:07:12:34:56"
local current_mac="$(hexdump -v -n $mac_length -s $mac_offset -e '5/1 "%02x:" 1/1 "%02x"' $firmware_file 2>/dev/null)"
# check if mac address was already patched
[ "$default_mac" = "$current_mac" ] || return
# some boards have bogus mac in otp (= directly in the PCIe card's EEPROM).
# we have to patch the default mac in the firmware because we cannot change
# the otp.
case $(board_name) in
dgl-5500-a1|\
tew-823dru)
local mac
mac=$(mtd_get_mac_ascii nvram wlan1_mac)
cp $firmware_file /tmp/ath10k-firmware.bin
macaddr_2bin $mac | dd of=/tmp/ath10k-firmware.bin \
conv=notrunc bs=1 seek=$mac_offset count=$mac_length
;;
esac
[ -f /tmp/ath10k-firmware.bin ] || return
cp /tmp/ath10k-firmware.bin $firmware_file
rm /tmp/ath10k-firmware.bin
}
check_patch_ath10k_firmware() {
case $(board_name) in
dgl-5500-a1|\
tew-823dru)
do_patch_ath10k_firmware
;;
esac
}
boot_hook_add preinit_main check_patch_ath10k_firmware

155
target/linux/ar71xx/base-files/lib/upgrade/allnet.sh
View File

@ -1,155 +0,0 @@
# The U-Boot loader of the some Allnet devices requires image sizes and
# checksums to be provided in the U-Boot environment.
# In case the check fails during boot, a failsafe-system is started to provide
# a minimal web-interface for flashing a new firmware.
# determine size of the main firmware partition
platform_get_firmware_size() {
local dev size erasesize name
while read dev size erasesize name; do
name=${name#'"'}; name=${name%'"'}
case "$name" in
firmware)
printf "%d" "0x$size"
break
;;
esac
done < /proc/mtd
}
# get the first 4 bytes (magic) of a given file starting at offset in hex format
get_magic_long_at() {
dd if="$1" skip=$(( $CI_BLKSZ / 4 * $2 )) bs=4 count=1 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
get_filesize() {
wc -c "$1" | while read image_size _n ; do echo $image_size ; break; done
}
# scan through the update image pages until matching a magic
platform_get_offset() {
offsetcount=0
magiclong="x"
if [ -n "$3" ]; then
offsetcount=$3
fi
while magiclong=$( get_magic_long_at "$1" "$offsetcount" ) && [ -n "$magiclong" ]; do
case "$magiclong" in
"2705"*)
# U-Boot image magic
if [ "$2" = "uImage" ]; then
echo $offsetcount
return
fi
;;
"68737173"|"73717368")
# SquashFS
if [ "$2" = "rootfs" ]; then
echo $offsetcount
return
fi
;;
"deadc0de"|"19852003")
# JFFS2 empty page
if [ "$2" = "rootfs-data" ]; then
echo $offsetcount
return
fi
;;
esac
offsetcount=$(( $offsetcount + 1 ))
done
}
platform_check_image_allnet() {
local fw_printenv=/usr/sbin/fw_printenv
[ ! -n "$fw_printenv" -o ! -x "$fw_printenv" ] && {
echo "Please install uboot-envtools!"
return 1
}
[ ! -r "/etc/fw_env.config" ] && {
echo "/etc/fw_env.config is missing"
return 1
}
local image_size=$( get_filesize "$1" )
local firmware_size=$( platform_get_firmware_size )
[ $image_size -ge $firmware_size ] &&
{
echo "upgrade image is too big (${image_size}b > ${firmware_size}b)"
}
local vmlinux_blockoffset=$( platform_get_offset "$1" uImage )
[ -z $vmlinux_blockoffset ] && {
echo "vmlinux-uImage not found"
return 1
}
local rootfs_blockoffset=$( platform_get_offset "$1" rootfs "$vmlinux_blockoffset" )
[ -z $rootfs_blockoffset ] && {
echo "missing rootfs"
return 1
}
local data_blockoffset=$( platform_get_offset "$1" rootfs-data "$rootfs_blockoffset" )
[ -z $data_blockoffset ] && {
echo "rootfs doesn't have JFFS2 end marker"
return 1
}
return 0
}
platform_do_upgrade_allnet() {
local firmware_base_addr=$( printf "%d" "$1" )
local vmlinux_blockoffset=$( platform_get_offset "$2" uImage )
if [ ! -n "$vmlinux_blockoffset" ]; then
echo "can't determine uImage offset"
return 1
fi
local rootfs_blockoffset=$( platform_get_offset "$2" rootfs $(( $vmlinux_blockoffset + 1 )) )
local vmlinux_offset=$(( $vmlinux_blockoffset * $CI_BLKSZ ))
local vmlinux_addr=$(( $firmware_base_addr + $vmlinux_offset ))
local vmlinux_hexaddr=0x$( printf "%08x" "$vmlinux_addr" )
if [ ! -n "$rootfs_blockoffset" ]; then
echo "can't determine rootfs offset"
return 1
fi
local rootfs_offset=$(( $rootfs_blockoffset * $CI_BLKSZ ))
local rootfs_addr=$(( $firmware_base_addr + $rootfs_offset ))
local rootfs_hexaddr=0x$( printf "%08x" "$rootfs_addr" )
local vmlinux_blockcount=$(( $rootfs_blockoffset - $vmlinux_blockoffset ))
local vmlinux_size=$(( $rootfs_offset - $vmlinux_offset ))
local vmlinux_hexsize=0x$( printf "%08x" "$vmlinux_size" )
local data_blockoffset=$( platform_get_offset "$2" rootfs-data $(( $rootfs_blockoffset + 1 )) )
if [ ! -n "$data_blockoffset" ]; then
echo "can't determine rootfs size"
return 1
fi
local data_offset=$(( $data_blockoffset * $CI_BLKSZ ))
local rootfs_blockcount=$(( $data_blockoffset - $rootfs_blockoffset ))
local rootfs_size=$(( $data_offset - $rootfs_offset ))
local rootfs_hexsize=0x$( printf "%08x" "$rootfs_size" )
local rootfs_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$rootfs_blockoffset count=$rootfs_blockcount 2>/dev/null | md5sum -); rootfs_md5="${rootfs_md5%% *}"
local vmlinux_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$vmlinux_blockoffset count=$vmlinux_blockcount 2>/dev/null | md5sum -); vmlinux_md5="${vmlinux_md5%% *}"
# this needs a recent version of uboot-envtools!
cat >/tmp/fw_env_upgrade <<EOF
vmlinux_start_addr $vmlinux_hexaddr
vmlinux_size $vmlinux_hexsize
vmlinux_checksum $vmlinux_md5
rootfs_start_addr $rootfs_hexaddr
rootfs_size $rootfs_hexsize
rootfs_checksum $rootfs_md5
bootcmd bootm $vmlinux_hexaddr
EOF
mkdir -p /var/lock
fw_setenv -s /tmp/fw_env_upgrade || {
echo "failed to update U-Boot environment"
return 1
}
shift
default_do_upgrade "$@"
}

165
target/linux/ar71xx/base-files/lib/upgrade/dir825.sh
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@ -1,165 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2012 OpenWrt.org
#
. /lib/functions.sh
. /lib/ar71xx.sh
get_magic_at() {
local mtddev=$1
local pos=$2
dd bs=1 count=2 skip=$pos if=$mtddev 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
dir825b_is_caldata_valid() {
local mtddev=$1
local magic
magic=$(get_magic_at $mtddev 4096)
[ "$magic" != "a55a" ] && return 0
magic=$(get_magic_at $mtddev 20480)
[ "$magic" != "a55a" ] && return 0
return 1
}
dir825b_copy_caldata() {
local cal_src=$1
local cal_dst=$2
local mtd_src
local mtd_dst
local md5_src
local md5_dst
mtd_src=$(find_mtd_part $cal_src)
[ -z "$mtd_src" ] && {
echo "no $cal_src partition found"
return 1
}
mtd_dst=$(find_mtd_part $cal_dst)
[ -z "$mtd_dst" ] && {
echo "no $cal_dst partition found"
return 1
}
dir825b_is_caldata_valid "$mtd_src" && {
echo "no valid calibration data found in $cal_src"
return 1
}
dir825b_is_caldata_valid "$mtd_dst" && {
echo "Copying calibration data from $cal_src to $cal_dst..."
dd if="$mtd_src" 2>/dev/null | mtd -q -q write - "$cal_dst"
}
md5_src=$(md5sum "$mtd_src") && md5_src="${md5_src%% *}"
md5_dst=$(md5sum "$mtd_dst") && md5_dst="${md5_dst%% *}"
[ "$md5_src" != "$md5_dst" ] && {
echo "calibration data mismatch $cal_src:$md5_src $cal_dst:$md5_dst"
return 1
}
return 0
}
dir825b_do_upgrade_combined() {
local fw_part=$1
local fw_file=$2
local fw_mtd=$(find_mtd_part $fw_part)
local fw_length=0x$(dd if="$fw_file" bs=2 skip=1 count=4 2>/dev/null)
local fw_blocks=$(($fw_length / 65536))
if [ -n "$fw_mtd" ] && [ ${fw_blocks:-0} -gt 0 ]; then
local append=""
[ -f "$UPGRADE_BACKUP" ] && append="-j $UPGRADE_BACKUP"
sync
dd if="$fw_file" bs=64k skip=1 count=$fw_blocks 2>/dev/null | \
mtd $append write - "$fw_part"
fi
}
dir825b_check_image() {
local magic="$(get_magic_long "$1")"
local fw_mtd=$(find_mtd_part "firmware_orig")
case "$magic" in
"27051956")
;;
"43493030")
local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null)
local md5_chk=$(dd if="$1" bs=64k skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}"
local fw_len=$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null)
local fw_part_len=$(mtd_get_part_size "firmware")
if [ -z "$fw_mtd" ]; then
ask_bool 0 "Do you have a backup of the caldata partition?" || {
echo "Warning, please make sure that you have a backup of the caldata partition."
echo "Once you have that, use 'sysupgrade -i' for upgrading to the 'fat' firmware."
return 1
}
fi
if [ -z "$md5_img" -o -z "$md5_chk" ]; then
echo "Unable to get image checksums. Maybe you are using a streamed image?"
return 1
fi
if [ "$md5_img" != "$md5_chk" ]; then
echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)"
return 1
fi
fw_len=$((0x$fw_len))
fw_part_len=${fw_part_len:-0}
if [ $fw_part_len -lt $fw_len ]; then
echo "The upgrade image is too big (size:$fw_len available:$fw_part_len)"
return 1
fi
;;
*)
echo "Unsupported image format."
return 1
;;
esac
return 0
}
platform_do_upgrade_dir825b() {
local magic="$(get_magic_long "$1")"
local fw_mtd=$(find_mtd_part "firmware_orig")
case "$magic" in
"27051956")
if [ -n "$fw_mtd" ]; then
# restore calibration data before downgrading to
# the normal image
dir825b_copy_caldata "caldata" "caldata_orig" || {
echo "unable to restore calibration data"
exit 1
}
PART_NAME="firmware_orig"
else
PART_NAME="firmware"
fi
default_do_upgrade "$1"
;;
"43493030")
if [ -z "$fw_mtd" ]; then
# backup calibration data before upgrading to the
# fat image
dir825b_copy_caldata "caldata" "caldata_copy" || {
echo "unable to backup calibration data"
exit 1
}
fi
dir825b_do_upgrade_combined "firmware" "$1"
;;
esac
}

165
target/linux/ar71xx/base-files/lib/upgrade/merakinand.sh
View File

@ -1,165 +0,0 @@
#!/bin/sh
#
# Copyright (C) 2015-2016 Chris Blake <chrisrblake93@gmail.com>
#
# Custom upgrade script for Meraki NAND devices (ex. MR18)
# Based on dir825.sh and stock nand functions
#
. /lib/ar71xx.sh
. /lib/functions.sh
get_magic_at() {
local mtddev=$1
local pos=$2
dd bs=1 count=2 skip=$pos if=$mtddev 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
meraki_is_caldata_valid() {
local board=$1
local mtddev=$2
local magic
case "$board" in
"mr18")
magic=$(get_magic_at $mtddev 4096)
[ "$magic" != "0202" ] && return 0
magic=$(get_magic_at $mtddev 20480)
[ "$magic" != "0202" ] && return 0
magic=$(get_magic_at $mtddev 36864)
[ "$magic" != "0202" ] && return 0
return 1
;;
"z1")
magic=$(get_magic_at $mtddev 4096)
[ "$magic" != "0202" ] && return 0
magic=$(get_magic_at $mtddev 86016)
[ "$magic" != "a55a" ] && return 0
return 1
;;
*)
return 1
;;
esac
}
merakinand_copy_caldata() {
local cal_src=$1
local cal_dst=$2
local ubidev="$(nand_find_ubi $CI_UBIPART)"
local board_name="$(board_name)"
local rootfs_size="$(ubinfo /dev/ubi0 -N rootfs_data | grep "Size" | awk '{ print $6 }')"
# Setup partitions using board name, in case of future platforms
case "$board_name" in
"mr18"|\
"z1")
# Src is MTD
mtd_src="$(find_mtd_chardev $cal_src)"
[ -n "$mtd_src" ] || {
echo "no mtd device found for partition $cal_src"
exit 1
}
# Dest is UBI
# TODO: possibly add create (hard to do when rootfs_data is expanded & mounted)
# Would need to be done from ramdisk
mtd_dst="$(nand_find_volume $ubidev $cal_dst)"
[ -n "$mtd_dst" ] || {
echo "no ubi device found for partition $cal_dst"
exit 1
}
meraki_is_caldata_valid "$board_name" "$mtd_src" && {
echo "no valid calibration data found in $cal_src"
exit 1
}
meraki_is_caldata_valid "$board_name" "/dev/$mtd_dst" && {
echo "Copying calibration data from $cal_src to $cal_dst..."
dd if="$mtd_src" of=/tmp/caldata.tmp 2>/dev/null
ubiupdatevol "/dev/$mtd_dst" /tmp/caldata.tmp
rm /tmp/caldata.tmp
sync
}
return 0
;;
*)
echo "Unsupported device $board_name";
return 1
;;
esac
}
merakinand_do_kernel_check() {
local board_name="$1"
local tar_file="$2"
local image_magic_word=`(tar xf $tar_file sysupgrade-$board_name/kernel -O 2>/dev/null | dd bs=1 count=4 skip=0 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"')`
# What is our kernel magic string?
case "$board_name" in
"mr18")
[ "$image_magic_word" == "8e73ed8a" ] && {
echo "pass" && return 0
}
;;
"z1")
[ "$image_magic_word" == "4d495053" ] && {
echo "pass" && return 0
}
;;
esac
exit 1
}
merakinand_do_platform_check() {
local board_name="$1"
local tar_file="$2"
local control_length=`(tar xf $tar_file sysupgrade-$board_name/CONTROL -O | wc -c) 2> /dev/null`
local file_type="$(identify_tar $2 sysupgrade-$board_name/root)"
local kernel_magic="$(merakinand_do_kernel_check $1 $2)"
case "$board_name" in
"mr18"|\
"z1")
[ "$control_length" = 0 -o "$file_type" != "squashfs" -o "$kernel_magic" != "pass" ] && {
echo "Invalid sysupgrade file for $board_name"
return 1
}
;;
*)
echo "Unsupported device $board_name";
return 1
;;
esac
return 0
}
merakinand_do_upgrade() {
local tar_file="$1"
local board_name="$(board_name)"
# Do we need to do any platform tweaks?
case "$board_name" in
"mr18")
# Check and create UBI caldata if it's invalid
merakinand_copy_caldata "odm-caldata" "caldata"
nand_do_upgrade $1
;;
"z1")
# Check and create UBI caldata if it's invalid
merakinand_copy_caldata "origcaldata" "caldata"
nand_do_upgrade $1
;;
*)
echo "Unsupported device $board_name";
exit 1
;;
esac
}

232
target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh
View File

@ -1,232 +0,0 @@
# The U-Boot loader of the OpenMesh devices requires image sizes and
# checksums to be provided in the U-Boot environment.
# The OpenMesh devices come with 2 main partitions - while one is active
# sysupgrade will flash the other. The boot order is changed to boot the
# newly flashed partition. If the new partition can't be booted due to
# upgrade failures the previously used partition is loaded.
trim()
{
echo $1
}
cfg_value_get()
{
local cfg=$1 cfg_opt
local section=$2 our_section=0
local param=$3 our_param=
for cfg_opt in $cfg
do
[ "$cfg_opt" = "[$section]" ] && our_section=1 && continue
[ "$our_section" = "1" ] || continue
our_param=$(echo ${cfg_opt%%=*})
[ "$param" = "$our_param" ] && echo ${cfg_opt##*=} && break
done
}
platform_check_image_target_openmesh()
{
img_board_target="$1"
case "$img_board_target" in
A60)
[ "$board" = "a40" ] && return 0
[ "$board" = "a60" ] && return 0
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
OM2P)
[ "$board" = "om2p" ] && return 0
[ "$board" = "om2pv2" ] && return 0
[ "$board" = "om2pv4" ] && return 0
[ "$board" = "om2p-lc" ] && return 0
[ "$board" = "om2p-hs" ] && return 0
[ "$board" = "om2p-hsv2" ] && return 0
[ "$board" = "om2p-hsv3" ] && return 0
[ "$board" = "om2p-hsv4" ] && return 0
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
OM5P)
[ "$board" = "om5p" ] && return 0
[ "$board" = "om5p-an" ] && return 0
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
OM5PAC)
[ "$board" = "om5p-ac" ] && return 0
[ "$board" = "om5p-acv2" ] && return 0
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
MR1750)
[ "$board" = "mr1750" ] && return 0
[ "$board" = "mr1750v2" ] && return 0
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
MR600)
[ "$board" = "mr600" ] && return 0
[ "$board" = "mr600v2" ] && return 0
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
MR900)
[ "$board" = "mr900" ] && return 0
[ "$board" = "mr900v2" ] && return 0
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
*)
echo "Invalid board target ($img_board_target). Use the correct image for this platform"
return 1
;;
esac
}
platform_check_image_openmesh()
{
local img_magic=$1
local img_path=$2
local fw_printenv=/usr/sbin/fw_printenv
local img_board_target= img_num_files= i=0
local cfg_name= kernel_name= rootfs_name=
case "$img_magic" in
# Combined Extended Image v1
43453031)
img_board_target=$(trim $(dd if="$img_path" bs=4 skip=1 count=8 2>/dev/null))
img_num_files=$(trim $(dd if="$img_path" bs=2 skip=18 count=1 2>/dev/null))
;;
*)
echo "Invalid image ($img_magic). Use combined extended images on this platform"
return 1
;;
esac
platform_check_image_target_openmesh "$img_board_target" || return 1
[ $img_num_files -lt 3 ] && {
echo "Invalid number of embedded images ($img_num_files). Use the correct image for this platform"
return 1
}
cfg_name=$(trim $(dd if="$img_path" bs=2 skip=19 count=16 2>/dev/null))
[ "$cfg_name" != "fwupgrade.cfg" ] && {
echo "Invalid embedded config file ($cfg_name). Use the correct image for this platform"
return 1
}
kernel_name=$(trim $(dd if="$img_path" bs=2 skip=55 count=16 2>/dev/null))
[ "$kernel_name" != "kernel" ] && {
echo "Invalid embedded kernel file ($kernel_name). Use the correct image for this platform"
return 1
}
rootfs_name=$(trim $(dd if="$img_path" bs=2 skip=91 count=16 2>/dev/null))
[ "$rootfs_name" != "rootfs" ] && {
echo "Invalid embedded kernel file ($rootfs_name). Use the correct image for this platform"
return 1
}
[ ! -x "$fw_printenv" ] && {
echo "Please install uboot-envtools!"
return 1
}
[ ! -r "/etc/fw_env.config" ] && {
echo "/etc/fw_env.config is missing"
return 1
}
return 0
}
platform_do_upgrade_openmesh()
{
local img_path=$1 img_board_target=
local kernel_start_addr= kernel_start_addr1= kernel_start_addr2=
local kernel_size= kernel_md5=
local rootfs_size= rootfs_checksize= rootfs_md5=
local kernel_bsize= total_size=
local data_offset=$((64 * 1024)) block_size= offset=
local uboot_env_upgrade="/tmp/fw_env_upgrade"
local cfg_size= kernel_size= rootfs_size=
local append=""
[ -f "$UPGRADE_BACKUP" ] && append="-j $UPGRADE_BACKUP"
cfg_size=$(dd if="$img_path" bs=2 skip=35 count=4 2>/dev/null)
kernel_size=$(dd if="$img_path" bs=2 skip=71 count=4 2>/dev/null)
rootfs_size=$(dd if="$img_path" bs=2 skip=107 count=4 2>/dev/null)
img_board_target=$(trim $(dd if="$img_path" bs=4 skip=1 count=8 2>/dev/null))
cfg_content=$(dd if="$img_path" bs=1 skip=$data_offset count=$(echo $((0x$cfg_size))) 2>/dev/null)
case $img_board_target in
OM2P)
block_size=$((256 * 1024))
total_size=7340032
kernel_start_addr1=0x9f1c0000
kernel_start_addr2=0x9f8c0000
;;
OM5P|OM5PAC|MR600|MR900|MR1750|A60)
block_size=$((64 * 1024))
total_size=7995392
kernel_start_addr1=0x9f0b0000
kernel_start_addr2=0x9f850000
;;
esac
kernel_md5=$(cfg_value_get "$cfg_content" "vmlinux" "md5sum")
rootfs_md5=$(cfg_value_get "$cfg_content" "rootfs" "md5sum")
rootfs_checksize=$(cfg_value_get "$cfg_content" "rootfs" "checksize")
if [ "$((0x$kernel_size % $block_size))" = "0" ]
then
kernel_bsize=$(echo $((0x$kernel_size)))
else
kernel_bsize=$((0x$kernel_size + ($block_size - (0x$kernel_size % $block_size))))
fi
mtd -q erase inactive
offset=$(echo $(($data_offset + 0x$cfg_size + 0x$kernel_size)))
dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$rootfs_size))) 2>&- | mtd -n -p $kernel_bsize $append write - "inactive"
offset=$(echo $(($data_offset + 0x$cfg_size)))
dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$kernel_size))) 2>&- | mtd -n write - "inactive"
rm $uboot_env_upgrade 2>&-
if [ "$(grep 'mtd3:.*inactive' /proc/mtd)" ]
then
printf "kernel_size_1 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade
printf "rootfs_size_1 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade
printf "bootseq 1,2\n" >> $uboot_env_upgrade
kernel_start_addr=$kernel_start_addr1
else
printf "kernel_size_2 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade
printf "rootfs_size_2 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade
printf "bootseq 2,1\n" >> $uboot_env_upgrade
kernel_start_addr=$kernel_start_addr2
fi
printf "vmlinux_start_addr %s\n" $kernel_start_addr >> $uboot_env_upgrade
printf "vmlinux_size 0x%s\n" $kernel_size >> $uboot_env_upgrade
printf "vmlinux_checksum %s\n" $kernel_md5 >> $uboot_env_upgrade
printf "rootfs_start_addr 0x%x\n" $(($kernel_start_addr + $kernel_bsize)) >> $uboot_env_upgrade
printf "rootfs_size %s\n" $rootfs_checksize >> $uboot_env_upgrade
printf "rootfs_checksum %s\n" $rootfs_md5 >> $uboot_env_upgrade
mkdir -p /var/lock
fw_setenv -s $uboot_env_upgrade || {
echo "failed to update U-Boot environment"
return 1
}
}

915
target/linux/ar71xx/base-files/lib/upgrade/platform.sh
View File

@ -1,915 +0,0 @@
#
# Copyright (C) 2011 OpenWrt.org
#
. /lib/functions/system.sh
. /lib/ar71xx.sh
PART_NAME=firmware
RAMFS_COPY_DATA='/lib/ar71xx.sh /etc/fw_env.config /var/lock/fw_printenv.lock'
RAMFS_COPY_BIN='nandwrite fw_printenv fw_setenv'
CI_BLKSZ=65536
CI_LDADR=0x80060000
PLATFORM_DO_UPGRADE_COMBINED_SEPARATE_MTD=0
platform_find_partitions() {
local first dev size erasesize name
while read dev size erasesize name; do
name=${name#'"'}; name=${name%'"'}
case "$name" in
vmlinux.bin.l7|vmlinux|kernel|linux|linux.bin|rootfs|filesystem)
if [ -z "$first" ]; then
first="$name"
else
echo "$erasesize:$first:$name"
break
fi
;;
esac
done < /proc/mtd
}
platform_find_kernelpart() {
local part
for part in "${1%:*}" "${1#*:}"; do
case "$part" in
vmlinux.bin.l7|vmlinux|kernel|linux|linux.bin)
echo "$part"
break
;;
esac
done
}
platform_find_rootfspart() {
local part
for part in "${1%:*}" "${1#*:}"; do
[ "$part" != "$2" ] && echo "$part" && break
done
}
platform_do_upgrade_combined() {
local partitions=$(platform_find_partitions)
local kernelpart=$(platform_find_kernelpart "${partitions#*:}")
local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}"
local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null)
local kern_blocks=$(($kern_length / $CI_BLKSZ))
local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ))
if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \
[ ${kern_blocks:-0} -gt 0 ] && \
[ ${root_blocks:-0} -gt 0 ] && \
[ ${erase_size:-0} -gt 0 ];
then
local rootfspart=$(platform_find_rootfspart "$partitions" "$kernelpart")
local append=""
[ -f "$UPGRADE_BACKUP" ] && append="-j $UPGRADE_BACKUP"
if [ "$PLATFORM_DO_UPGRADE_COMBINED_SEPARATE_MTD" -ne 1 ]; then
( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \
dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \
mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions
elif [ -n "$rootfspart" ]; then
dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null | \
mtd write - $kernelpart
dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null | \
mtd -r $append write - $rootfspart
fi
fi
PLATFORM_DO_UPGRADE_COMBINED_SEPARATE_MTD=0
}
tplink_get_image_hwid() {
get_image "$@" | dd bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
tplink_get_image_mid() {
get_image "$@" | dd bs=4 count=1 skip=17 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
tplink_get_image_boot_size() {
get_image "$@" | dd bs=4 count=1 skip=37 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
tplink_pharos_check_support_list() {
local image="$1"
local offset="$2"
local model="$3"
local trargs="$4"
# Here $image is given to dd directly instead of using get_image;
# otherwise the skip will take almost a second (as dd can't seek)
dd if="$image" bs=1 skip=$offset count=1024 2>/dev/null | tr -d "$trargs" | (
while IFS= read -r line; do
[ "$line" = "$model" ] && exit 0
done
exit 1
)
}
tplink_pharos_check_image() {
local image_magic="$(get_magic_long "$1")"
local board_magic="$2"
[ "$image_magic" != "$board_magic" ] && {
echo "Invalid image magic '$image_magic'. Expected '$board_magic'."
return 1
}
local model_string="$3"
local trargs="$4"
# New images have the support list at 7802888, old ones at 1511432
tplink_pharos_check_support_list "$1" 7802888 "$model_string" "$trargs" || \
tplink_pharos_check_support_list "$1" 1511432 "$model_string" "$trargs" || {
echo "Unsupported image (model not in support-list)"
return 1
}
return 0
}
seama_get_type_magic() {
get_image "$@" | dd bs=1 count=4 skip=53 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
wrgg_get_image_magic() {
get_image "$@" | dd bs=4 count=1 skip=8 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
cybertan_get_image_magic() {
get_image "$@" | dd bs=8 count=1 skip=0 2>/dev/null | hexdump -v -n 8 -e '1/1 "%02x"'
}
cybertan_check_image() {
local magic="$(cybertan_get_image_magic "$1")"
local fw_magic="$(cybertan_get_hw_magic)"
[ "$fw_magic" != "$magic" ] && {
echo "Invalid image, ID mismatch, got:$magic, but need:$fw_magic"
return 1
}
return 0
}
platform_do_upgrade_compex() {
local fw_file=$1
local fw_part=$PART_NAME
local fw_mtd=$(find_mtd_part $fw_part)
local fw_length=0x$(dd if="$fw_file" bs=2 skip=1 count=4 2>/dev/null)
local fw_blocks=$(($fw_length / 65536))
if [ -n "$fw_mtd" ] && [ ${fw_blocks:-0} -gt 0 ]; then
local append=""
[ -f "$UPGRADE_BACKUP" ] && append="-j $UPGRADE_BACKUP"
sync
dd if="$fw_file" bs=64k skip=1 count=$fw_blocks 2>/dev/null | \
mtd $append write - "$fw_part"
fi
}
alfa_check_image() {
local magic_long="$(get_magic_long "$1")"
local fw_part_size=$(mtd_get_part_size firmware)
case "$magic_long" in
"27051956")
[ "$fw_part_size" != "16318464" ] && {
echo "Invalid image magic \"$magic_long\" for $fw_part_size bytes"
return 1
}
;;
"68737173")
[ "$fw_part_size" != "7929856" ] && {
echo "Invalid image magic \"$magic_long\" for $fw_part_size bytes"
return 1
}
;;
esac
return 0
}
platform_check_image() {
local board=$(board_name)
local magic="$(get_magic_word "$1")"
local magic_long="$(get_magic_long "$1")"
[ "$#" -gt 1 ] && return 1
case "$board" in
airgateway|\
airgatewaypro|\
airrouter|\
ap121f|\
ap132|\
ap531b0|\
ap90q|\
archer-c25-v1|\
archer-c58-v1|\
archer-c59-v1|\
archer-c59-v2|\
archer-c60-v1|\
archer-c60-v2|\
archer-c7-v4|\
archer-c7-v5|\
arduino-yun|\
bullet-m|\
bullet-m-xw|\
c-55|\
carambola2|\
cf-e316n-v2|\
cf-e320n-v2|\
cf-e355ac-v1|\
cf-e355ac-v2|\
cf-e375ac|\
cf-e380ac-v1|\
cf-e380ac-v2|\
cf-e385ac|\
cf-e520n|\
cf-e530n|\
cpe505n|\
cpe830|\
cpe870|\
dap-1330-a1|\
dgl-5500-a1|\
dhp-1565-a1|\
dir-505-a1|\
dir-600-a1|\
dir-615-c1|\
dir-615-e1|\
dir-615-e4|\
dir-615-i1|\
dir-825-c1|\
dir-835-a1|\
dlan-hotspot|\
dlan-pro-1200-ac|\
dlan-pro-500-wp|\
dr342|\
dr531|\
dragino2|\
e1700ac-v2|\
e558-v2|\
e600g-v2|\
e600gac-v2|\
e750a-v4|\
e750g-v8|\
ebr-2310-c1|\
ens202ext|\
epg5000|\
esr1750|\
esr900|\
ew-balin|\
ew-dorin|\
ew-dorin-router|\
gl-ar150|\
gl-ar300m|\
gl-ar300|\
gl-ar750|\
gl-ar750s|\
gl-domino|\
gl-mifi|\
gl-usb150|\
hiwifi-hc6361|\
hornet-ub-x2|\
jwap230|\
lbe-m5|\
lima|\
loco-m-xw|\
mzk-w04nu|\
mzk-w300nh|\
n5q|\
nanostation-m|\
nanostation-m-xw|\
nbg460n_550n_550nh|\
pqi-air-pen|\
r36a|\
r602n|\
rme-eg200|\
rocket-m|\
rocket-m-ti|\
rocket-m-xw|\
rw2458n|\
sc1750|\
sc300m|\
sc450|\
sr3200|\
t830|\
tew-632brp|\
tew-712br|\
tew-732br|\
tew-823dru|\
tl-wr1043n-v5|\
tl-wr942n-v1|\
unifi|\
unifi-outdoor|\
unifiac-lite|\
unifiac-pro|\
wam250|\
weio|\
whr-g301n|\
whr-hp-g300n|\
whr-hp-gn|\
wlae-ag300n|\
wndap360|\
wpj342|\
wpj344|\
wpj531|\
wpj558|\
wpj563|\
wrt400n|\
wrtnode2q|\
wzr-450hp2|\
wzr-hp-ag300h|\
wzr-hp-g300nh|\
wzr-hp-g300nh2|\
wzr-hp-g450h|\
xd3200)
[ "$magic" != "2705" ] && {
echo "Invalid image type."
return 1
}
return 0
;;
alfa-ap96|\
alfa-nx|\
ap121|\
ap121-mini|\
ap135-020|\
ap136-010|\
ap136-020|\
ap147-010|\
ap152|\
ap91-5g|\
ap96|\
bhr-4grv2|\
bxu2000n-2-a1|\
db120|\
dr344|\
dw33d|\
f9k1115v2|\
hornet-ub|\
mr12|\
mr16|\
zbt-we1526|\
zcn-1523h-2|\
zcn-1523h-5)
[ "$magic_long" != "68737173" -a "$magic_long" != "19852003" ] && {
echo "Invalid image type."
return 1
}
return 0
;;
all0258n|\
all0315n|\
cap324|\
cap4200ag|\
cr3000|\
cr5000)
platform_check_image_allnet "$1" && return 0
return 1
;;
all0305|\
eap300v2|\
eap7660d|\
ja76pf|\
ja76pf2|\
jwap003|\
ls-sr71|\
pb42|\
pb44|\
routerstation|\
routerstation-pro|\
wp543|\
wpe72)
[ "$magic" != "4349" ] && {
echo "Invalid image. Use *-sysupgrade.bin files on this board"
return 1
}
local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null)
local md5_chk=$(fwtool -q -t -i /dev/null "$1"; dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}"
if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then
return 0
else
echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)"
return 1
fi
return 0
;;
antminer-s1|\
antminer-s3|\
antrouter-r1|\
archer-c5|\
archer-c7|\
el-m150|\
el-mini|\
gl-inet|\
lan-turtle|\
mc-mac1200r|\
minibox-v1|\
minibox-v3.2|\
omy-g1|\
omy-x1|\
onion-omega|\
oolite-v1|\
oolite-v5.2|\
oolite-v5.2-dev|\
packet-squirrel|\
re355|\
re450|\
rut900|\
smart-300|\
som9331|\
tellstick-znet-lite|\
tl-mr10u|\
tl-mr11u|\
tl-mr12u|\
tl-mr13u|\
tl-mr3020|\
tl-mr3040|\
tl-mr3040-v2|\
tl-mr3220|\
tl-mr3220-v2|\
tl-mr3420|\
tl-mr3420-v2|\
tl-mr6400|\
tl-wa701nd-v2|\
tl-wa7210n-v2|\
tl-wa750re|\
tl-wa7510n|\
tl-wa801nd-v2|\
tl-wa801nd-v3|\
tl-wa830re-v2|\
tl-wa850re|\
tl-wa850re-v2|\
tl-wa855re-v1|\
tl-wa860re|\
tl-wa901nd|\
tl-wa901nd-v2|\
tl-wa901nd-v3|\
tl-wa901nd-v4|\
tl-wa901nd-v5|\
tl-wdr3320-v2|\
tl-wdr3500|\
tl-wdr4300|\
tl-wdr4900-v2|\
tl-wdr6500-v2|\
tl-wpa8630|\
tl-wr1041n-v2|\
tl-wr1043nd|\
tl-wr1043nd-v2|\
tl-wr1043nd-v4|\
tl-wr2543n|\
tl-wr703n|\
tl-wr710n|\
tl-wr720n-v3|\
tl-wr740n-v6|\
tl-wr741nd|\
tl-wr741nd-v4|\
tl-wr802n-v1|\
tl-wr802n-v2|\
tl-wr810n|\
tl-wr810n-v2|\
tl-wr840n-v2|\
tl-wr840n-v3|\
tl-wr841n-v1|\
tl-wr841n-v7|\
tl-wr841n-v8|\
tl-wr841n-v9|\
tl-wr841n-v11|\
tl-wr842n-v2|\
tl-wr842n-v3|\
tl-wr902ac-v1|\
tl-wr940n-v4|\
tl-wr940n-v6|\
tl-wr941nd|\
tl-wr941nd-v5|\
tl-wr941nd-v6|\
ts-d084|\
wifi-pineapple-nano)
local magic_ver="0100"
case "$board" in
tl-wdr3320-v2|tl-wdr6500-v2)
magic_ver="0200"
;;
esac
[ "$magic" != "$magic_ver" ] && {
echo "Invalid image type."
return 1
}
local hwid
local mid
local imagehwid
local imagemid
hwid=$(tplink_get_hwid)
mid=$(tplink_get_mid)
imagehwid=$(tplink_get_image_hwid "$1")
imagemid=$(tplink_get_image_mid "$1")
[ "$hwid" != "$imagehwid" -o "$mid" != "$imagemid" ] && {
echo "Invalid image, hardware ID mismatch, hw:$hwid $mid image:$imagehwid $imagemid."
return 1
}
local boot_size
boot_size=$(tplink_get_image_boot_size "$1")
[ "$boot_size" != "00000000" ] && {
echo "Invalid image, it contains a bootloader."
return 1
}
return 0
;;
bsb|\
dir-825-b1|\
tew-673gru)
dir825b_check_image "$1" && return 0
;;
rb-411|\
rb-411u|\
rb-433|\
rb-433u|\
rb-435g|\
rb-450|\
rb-450g|\
rb-493|\
rb-493g|\
rb-750|\
rb-750gl|\
rb-751|\
rb-751g|\
rb-911g-2hpnd|\
rb-911g-5hpnd|\
rb-911g-5hpacd|\
rb-912uag-2hpnd|\
rb-912uag-5hpnd|\
rb-921gs-5hpacd-r2|\
rb-922uags-5hpacd|\
rb-951g-2hnd|\
rb-951ui-2hnd|\
rb-2011l|\
rb-2011il|\
rb-2011ils|\
rb-2011uas|\
rb-2011uas-2hnd|\
rb-2011uias|\
rb-2011uias-2hnd|\
rb-2011uias-2hnd-r2|\
rb-sxt2n|\
rb-sxt5n)
nand_do_platform_check routerboard $1
return $?
;;
c-60|\
hiveap-121|\
nbg6716|\
r6100|\
rambutan|\
wi2a-ac200i|\
wndr3700v4|\
wndr4300)
nand_do_platform_check $board $1
return $?
;;
cpe210|\
cpe510|\
eap120|\
wbs210|\
wbs510)
tplink_pharos_check_image "$1" "7f454c46" "$(tplink_pharos_get_model_string)" '' && return 0
return 1
;;
cpe210-v2|\
cpe210-v3)
tplink_pharos_check_image "$1" "01000000" "$(tplink_pharos_v2_get_model_string)" '\0\xff\r' && return 0
return 1
;;
cpe510-v2)
tplink_pharos_check_image "$1" "7f454c46" "$(tplink_pharos_v2_get_model_string)" '\0\xff\r' && return 0
return 1
;;
a40|\
a60|\
mr1750|\
mr1750v2|\
mr600|\
mr600v2|\
mr900|\
mr900v2|\
om2p|\
om2p-hs|\
om2p-hsv2|\
om2p-hsv3|\
om2p-hsv4|\
om2p-lc|\
om2pv2|\
om2pv4|\
om5p|\
om5p-ac|\
om5p-acv2|\
om5p-an)
platform_check_image_openmesh "$magic_long" "$1" && return 0
return 1
;;
mr18|\
z1)
merakinand_do_platform_check $board $1
return $?
;;
dir-869-a1|\
mynet-n600|\
mynet-n750|\
qihoo-c301)
[ "$magic_long" != "5ea3a417" ] && {
echo "Invalid image, bad magic: $magic_long"
return 1
}
local typemagic=$(seama_get_type_magic "$1")
[ "$typemagic" != "6669726d" ] && {
echo "Invalid image, bad type: $typemagic"
return 1
}
return 0
;;
e2100l|\
mynet-rext|\
wrt160nl)
cybertan_check_image "$1" && return 0
return 1
;;
nbg6616|\
uap-pro|\
unifi-outdoor-plus)
[ "$magic_long" != "19852003" ] && {
echo "Invalid image type."
return 1
}
return 0
;;
tube2h)
alfa_check_image "$1" && return 0
return 1
;;
wndr3700|\
wnr1000-v2|\
wnr2000-v3|\
wnr612-v2|\
wpn824n)
local hw_magic
hw_magic="$(ar71xx_get_mtd_part_magic firmware)"
[ "$magic_long" != "$hw_magic" ] && {
echo "Invalid image, hardware ID mismatch, hw:$hw_magic image:$magic_long."
return 1
}
return 0
;;
wnr2000-v4)
[ "$magic_long" != "32303034" ] && {
echo "Invalid image type."
return 1
}
return 0
;;
wnr2200)
[ "$magic_long" != "32323030" ] && {
echo "Invalid image type."
return 1
}
return 0
;;
dap-2695-a1)
local magic=$(wrgg_get_image_magic "$1")
[ "$magic" != "21030820" ] && {
echo "Invalid image, bad type: $magic"
return 1
}
return 0;
;;
# these boards use metadata images
fritz300e|\
fritz4020|\
fritz450e|\
koala|\
rb-750-r2|\
rb-750p-pbr2|\
rb-750up-r2|\
rb-911-2hn|\
rb-911-5hn|\
rb-931-2nd|\
rb-941-2nd|\
rb-951ui-2nd|\
rb-952ui-5ac2nd|\
rb-962uigs-5hact2hnt|\
rb-lhg-5nd|\
rb-map-2nd|\
rb-mapl-2nd|\
rb-sxt-2nd-r3|\
rb-wap-2nd|\
rb-wapg-5hact2hnd|\
rb-wapr-2nd)
return 0
;;
esac
echo "Sysupgrade is not yet supported on $board."
return 1
}
platform_do_upgrade_mikrotik_rb() {
CI_KERNPART=none
local fw_mtd=$(find_mtd_part kernel)
fw_mtd="${fw_mtd/block/}"
[ -n "$fw_mtd" ] || return
local board_dir=$(tar tf "$1" | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
[ -n "$board_dir" ] || return
mtd erase kernel
tar xf "$1" ${board_dir}/kernel -O | nandwrite -o "$fw_mtd" -
nand_do_upgrade "$1"
}
platform_do_upgrade_nokia() {
case "$(fw_printenv -n dualPartition)" in
imgA)
fw_setenv dualPartition imgB
fw_setenv ActImg NokiaImageB
;;
imgB)
fw_setenv dualPartition imgA
fw_setenv ActImg NokiaImageA
;;
esac
ubiblock -r /dev/ubiblock0_0 2>/dev/null >/dev/null
rm -f /dev/ubiblock0_0
ubidetach -d 0 2>/dev/null >/dev/null
CI_UBIPART=ubi_alt
CI_KERNPART=kernel_alt
nand_do_upgrade "$1"
}
platform_do_upgrade() {
local board=$(board_name)
case "$board" in
rb-750-r2|\
rb-750p-pbr2|\
rb-750up-r2|\
rb-911-2hn|\
rb-911-5hn|\
rb-931-2nd|\
rb-941-2nd|\
rb-951ui-2nd|\
rb-952ui-5ac2nd|\
rb-962uigs-5hact2hnt|\
rb-lhg-5nd|\
rb-map-2nd|\
rb-mapl-2nd|\
rb-sxt-2nd-r3|\
rb-wap-2nd|\
rb-wapg-5hact2hnd|\
rb-wapr-2nd)
# erase firmware if booted from initramfs
[ -z "$(rootfs_type)" ] && mtd erase firmware
;;
esac
case "$board" in
all0258n)
platform_do_upgrade_allnet "0x9f050000" "$1"
;;
all0305|\
eap7660d|\
ja76pf|\
ja76pf2|\
jwap003|\
ls-sr71|\
pb42|\
pb44|\
routerstation|\
routerstation-pro)
platform_do_upgrade_combined "$1"
;;
all0315n)
platform_do_upgrade_allnet "0x9f080000" "$1"
;;
cap4200ag|\
eap300v2|\
ens202ext)
platform_do_upgrade_allnet "0xbf0a0000" "$1"
;;
dir-825-b1|\
tew-673gru)
platform_do_upgrade_dir825b "$1"
;;
a40|\
a60|\
mr1750|\
mr1750v2|\
mr600|\
mr600v2|\
mr900|\
mr900v2|\
om2p|\
om2p-hs|\
om2p-hsv2|\
om2p-hsv3|\
om2p-hsv4|\
om2p-lc|\
om2pv2|\
om2pv4|\
om5p|\
om5p-ac|\
om5p-acv2|\
om5p-an)
platform_do_upgrade_openmesh "$1"
;;
c-60|\
hiveap-121|\
nbg6716|\
r6100|\
rambutan|\
wndr3700v4|\
wndr4300)
nand_do_upgrade "$1"
;;
mr18|\
z1)
merakinand_do_upgrade "$1"
;;
rb-411|\
rb-411u|\
rb-433|\
rb-433u|\
rb-435g|\
rb-450|\
rb-450g|\
rb-493|\
rb-493g|\
rb-750|\
rb-750gl|\
rb-751|\
rb-751g|\
rb-911g-2hpnd|\
rb-911g-5hpacd|\
rb-911g-5hpnd|\
rb-912uag-2hpnd|\
rb-912uag-5hpnd|\
rb-921gs-5hpacd-r2|\
rb-922uags-5hpacd|\
rb-951g-2hnd|\
rb-951ui-2hnd|\
rb-2011il|\
rb-2011ils|\
rb-2011l|\
rb-2011uas|\
rb-2011uas-2hnd|\
rb-2011uias|\
rb-2011uias-2hnd|\
rb-2011uias-2hnd-r2|\
rb-sxt2n|\
rb-sxt5n)
platform_do_upgrade_mikrotik_rb "$1"
;;
uap-pro|\
unifi-outdoor-plus)
MTD_CONFIG_ARGS="-s 0x180000"
default_do_upgrade "$1"
;;
wi2a-ac200i)
platform_do_upgrade_nokia "$1"
;;
wp543|\
wpe72)
platform_do_upgrade_compex "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}

485
target/linux/ar71xx/config-4.14
View File

@ -1,485 +0,0 @@
CONFIG_AG71XX=y
CONFIG_AG71XX_AR8216_SUPPORT=y
# CONFIG_AG71XX_DEBUG is not set
# CONFIG_AG71XX_DEBUG_FS is not set
CONFIG_AR8216_PHY=y
CONFIG_AR8216_PHY_LEDS=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
# CONFIG_ARCH_HAS_SG_CHAIN is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_AT803X_PHY=y
CONFIG_ATH79=y
# CONFIG_ATH79_DEV_AP9X_PCI is not set
# CONFIG_ATH79_DEV_DSA is not set
# CONFIG_ATH79_DEV_ETH is not set
# CONFIG_ATH79_DEV_GPIO_BUTTONS is not set
# CONFIG_ATH79_DEV_LEDS_GPIO is not set
# CONFIG_ATH79_DEV_M25P80 is not set
# CONFIG_ATH79_DEV_SPI is not set
# CONFIG_ATH79_DEV_USB is not set
# CONFIG_ATH79_MACH_A60 is not set
# CONFIG_ATH79_MACH_ALFA_AP120C is not set
# CONFIG_ATH79_MACH_ALFA_AP96 is not set
# CONFIG_ATH79_MACH_ALFA_NX is not set
# CONFIG_ATH79_MACH_ALL0258N is not set
# CONFIG_ATH79_MACH_ALL0315N is not set
# CONFIG_ATH79_MACH_ANTMINER_S1 is not set
# CONFIG_ATH79_MACH_ANTMINER_S3 is not set
# CONFIG_ATH79_MACH_ANTROUTER_R1 is not set
# CONFIG_ATH79_MACH_AP121 is not set
# CONFIG_ATH79_MACH_AP121F is not set
# CONFIG_ATH79_MACH_AP132 is not set
# CONFIG_ATH79_MACH_AP136 is not set
# CONFIG_ATH79_MACH_AP143 is not set
# CONFIG_ATH79_MACH_AP147 is not set
# CONFIG_ATH79_MACH_AP152 is not set
# CONFIG_ATH79_MACH_AP531B0 is not set
# CONFIG_ATH79_MACH_AP81 is not set
# CONFIG_ATH79_MACH_AP90Q is not set
# CONFIG_ATH79_MACH_AP91_5G is not set
# CONFIG_ATH79_MACH_AP96 is not set
# CONFIG_ATH79_MACH_ARCHER_C25_V1 is not set
# CONFIG_ATH79_MACH_ARCHER_C58_V1 is not set
# CONFIG_ATH79_MACH_ARCHER_C59_V1 is not set
# CONFIG_ATH79_MACH_ARCHER_C59_V2 is not set
# CONFIG_ATH79_MACH_ARCHER_C60_V1 is not set
# CONFIG_ATH79_MACH_ARCHER_C60_V2 is not set
# CONFIG_ATH79_MACH_ARCHER_C7 is not set
# CONFIG_ATH79_MACH_ARDUINO_YUN is not set
# CONFIG_ATH79_MACH_AW_NR580 is not set
# CONFIG_ATH79_MACH_BHR_4GRV2 is not set
# CONFIG_ATH79_MACH_BHU_BXU2000N2_A is not set
# CONFIG_ATH79_MACH_BSB is not set
# CONFIG_ATH79_MACH_C55 is not set
# CONFIG_ATH79_MACH_C60 is not set
# CONFIG_ATH79_MACH_CAP324 is not set
# CONFIG_ATH79_MACH_CAP4200AG is not set
# CONFIG_ATH79_MACH_CARAMBOLA2 is not set
# CONFIG_ATH79_MACH_CF_E316N_V2 is not set
# CONFIG_ATH79_MACH_CF_E320N_V2 is not set
# CONFIG_ATH79_MACH_CF_E355AC is not set
# CONFIG_ATH79_MACH_CF_E375AC is not set
# CONFIG_ATH79_MACH_CF_E380AC_V1 is not set
# CONFIG_ATH79_MACH_CF_E380AC_V2 is not set
# CONFIG_ATH79_MACH_CF_E520N is not set
# CONFIG_ATH79_MACH_CF_E530N is not set
# CONFIG_ATH79_MACH_CPE505N is not set
# CONFIG_ATH79_MACH_CPE510 is not set
# CONFIG_ATH79_MACH_CPE830 is not set
# CONFIG_ATH79_MACH_CPE870 is not set
# CONFIG_ATH79_MACH_CR3000 is not set
# CONFIG_ATH79_MACH_CR5000 is not set
# CONFIG_ATH79_MACH_DAP_1330_A1 is not set
# CONFIG_ATH79_MACH_DAP_2695_A1 is not set
# CONFIG_ATH79_MACH_DB120 is not set
# CONFIG_ATH79_MACH_DGL_5500_A1 is not set
# CONFIG_ATH79_MACH_DHP_1565_A1 is not set
# CONFIG_ATH79_MACH_DIR_505_A1 is not set
# CONFIG_ATH79_MACH_DIR_600_A1 is not set
# CONFIG_ATH79_MACH_DIR_615_C1 is not set
# CONFIG_ATH79_MACH_DIR_615_I1 is not set
# CONFIG_ATH79_MACH_DIR_825_B1 is not set
# CONFIG_ATH79_MACH_DIR_825_C1 is not set
# CONFIG_ATH79_MACH_DIR_869_A1 is not set
# CONFIG_ATH79_MACH_DLAN_HOTSPOT is not set
# CONFIG_ATH79_MACH_DLAN_PRO_1200_AC is not set
# CONFIG_ATH79_MACH_DLAN_PRO_500_WP is not set
# CONFIG_ATH79_MACH_DOMYWIFI_DW33D is not set
# CONFIG_ATH79_MACH_DR342 is not set
# CONFIG_ATH79_MACH_DR344 is not set
# CONFIG_ATH79_MACH_DR531 is not set
# CONFIG_ATH79_MACH_DRAGINO2 is not set
# CONFIG_ATH79_MACH_E1700AC_V2 is not set
# CONFIG_ATH79_MACH_E2100L is not set
# CONFIG_ATH79_MACH_E558_V2 is not set
# CONFIG_ATH79_MACH_E600G_V2 is not set
# CONFIG_ATH79_MACH_E750A_V4 is not set
# CONFIG_ATH79_MACH_E750G_V8 is not set
# CONFIG_ATH79_MACH_EAP120 is not set
# CONFIG_ATH79_MACH_EAP300V2 is not set
# CONFIG_ATH79_MACH_EAP7660D is not set
# CONFIG_ATH79_MACH_EL_M150 is not set
# CONFIG_ATH79_MACH_EL_MINI is not set
# CONFIG_ATH79_MACH_ENS202EXT is not set
# CONFIG_ATH79_MACH_EPG5000 is not set
# CONFIG_ATH79_MACH_ESR1750 is not set
# CONFIG_ATH79_MACH_ESR900 is not set
# CONFIG_ATH79_MACH_EW_BALIN is not set
# CONFIG_ATH79_MACH_EW_DORIN is not set
# CONFIG_ATH79_MACH_F9K1115V2 is not set
# CONFIG_ATH79_MACH_FRITZ300E is not set
# CONFIG_ATH79_MACH_FRITZ4020 is not set
# CONFIG_ATH79_MACH_FRITZ450E is not set
# CONFIG_ATH79_MACH_GL_AR150 is not set
# CONFIG_ATH79_MACH_GL_AR300 is not set
# CONFIG_ATH79_MACH_GL_AR300M is not set
# CONFIG_ATH79_MACH_GL_AR750 is not set
# CONFIG_ATH79_MACH_GL_AR750S is not set
# CONFIG_ATH79_MACH_GL_DOMINO is not set
# CONFIG_ATH79_MACH_GL_INET is not set
# CONFIG_ATH79_MACH_GL_MIFI is not set
# CONFIG_ATH79_MACH_GL_USB150 is not set
# CONFIG_ATH79_MACH_GS_MINIBOX_V32 is not set
# CONFIG_ATH79_MACH_GS_OOLITE_V1 is not set
# CONFIG_ATH79_MACH_GS_OOLITE_V5_2 is not set
# CONFIG_ATH79_MACH_HIVEAP_121 is not set
# CONFIG_ATH79_MACH_HIWIFI_HC6361 is not set
# CONFIG_ATH79_MACH_HORNET_UB is not set
# CONFIG_ATH79_MACH_JA76PF is not set
# CONFIG_ATH79_MACH_JWAP003 is not set
# CONFIG_ATH79_MACH_JWAP230 is not set
# CONFIG_ATH79_MACH_KOALA is not set
# CONFIG_ATH79_MACH_LAN_TURTLE is not set
# CONFIG_ATH79_MACH_LIMA is not set
# CONFIG_ATH79_MACH_MC_MAC1200R is not set
# CONFIG_ATH79_MACH_MR12 is not set
# CONFIG_ATH79_MACH_MR16 is not set
# CONFIG_ATH79_MACH_MR1750 is not set
# CONFIG_ATH79_MACH_MR18 is not set
# CONFIG_ATH79_MACH_MR600 is not set
# CONFIG_ATH79_MACH_MR900 is not set
# CONFIG_ATH79_MACH_MYNET_N600 is not set
# CONFIG_ATH79_MACH_MYNET_N750 is not set
# CONFIG_ATH79_MACH_MYNET_REXT is not set
# CONFIG_ATH79_MACH_MZK_W04NU is not set
# CONFIG_ATH79_MACH_MZK_W300NH is not set
# CONFIG_ATH79_MACH_N5Q is not set
# CONFIG_ATH79_MACH_NBG460N is not set
# CONFIG_ATH79_MACH_NBG6716 is not set
# CONFIG_ATH79_MACH_OM2P is not set
# CONFIG_ATH79_MACH_OM5P is not set
# CONFIG_ATH79_MACH_OM5P_AC is not set
# CONFIG_ATH79_MACH_OM5P_ACv2 is not set
# CONFIG_ATH79_MACH_OMY_G1 is not set
# CONFIG_ATH79_MACH_OMY_X1 is not set
# CONFIG_ATH79_MACH_ONION_OMEGA is not set
# CONFIG_ATH79_MACH_PB42 is not set
# CONFIG_ATH79_MACH_PB44 is not set
# CONFIG_ATH79_MACH_PQI_AIR_PEN is not set
# CONFIG_ATH79_MACH_QIHOO_C301 is not set
# CONFIG_ATH79_MACH_R36A is not set
# CONFIG_ATH79_MACH_R602N is not set
# CONFIG_ATH79_MACH_R6100 is not set
# CONFIG_ATH79_MACH_RAMBUTAN is not set
# CONFIG_ATH79_MACH_RB2011 is not set
# CONFIG_ATH79_MACH_RB4XX is not set
# CONFIG_ATH79_MACH_RB750 is not set
# CONFIG_ATH79_MACH_RB91X is not set
# CONFIG_ATH79_MACH_RB922 is not set
# CONFIG_ATH79_MACH_RB95X is not set
# CONFIG_ATH79_MACH_RBSPI is not set
# CONFIG_ATH79_MACH_RBSXTLITE is not set
# CONFIG_ATH79_MACH_RE355 is not set
# CONFIG_ATH79_MACH_RE450 is not set
# CONFIG_ATH79_MACH_RME_EG200 is not set
# CONFIG_ATH79_MACH_RUT9XX is not set
# CONFIG_ATH79_MACH_RW2458N is not set
# CONFIG_ATH79_MACH_SC1750 is not set
# CONFIG_ATH79_MACH_SC300M is not set
# CONFIG_ATH79_MACH_SC450 is not set
# CONFIG_ATH79_MACH_SMART_300 is not set
# CONFIG_ATH79_MACH_SOM9331 is not set
# CONFIG_ATH79_MACH_SR3200 is not set
# CONFIG_ATH79_MACH_T830 is not set
# CONFIG_ATH79_MACH_TELLSTICK_ZNET_LITE is not set
# CONFIG_ATH79_MACH_TEW_632BRP is not set
# CONFIG_ATH79_MACH_TEW_673GRU is not set
# CONFIG_ATH79_MACH_TEW_712BR is not set
# CONFIG_ATH79_MACH_TEW_732BR is not set
# CONFIG_ATH79_MACH_TEW_823DRU is not set
# CONFIG_ATH79_MACH_TL_MR11U is not set
# CONFIG_ATH79_MACH_TL_MR13U is not set
# CONFIG_ATH79_MACH_TL_MR3020 is not set
# CONFIG_ATH79_MACH_TL_MR3X20 is not set
# CONFIG_ATH79_MACH_TL_MR6400 is not set
# CONFIG_ATH79_MACH_TL_WA701ND_V2 is not set
# CONFIG_ATH79_MACH_TL_WA7210N_V2 is not set
# CONFIG_ATH79_MACH_TL_WA801ND_V3 is not set
# CONFIG_ATH79_MACH_TL_WA830RE_V2 is not set
# CONFIG_ATH79_MACH_TL_WA850RE_V2 is not set
# CONFIG_ATH79_MACH_TL_WA855RE_V1 is not set
# CONFIG_ATH79_MACH_TL_WA901ND is not set
# CONFIG_ATH79_MACH_TL_WA901ND_V2 is not set
# CONFIG_ATH79_MACH_TL_WA901ND_V4 is not set
# CONFIG_ATH79_MACH_TL_WAX50RE is not set
# CONFIG_ATH79_MACH_TL_WDR3320_V2 is not set
# CONFIG_ATH79_MACH_TL_WDR3500 is not set
# CONFIG_ATH79_MACH_TL_WDR4300 is not set
# CONFIG_ATH79_MACH_TL_WDR6500_V2 is not set
# CONFIG_ATH79_MACH_TL_WPA8630 is not set
# CONFIG_ATH79_MACH_TL_WR1041N_V2 is not set
# CONFIG_ATH79_MACH_TL_WR1043ND is not set
# CONFIG_ATH79_MACH_TL_WR1043ND_V2 is not set
# CONFIG_ATH79_MACH_TL_WR1043ND_V4 is not set
# CONFIG_ATH79_MACH_TL_WR1043N_V5 is not set
# CONFIG_ATH79_MACH_TL_WR2543N is not set
# CONFIG_ATH79_MACH_TL_WR703N is not set
# CONFIG_ATH79_MACH_TL_WR720N_V3 is not set
# CONFIG_ATH79_MACH_TL_WR741ND is not set
# CONFIG_ATH79_MACH_TL_WR741ND_V4 is not set
# CONFIG_ATH79_MACH_TL_WR802N_V1 is not set
# CONFIG_ATH79_MACH_TL_WR802N_V2 is not set
# CONFIG_ATH79_MACH_TL_WR810N is not set
# CONFIG_ATH79_MACH_TL_WR810N_V2 is not set
# CONFIG_ATH79_MACH_TL_WR840N_V2 is not set
# CONFIG_ATH79_MACH_TL_WR841N_V1 is not set
# CONFIG_ATH79_MACH_TL_WR841N_V8 is not set
# CONFIG_ATH79_MACH_TL_WR841N_V9 is not set
# CONFIG_ATH79_MACH_TL_WR902AC_V1 is not set
# CONFIG_ATH79_MACH_TL_WR940N_V4 is not set
# CONFIG_ATH79_MACH_TL_WR941ND is not set
# CONFIG_ATH79_MACH_TL_WR941ND_V6 is not set
# CONFIG_ATH79_MACH_TL_WR942N_V1 is not set
# CONFIG_ATH79_MACH_TS_D084 is not set
# CONFIG_ATH79_MACH_TUBE2H is not set
# CONFIG_ATH79_MACH_UBNT is not set
# CONFIG_ATH79_MACH_UBNT_UNIFIAC is not set
# CONFIG_ATH79_MACH_UBNT_XM is not set
# CONFIG_ATH79_MACH_WAM250 is not set
# CONFIG_ATH79_MACH_WEIO is not set
# CONFIG_ATH79_MACH_WHR_HP_G300N is not set
# CONFIG_ATH79_MACH_WI2A_AC200I is not set
# CONFIG_ATH79_MACH_WIFI_PINEAPPLE_NANO is not set
# CONFIG_ATH79_MACH_WLAE_AG300N is not set
# CONFIG_ATH79_MACH_WLR8100 is not set
# CONFIG_ATH79_MACH_WNDAP360 is not set
# CONFIG_ATH79_MACH_WNDR3700 is not set
# CONFIG_ATH79_MACH_WNDR4300 is not set
# CONFIG_ATH79_MACH_WNR2000 is not set
# CONFIG_ATH79_MACH_WNR2000_V3 is not set
# CONFIG_ATH79_MACH_WNR2000_V4 is not set
# CONFIG_ATH79_MACH_WNR2200 is not set
# CONFIG_ATH79_MACH_WP543 is not set
# CONFIG_ATH79_MACH_WPE72 is not set
# CONFIG_ATH79_MACH_WPJ342 is not set
# CONFIG_ATH79_MACH_WPJ344 is not set
# CONFIG_ATH79_MACH_WPJ531 is not set
# CONFIG_ATH79_MACH_WPJ558 is not set
# CONFIG_ATH79_MACH_WPJ563 is not set
# CONFIG_ATH79_MACH_WRT160NL is not set
# CONFIG_ATH79_MACH_WRT400N is not set
# CONFIG_ATH79_MACH_WRTNODE2Q is not set
# CONFIG_ATH79_MACH_WZR_450HP2 is not set
# CONFIG_ATH79_MACH_WZR_HP_AG300H is not set
# CONFIG_ATH79_MACH_WZR_HP_G300NH is not set
# CONFIG_ATH79_MACH_WZR_HP_G300NH2 is not set
# CONFIG_ATH79_MACH_WZR_HP_G450H is not set
# CONFIG_ATH79_MACH_XD3200 is not set
# CONFIG_ATH79_MACH_Z1 is not set
# CONFIG_ATH79_MACH_ZBT_WE1526 is not set
# CONFIG_ATH79_MACH_ZCN_1523H is not set
# CONFIG_ATH79_NVRAM is not set
# CONFIG_ATH79_PCI_ATH9K_FIXUP is not set
# CONFIG_ATH79_ROUTERBOOT is not set
CONFIG_ATH79_WDT=y
CONFIG_CEVT_R4K=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
# CONFIG_COMMON_CLK_BOSTON is not set
CONFIG_COMMON_CLK=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_RIXI=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_FIXED_PHY=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_ATH79=y
CONFIG_GPIO_GENERIC=y
# CONFIG_GPIO_LATCH is not set
CONFIG_GPIO_NXP_74HC153=y
CONFIG_GPIO_PCF857X=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_CBPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HZ_PERIODIC=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_GPIO=y
CONFIG_IMAGE_CMDLINE_HACK=y
CONFIG_INITRAMFS_ROOT_GID=0
CONFIG_INITRAMFS_ROOT_UID=0
CONFIG_INITRAMFS_SOURCE="../../root"
CONFIG_INTEL_XWAY_PHY=y
CONFIG_IP17XX_PHY=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
CONFIG_LEDS_GPIO=y
CONFIG_MARVELL_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MDIO_GPIO=y
CONFIG_MICREL_PHY=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
CONFIG_MIPS_CLOCK_VSYSCALL=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
CONFIG_MIPS_SPRAM=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CYBERTAN_PARTS=y
CONFIG_MTD_M25P80=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
CONFIG_MTD_MYLOADER_PARTS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_EVA_FW=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_LZMA_FW=y
CONFIG_MTD_SPLIT_MINOR_FW=y
CONFIG_MTD_SPLIT_SEAMA_FW=y
CONFIG_MTD_SPLIT_TPLINK_FW=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_TPLINK_PARTS=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MV88E6060=y
CONFIG_NET_DSA_MV88E6063=y
CONFIG_NET_DSA_TAG_TRAILER=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
# CONFIG_NO_IOPORT_MAP is not set
# CONFIG_OF is not set
# CONFIG_PCI_AR724X is not set
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_RATIONAL=y
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_RTL8306_PHY=y
CONFIG_RTL8366RB_PHY=y
CONFIG_RTL8366S_PHY=y
CONFIG_RTL8366_SMI=y
CONFIG_RTL8367_PHY=y
# CONFIG_SCHED_INFO is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_FSL is not set
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
# CONFIG_SOC_AR71XX is not set
# CONFIG_SOC_AR724X is not set
# CONFIG_SOC_AR913X is not set
# CONFIG_SOC_AR933X is not set
# CONFIG_SOC_AR934X is not set
# CONFIG_SOC_QCA953X is not set
# CONFIG_SOC_QCA955X is not set
# CONFIG_SOC_QCA956X is not set
CONFIG_SPI=y
CONFIG_SPI_ATH79=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
# CONFIG_SPI_RB4XX is not set
# CONFIG_SPI_VSC7385 is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_ZBOOT=y
CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_USB_SUPPORT=y

2458
target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
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290
target/linux/ar71xx/files/arch/mips/ath79/Makefile
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@ -1,290 +0,0 @@
#
# Makefile for the Atheros AR71XX/AR724X/AR913X specific parts of the kernel
#
# Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
obj-y := prom.o setup.o irq.o common.o clock.o gpio.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_PCI) += pci.o
#
# Devices
#
obj-y += dev-common.o
obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o
obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o
obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o
obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o
obj-$(CONFIG_ATH79_DEV_NFC) += dev-nfc.o
obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
#
# Miscellaneous objects
#
obj-$(CONFIG_ATH79_NVRAM) += nvram.o
obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o
obj-$(CONFIG_ATH79_ROUTERBOOT) += routerboot.o
#
# Machines
#
obj-$(CONFIG_ATH79_MACH_A60) += mach-a60.o
obj-$(CONFIG_ATH79_MACH_WI2A_AC200I) += mach-wi2a-ac200i.o
obj-$(CONFIG_ATH79_MACH_ALFA_AP120C) += mach-alfa-ap120c.o
obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o
obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o
obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o
obj-$(CONFIG_ATH79_MACH_ALL0315N) += mach-all0315n.o
obj-$(CONFIG_ATH79_MACH_ANTMINER_S1) += mach-antminer-s1.o
obj-$(CONFIG_ATH79_MACH_ANTMINER_S3) += mach-antminer-s3.o
obj-$(CONFIG_ATH79_MACH_ANTROUTER_R1) += mach-antrouter-r1.o
obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
obj-$(CONFIG_ATH79_MACH_AP121F) += mach-ap121f.o
obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o
obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o
obj-$(CONFIG_ATH79_MACH_AP147) += mach-ap147.o
obj-$(CONFIG_ATH79_MACH_AP152) += mach-ap152.o
obj-$(CONFIG_ATH79_MACH_AP531B0) += mach-ap531b0.o
obj-$(CONFIG_ATH79_MACH_AP90Q) += mach-ap90q.o
obj-$(CONFIG_ATH79_MACH_AP91_5G) += mach-ap91-5g.o
obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C25_V1) += mach-archer-c25-v1.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C58_V1) += mach-archer-c59-v1.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C59_V1) += mach-archer-c59-v1.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C60_V1) += mach-archer-c60-v1.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C60_V2) += mach-archer-c60-v1.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7-v4.o
obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7-v5.o
obj-$(CONFIG_ATH79_MACH_ARDUINO_YUN) += mach-arduino-yun.o
obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o
obj-$(CONFIG_ATH79_MACH_BHR_4GRV2) += mach-bhr-4grv2.o
obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A) += mach-bhu-bxu2000n2-a.o
obj-$(CONFIG_ATH79_MACH_BSB) += mach-bsb.o
obj-$(CONFIG_ATH79_MACH_C55) += mach-c55.o
obj-$(CONFIG_ATH79_MACH_C60) += mach-c60.o
obj-$(CONFIG_ATH79_MACH_CAP324) += mach-cap324.o
obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o
obj-$(CONFIG_ATH79_MACH_CARAMBOLA2) += mach-carambola2.o
obj-$(CONFIG_ATH79_MACH_CF_E316N_V2) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E320N_V2) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E355AC) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E375AC) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E380AC_V1) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E380AC_V2) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E520N) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E530N) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CPE505N) += mach-r602n.o
obj-$(CONFIG_ATH79_MACH_CPE510) += mach-cpe510.o
obj-$(CONFIG_ATH79_MACH_CPE830) += mach-ap90q.o
obj-$(CONFIG_ATH79_MACH_CPE870) += mach-cpe870.o
obj-$(CONFIG_ATH79_MACH_CR3000) += mach-cr3000.o
obj-$(CONFIG_ATH79_MACH_CR5000) += mach-cr5000.o
obj-$(CONFIG_ATH79_MACH_DAP_1330_A1) += mach-dap-1330-a1.o
obj-$(CONFIG_ATH79_MACH_DAP_2695_A1) += mach-dap-2695-a1.o
obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
obj-$(CONFIG_ATH79_MACH_DGL_5500_A1) += mach-dgl-5500-a1.o
obj-$(CONFIG_ATH79_MACH_DHP_1565_A1) += mach-dhp-1565-a1.o
obj-$(CONFIG_ATH79_MACH_DIR_505_A1) += mach-dir-505-a1.o
obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o
obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o
obj-$(CONFIG_ATH79_MACH_DIR_615_I1) += mach-dir-615-i1.o
obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o
obj-$(CONFIG_ATH79_MACH_DIR_825_C1) += mach-dir-825-c1.o
obj-$(CONFIG_ATH79_MACH_DIR_869_A1) += mach-dir-869-a1.o
obj-$(CONFIG_ATH79_MACH_DLAN_HOTSPOT) += mach-dlan-hotspot.o
obj-$(CONFIG_ATH79_MACH_DLAN_PRO_1200_AC) += mach-dlan-pro-1200-ac.o
obj-$(CONFIG_ATH79_MACH_DLAN_PRO_500_WP) += mach-dlan-pro-500-wp.o
obj-$(CONFIG_ATH79_MACH_DOMYWIFI_DW33D) += mach-domywifi-dw33d.o
obj-$(CONFIG_ATH79_MACH_DR342) += mach-dr344.o
obj-$(CONFIG_ATH79_MACH_DR344) += mach-dr344.o
obj-$(CONFIG_ATH79_MACH_DR531) += mach-dr531.o
obj-$(CONFIG_ATH79_MACH_DRAGINO2) += mach-dragino2.o
obj-$(CONFIG_ATH79_MACH_E1700AC_V2) += mach-e1700ac-v2.o
obj-$(CONFIG_ATH79_MACH_E558_V2) += mach-e558-v2.o
obj-$(CONFIG_ATH79_MACH_E600G_V2) += mach-e600g-v2.o
obj-$(CONFIG_ATH79_MACH_E750A_V4) += mach-e750a-v4.o
obj-$(CONFIG_ATH79_MACH_E750G_V8) += mach-e750g-v8.o
obj-$(CONFIG_ATH79_MACH_EAP120) += mach-eap120.o
obj-$(CONFIG_ATH79_MACH_EAP300V2) += mach-eap300v2.o
obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o
obj-$(CONFIG_ATH79_MACH_EL_M150) += mach-el-m150.o
obj-$(CONFIG_ATH79_MACH_EL_MINI) += mach-el-mini.o
obj-$(CONFIG_ATH79_MACH_ENS202EXT) += mach-ens202ext.o
obj-$(CONFIG_ATH79_MACH_EPG5000) += mach-epg5000.o
obj-$(CONFIG_ATH79_MACH_ESR1750) += mach-esr1750.o
obj-$(CONFIG_ATH79_MACH_ESR900) += mach-esr900.o
obj-$(CONFIG_ATH79_MACH_EW_BALIN) += mach-ew-balin.o
obj-$(CONFIG_ATH79_MACH_EW_DORIN) += mach-ew-dorin.o
obj-$(CONFIG_ATH79_MACH_F9K1115V2) += mach-f9k1115v2.o
obj-$(CONFIG_ATH79_MACH_FRITZ300E) += mach-fritz300e.o
obj-$(CONFIG_ATH79_MACH_FRITZ4020) += mach-fritz4020.o
obj-$(CONFIG_ATH79_MACH_FRITZ450E) += mach-fritz450e.o
obj-$(CONFIG_ATH79_MACH_GL_AR150) += mach-gl-ar150.o
obj-$(CONFIG_ATH79_MACH_GL_AR300) += mach-gl-ar300.o
obj-$(CONFIG_ATH79_MACH_GL_AR300M) += mach-gl-ar300m.o
obj-$(CONFIG_ATH79_MACH_GL_AR750) += mach-gl-ar750.o
obj-$(CONFIG_ATH79_MACH_GL_AR750S) += mach-gl-ar750s.o
obj-$(CONFIG_ATH79_MACH_GL_DOMINO) += mach-gl-domino.o
obj-$(CONFIG_ATH79_MACH_GL_INET) += mach-gl-inet.o
obj-$(CONFIG_ATH79_MACH_GL_MIFI) += mach-gl-mifi.o
obj-$(CONFIG_ATH79_MACH_GL_USB150) += mach-gl-usb150.o
obj-$(CONFIG_ATH79_MACH_GS_MINIBOX_V32) += mach-gs-minibox-v32.o
obj-$(CONFIG_ATH79_MACH_GS_OOLITE_V1) += mach-gs-oolite-v1.o
obj-$(CONFIG_ATH79_MACH_GS_OOLITE_V5_2) += mach-gs-oolite-v5-2.o
obj-$(CONFIG_ATH79_MACH_HIVEAP_121) += mach-hiveap-121.o
obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361) += mach-hiwifi-hc6361.o
obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o
obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o
obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o
obj-$(CONFIG_ATH79_MACH_JWAP230) += mach-jwap230.o
obj-$(CONFIG_ATH79_MACH_KOALA) += mach-koala.o
obj-$(CONFIG_ATH79_MACH_LAN_TURTLE) += mach-lan-turtle.o
obj-$(CONFIG_ATH79_MACH_LIMA) += mach-lima.o
obj-$(CONFIG_ATH79_MACH_MC_MAC1200R) += mach-mc-mac1200r.o
obj-$(CONFIG_ATH79_MACH_MR12) += mach-mr12.o
obj-$(CONFIG_ATH79_MACH_MR16) += mach-mr16.o
obj-$(CONFIG_ATH79_MACH_MR1750) += mach-mr1750.o
obj-$(CONFIG_ATH79_MACH_MR18) += mach-mr18.o
obj-$(CONFIG_ATH79_MACH_MR600) += mach-mr600.o
obj-$(CONFIG_ATH79_MACH_MR900) += mach-mr900.o
obj-$(CONFIG_ATH79_MACH_MYNET_N600) += mach-mynet-n600.o
obj-$(CONFIG_ATH79_MACH_MYNET_N750) += mach-mynet-n750.o
obj-$(CONFIG_ATH79_MACH_MYNET_REXT) += mach-mynet-rext.o
obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o
obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o
obj-$(CONFIG_ATH79_MACH_N5Q) += mach-n5q.o
obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o
obj-$(CONFIG_ATH79_MACH_NBG6716) += mach-nbg6716.o
obj-$(CONFIG_ATH79_MACH_RAMBUTAN) += mach-rambutan.o
obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
obj-$(CONFIG_ATH79_MACH_OM5P) += mach-om5p.o
obj-$(CONFIG_ATH79_MACH_OM5P_AC) += mach-om5pac.o
obj-$(CONFIG_ATH79_MACH_OM5P_ACv2) += mach-om5pacv2.o
obj-$(CONFIG_ATH79_MACH_OMY_G1) += mach-omy-g1.o
obj-$(CONFIG_ATH79_MACH_OMY_X1) += mach-omy-x1.o
obj-$(CONFIG_ATH79_MACH_ONION_OMEGA) += mach-onion-omega.o
obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
obj-$(CONFIG_ATH79_MACH_PQI_AIR_PEN) += mach-pqi-air-pen.o
obj-$(CONFIG_ATH79_MACH_QIHOO_C301) += mach-qihoo-c301.o
obj-$(CONFIG_ATH79_MACH_R36A) += mach-r36a.o
obj-$(CONFIG_ATH79_MACH_R602N) += mach-r602n.o
obj-$(CONFIG_ATH79_MACH_R6100) += mach-r6100.o
obj-$(CONFIG_ATH79_MACH_RB2011) += mach-rb2011.o
obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o
obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o
obj-$(CONFIG_ATH79_MACH_RB91X) += mach-rb91x.o
obj-$(CONFIG_ATH79_MACH_RB922) += mach-rb922.o
obj-$(CONFIG_ATH79_MACH_RB941) += mach-rb941.o
obj-$(CONFIG_ATH79_MACH_RB95X) += mach-rb95x.o
obj-$(CONFIG_ATH79_MACH_RBSPI) += mach-rbspi.o
obj-$(CONFIG_ATH79_MACH_RBSXTLITE) += mach-rbsxtlite.o
obj-$(CONFIG_ATH79_MACH_RE355) += mach-re450.o
obj-$(CONFIG_ATH79_MACH_RE450) += mach-re450.o
obj-$(CONFIG_ATH79_MACH_RME_EG200) += mach-rme-eg200.o
obj-$(CONFIG_ATH79_MACH_RUT9XX) += mach-rut9xx.o
obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
obj-$(CONFIG_ATH79_MACH_SC1750) += mach-sc1750.o
obj-$(CONFIG_ATH79_MACH_SC300M) += mach-sc300m.o
obj-$(CONFIG_ATH79_MACH_SC450) += mach-sc450.o
obj-$(CONFIG_ATH79_MACH_SMART_300) += mach-smart-300.o
obj-$(CONFIG_ATH79_MACH_SOM9331) += mach-som9331.o
obj-$(CONFIG_ATH79_MACH_SR3200) += mach-sr3200.o
obj-$(CONFIG_ATH79_MACH_T830) += mach-t830.o
obj-$(CONFIG_ATH79_MACH_TELLSTICK_ZNET_LITE) += mach-tellstick-znet-lite.o
obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o
obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o
obj-$(CONFIG_ATH79_MACH_TEW_712BR) += mach-tew-712br.o
obj-$(CONFIG_ATH79_MACH_TEW_732BR) += mach-tew-732br.o
obj-$(CONFIG_ATH79_MACH_TEW_823DRU) += mach-tew-823dru.o
obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o
obj-$(CONFIG_ATH79_MACH_TL_MR13U) += mach-tl-mr13u.o
obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o
obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
obj-$(CONFIG_ATH79_MACH_TL_MR6400) += mach-tl-mr6400.o
obj-$(CONFIG_ATH79_MACH_TL_WA701ND_V2) += mach-tl-wa701nd-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WA7210N_V2) += mach-tl-wa7210n-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WA801ND_V3) += mach-tl-wa801nd-v3.o
obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2) += mach-tl-wa830re-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WA850RE_V2) += mach-tl-wax50re.o
obj-$(CONFIG_ATH79_MACH_TL_WA855RE_V1) += mach-tl-wax50re.o
obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o
obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V4) += mach-tl-wa901nd-v4.o
obj-$(CONFIG_ATH79_MACH_TL_WAX50RE) += mach-tl-wax50re.o
obj-$(CONFIG_ATH79_MACH_TL_WDR3320_V2) += mach-tl-wdr3320-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o
obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o
obj-$(CONFIG_ATH79_MACH_TL_WDR6500_V2) += mach-tl-wdr6500-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WPA8630) += mach-tl-wpa8630.o
obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2) += mach-tl-wr1041n-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o
obj-$(CONFIG_ATH79_MACH_TL_WR1043ND_V2) += mach-tl-wr1043nd-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WR1043ND_V4) += mach-tl-wr1043nd-v4.o
obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o
obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o
obj-$(CONFIG_ATH79_MACH_TL_WR720N_V3) += mach-tl-wr720n-v3.o
obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o
obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o
obj-$(CONFIG_ATH79_MACH_TL_WR802N_V1) += mach-tl-wr802n.o
obj-$(CONFIG_ATH79_MACH_TL_WR802N_V2) += mach-tl-wr802n.o
obj-$(CONFIG_ATH79_MACH_TL_WR810N) += mach-tl-wr810n.o
obj-$(CONFIG_ATH79_MACH_TL_WR810N_V2) += mach-tl-wr810n.o
obj-$(CONFIG_ATH79_MACH_TL_WR840N_V2) += mach-tl-wr841n-v9.o
obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o
obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o
obj-$(CONFIG_ATH79_MACH_TL_WR902AC_V1) += mach-tl-wr902ac-v1.o
obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
obj-$(CONFIG_ATH79_MACH_TL_WR941ND_V6) += mach-tl-wr941nd-v6.o
obj-$(CONFIG_ATH79_MACH_TL_WR940N_V4) += mach-tl-wr940n-v4.o
obj-$(CONFIG_ATH79_MACH_TL_WR942N_V1) += mach-tl-wr942n-v1.o
obj-$(CONFIG_ATH79_MACH_TS_D084) += mach-ts-d084.o
obj-$(CONFIG_ATH79_MACH_TUBE2H) += mach-tube2h.o
obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o
obj-$(CONFIG_ATH79_MACH_UBNT_UNIFIAC) += mach-ubnt-unifiac.o
obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
obj-$(CONFIG_ATH79_MACH_WAM250) += mach-wam250.o
obj-$(CONFIG_ATH79_MACH_WEIO) += mach-weio.o
obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
obj-$(CONFIG_ATH79_MACH_WIFI_PINEAPPLE_NANO) += mach-wifi-pineapple-nano.o
obj-$(CONFIG_ATH79_MACH_WLAE_AG300N) += mach-wlae-ag300n.o
obj-$(CONFIG_ATH79_MACH_WLR8100) += mach-wlr8100.o
obj-$(CONFIG_ATH79_MACH_WNDAP360) += mach-wndap360.o
obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o
obj-$(CONFIG_ATH79_MACH_WNDR4300) += mach-wndr4300.o
obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o
obj-$(CONFIG_ATH79_MACH_WNR2000_V3) += mach-wnr2000-v3.o
obj-$(CONFIG_ATH79_MACH_WNR2000_V4) += mach-wnr2000-v4.o
obj-$(CONFIG_ATH79_MACH_WNR2200) += mach-wnr2200.o
obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o
obj-$(CONFIG_ATH79_MACH_WPE72) += mach-wpe72.o
obj-$(CONFIG_ATH79_MACH_WPJ342) += mach-wpj342.o
obj-$(CONFIG_ATH79_MACH_WPJ344) += mach-wpj344.o
obj-$(CONFIG_ATH79_MACH_WPJ531) += mach-wpj531.o
obj-$(CONFIG_ATH79_MACH_WPJ558) += mach-wpj558.o
obj-$(CONFIG_ATH79_MACH_WPJ563) += mach-wpj563.o
obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o
obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o
obj-$(CONFIG_ATH79_MACH_WRTNODE2Q) += mach-wrtnode2q.o
obj-$(CONFIG_ATH79_MACH_WZR_450HP2) += mach-wzr-450hp2.o
obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o
obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o
obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o
obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
obj-$(CONFIG_ATH79_MACH_XD3200) += mach-sr3200.o
obj-$(CONFIG_ATH79_MACH_Z1) += mach-z1.o
obj-$(CONFIG_ATH79_MACH_ZBT_WE1526) += mach-zbt-we1526.o
obj-$(CONFIG_ATH79_MACH_ZCN_1523H) += mach-zcn-1523h.o

173
target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c
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@ -1,173 +0,0 @@
/*
* Atheros AP9X reference board PCI initialization
*
* Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/pci.h>
#include <linux/ath9k_platform.h>
#include <linux/delay.h>
#include <asm/mach-ath79/ath79.h>
#include "dev-ap9x-pci.h"
#include "pci-ath9k-fixup.h"
#include "pci.h"
static struct ath9k_platform_data ap9x_wmac0_data = {
.led_pin = -1,
};
static struct ath9k_platform_data ap9x_wmac1_data = {
.led_pin = -1,
};
static char ap9x_wmac0_mac[6];
static char ap9x_wmac1_mac[6];
__init void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin)
{
switch (wmac) {
case 0:
ap9x_wmac0_data.led_pin = pin;
break;
case 1:
ap9x_wmac1_data.led_pin = pin;
break;
}
}
__init struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac)
{
switch (wmac) {
case 0:
return &ap9x_wmac0_data;
case 1:
return &ap9x_wmac1_data;
}
return NULL;
}
__init void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val)
{
switch (wmac) {
case 0:
ap9x_wmac0_data.gpio_mask = mask;
ap9x_wmac0_data.gpio_val = val;
break;
case 1:
ap9x_wmac1_data.gpio_mask = mask;
ap9x_wmac1_data.gpio_val = val;
break;
}
}
__init void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds,
int num_leds)
{
switch (wmac) {
case 0:
ap9x_wmac0_data.leds = leds;
ap9x_wmac0_data.num_leds = num_leds;
break;
case 1:
ap9x_wmac1_data.leds = leds;
ap9x_wmac1_data.num_leds = num_leds;
break;
}
}
__init void ap9x_pci_setup_wmac_btns(unsigned wmac,
struct gpio_keys_button *btns,
unsigned num_btns, unsigned poll_interval)
{
struct ath9k_platform_data *ap9x_wmac_data;
if (!(ap9x_wmac_data = ap9x_pci_get_wmac_data(wmac)))
return;
ap9x_wmac_data->btns = btns;
ap9x_wmac_data->num_btns = num_btns;
ap9x_wmac_data->btn_poll_interval = poll_interval;
}
static int ap91_pci_plat_dev_init(struct pci_dev *dev)
{
switch (PCI_SLOT(dev->devfn)) {
case 0:
dev->dev.platform_data = &ap9x_wmac0_data;
break;
}
return 0;
}
__init void ap91_pci_init(u8 *cal_data, u8 *mac_addr)
{
if (cal_data)
memcpy(ap9x_wmac0_data.eeprom_data, cal_data,
sizeof(ap9x_wmac0_data.eeprom_data));
if (mac_addr) {
memcpy(ap9x_wmac0_mac, mac_addr, sizeof(ap9x_wmac0_mac));
ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
}
ath79_pci_set_plat_dev_init(ap91_pci_plat_dev_init);
ath79_register_pci();
pci_enable_ath9k_fixup(0, ap9x_wmac0_data.eeprom_data);
}
__init void ap91_pci_init_simple(void)
{
ap91_pci_init(NULL, NULL);
ap9x_wmac0_data.eeprom_name = "pci_wmac0.eeprom";
}
static int ap94_pci_plat_dev_init(struct pci_dev *dev)
{
switch (PCI_SLOT(dev->devfn)) {
case 17:
dev->dev.platform_data = &ap9x_wmac0_data;
break;
case 18:
dev->dev.platform_data = &ap9x_wmac1_data;
break;
}
return 0;
}
__init void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
u8 *cal_data1, u8 *mac_addr1)
{
if (cal_data0)
memcpy(ap9x_wmac0_data.eeprom_data, cal_data0,
sizeof(ap9x_wmac0_data.eeprom_data));
if (cal_data1)
memcpy(ap9x_wmac1_data.eeprom_data, cal_data1,
sizeof(ap9x_wmac1_data.eeprom_data));
if (mac_addr0) {
memcpy(ap9x_wmac0_mac, mac_addr0, sizeof(ap9x_wmac0_mac));
ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
}
if (mac_addr1) {
memcpy(ap9x_wmac1_mac, mac_addr1, sizeof(ap9x_wmac1_mac));
ap9x_wmac1_data.macaddr = ap9x_wmac1_mac;
}
ath79_pci_set_plat_dev_init(ap94_pci_plat_dev_init);
ath79_register_pci();
pci_enable_ath9k_fixup(17, ap9x_wmac0_data.eeprom_data);
pci_enable_ath9k_fixup(18, ap9x_wmac1_data.eeprom_data);
}

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target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h
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/*
* Atheros AP9X reference board PCI initialization
*
* Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _ATH79_DEV_AP9X_PCI_H
#define _ATH79_DEV_AP9X_PCI_H
struct gpio_led;
struct gpio_keys_button;
struct ath9k_platform_data;
#if defined(CONFIG_ATH79_DEV_AP9X_PCI)
void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin);
void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val);
void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds,
int num_leds);
void ap9x_pci_setup_wmac_btns(unsigned wmac, struct gpio_keys_button *btns,
unsigned num_btns, unsigned poll_interval);
struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac);
void ap91_pci_init(u8 *cal_data, u8 *mac_addr);
void ap91_pci_init_simple(void);
void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
u8 *cal_data1, u8 *mac_addr1);
#else
static inline void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) {}
static inline void ap9x_pci_setup_wmac_gpio(unsigned wmac,
u32 mask, u32 val) {}
static inline void ap9x_pci_setup_wmac_leds(unsigned wmac,
struct gpio_led *leds,
int num_leds) {}
static inline void ap9x_pci_setup_wmac_btns(unsigned wmac,
struct gpio_keys_button *btns,
unsigned num_btns,
unsigned poll_interval) {}
static inline struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac)
{
return NULL;
}
static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) {}
static inline void ap91_pci_init_simple(void) {}
static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
u8 *cal_data1, u8 *mac_addr1) {}
#endif
#endif /* _ATH79_DEV_AP9X_PCI_H */

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target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c
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/*
* Atheros AR71xx DSA switch device support
*
* Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/mach-ath79/ath79.h>
#include "dev-dsa.h"
static struct platform_device ar71xx_dsa_switch_device = {
.name = "dsa",
.id = 0,
};
void __init ath79_register_dsa(struct device *netdev,
struct device *miidev,
struct dsa_platform_data *d)
{
int i;
d->netdev = netdev;
for (i = 0; i < d->nr_chips; i++)
d->chip[i].host_dev = miidev;
ar71xx_dsa_switch_device.dev.platform_data = d;
platform_device_register(&ar71xx_dsa_switch_device);
}

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target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h
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/*
* Atheros AR71xx DSA switch device support
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _ATH79_DEV_DSA_H
#define _ATH79_DEV_DSA_H
#include <net/dsa.h>
void ath79_register_dsa(struct device *netdev,
struct device *miidev,
struct dsa_platform_data *d);
#endif /* _ATH79_DEV_DSA_H */

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target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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55
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
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/*
* Atheros AR71xx SoC device definitions
*
* Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _ATH79_DEV_ETH_H
#define _ATH79_DEV_ETH_H
#include <asm/mach-ath79/ag71xx_platform.h>
struct platform_device;
extern unsigned char ath79_mac_base[] __initdata;
void ath79_parse_ascii_mac(char *mac_str, u8 *mac);
void ath79_extract_mac_reverse(u8 *ptr, u8 *out);
void ath79_init_mac(unsigned char *dst, const unsigned char *src,
int offset);
void ath79_init_local_mac(unsigned char *dst, const unsigned char *src);
struct ath79_eth_pll_data {
u32 pll_10;
u32 pll_100;
u32 pll_1000;
};
extern struct ath79_eth_pll_data ath79_eth0_pll_data;
extern struct ath79_eth_pll_data ath79_eth1_pll_data;
extern struct ag71xx_platform_data ath79_eth0_data;
extern struct ag71xx_platform_data ath79_eth1_data;
extern struct platform_device ath79_eth0_device;
extern struct platform_device ath79_eth1_device;
void ath79_register_eth(unsigned int id);
extern struct ag71xx_switch_platform_data ath79_switch_data;
extern struct ag71xx_mdio_platform_data ath79_mdio0_data;
extern struct ag71xx_mdio_platform_data ath79_mdio1_data;
extern struct platform_device ath79_mdio0_device;
extern struct platform_device ath79_mdio1_device;
void ath79_register_mdio(unsigned int id, u32 phy_mask);
void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
void ath79_setup_ar934x_eth_cfg(u32 mask);
void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
void ath79_setup_qca955x_eth_cfg(u32 mask);
void ath79_setup_qca956x_eth_cfg(u32 mask);
#endif /* _ATH79_DEV_ETH_H */

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target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c
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/*
* Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/concat.h>
#include "dev-spi.h"
#include "dev-m25p80.h"
static struct spi_board_info ath79_spi_info[] = {
{
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 25000000,
.modalias = "m25p80",
},
{
.bus_num = 0,
.chip_select = 1,
.max_speed_hz = 25000000,
.modalias = "m25p80",
}
};
static struct ath79_spi_platform_data ath79_spi_data;
void __init ath79_register_m25p80(struct flash_platform_data *pdata)
{
ath79_spi_data.bus_num = 0;
ath79_spi_data.num_chipselect = 1;
ath79_spi_info[0].platform_data = pdata;
ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1);
}
static struct flash_platform_data *multi_pdata;
static struct mtd_info *concat_devs[2] = { NULL, NULL };
static struct work_struct mtd_concat_work;
static void mtd_concat_add_work(struct work_struct *work)
{
struct mtd_info *mtd;
mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash");
mtd_device_register(mtd, multi_pdata->parts, multi_pdata->nr_parts);
}
static void mtd_concat_add(struct mtd_info *mtd)
{
static bool registered = false;
if (registered)
return;
if (!strcmp(mtd->name, "spi0.0"))
concat_devs[0] = mtd;
else if (!strcmp(mtd->name, "spi0.1"))
concat_devs[1] = mtd;
else
return;
if (!concat_devs[0] || !concat_devs[1])
return;
registered = true;
INIT_WORK(&mtd_concat_work, mtd_concat_add_work);
schedule_work(&mtd_concat_work);
}
static void mtd_concat_remove(struct mtd_info *mtd)
{
}
static void add_mtd_concat_notifier(void)
{
static struct mtd_notifier not = {
.add = mtd_concat_add,
.remove = mtd_concat_remove,
};
register_mtd_user(&not);
}
void __init ath79_register_m25p80_multi(struct flash_platform_data *pdata)
{
multi_pdata = pdata;
add_mtd_concat_notifier();
ath79_spi_data.bus_num = 0;
ath79_spi_data.num_chipselect = 2;
ath79_register_spi(&ath79_spi_data, ath79_spi_info, 2);
}

17
target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h
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/*
* Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _ATH79_DEV_M25P80_H
#define _ATH79_DEV_M25P80_H
#include <linux/spi/flash.h>
void ath79_register_m25p80(struct flash_platform_data *pdata) __init;
void ath79_register_m25p80_multi(struct flash_platform_data *pdata) __init;
#endif /* _ATH79_DEV_M25P80_H */

141
target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c
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/*
* Atheros AR934X SoCs built-in NAND flash controller support
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/platform/ar934x_nfc.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "dev-nfc.h"
static struct resource ath79_nfc_resources[2];
static u64 ar934x_nfc_dmamask = DMA_BIT_MASK(32);
static struct ar934x_nfc_platform_data ath79_nfc_data;
static struct platform_device ath79_nfc_device = {
.name = AR934X_NFC_DRIVER_NAME,
.id = -1,
.resource = ath79_nfc_resources,
.num_resources = ARRAY_SIZE(ath79_nfc_resources),
.dev = {
.dma_mask = &ar934x_nfc_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &ath79_nfc_data,
},
};
static void __init ath79_nfc_init_resource(struct resource res[2],
unsigned long base,
unsigned long size,
int irq)
{
memset(res, 0, sizeof(struct resource) * 2);
res[0].flags = IORESOURCE_MEM;
res[0].start = base;
res[0].end = base + size - 1;
res[1].flags = IORESOURCE_IRQ;
res[1].start = irq;
res[1].end = irq;
}
static void ar934x_nfc_hw_reset(bool active)
{
if (active) {
ath79_device_reset_set(AR934X_RESET_NANDF);
udelay(100);
ath79_device_reset_set(AR934X_RESET_ETH_SWITCH_ANALOG);
udelay(250);
} else {
ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH_ANALOG);
udelay(250);
ath79_device_reset_clear(AR934X_RESET_NANDF);
udelay(100);
}
}
static void ar934x_nfc_setup(void)
{
ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset;
ath79_nfc_init_resource(ath79_nfc_resources,
AR934X_NFC_BASE, AR934X_NFC_SIZE,
ATH79_MISC_IRQ(21));
platform_device_register(&ath79_nfc_device);
}
static void qca955x_nfc_hw_reset(bool active)
{
if (active) {
ath79_device_reset_set(QCA955X_RESET_NANDF);
udelay(250);
} else {
ath79_device_reset_clear(QCA955X_RESET_NANDF);
udelay(100);
}
}
static void qca955x_nfc_setup(void)
{
ath79_nfc_data.hw_reset = qca955x_nfc_hw_reset;
ath79_nfc_init_resource(ath79_nfc_resources,
QCA955X_NFC_BASE, QCA955X_NFC_SIZE,
ATH79_MISC_IRQ(21));
platform_device_register(&ath79_nfc_device);
}
void __init ath79_nfc_set_select_chip(void (*f)(int chip_no))
{
ath79_nfc_data.select_chip = f;
}
void __init ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd))
{
ath79_nfc_data.scan_fixup = f;
}
void __init ath79_nfc_set_swap_dma(bool enable)
{
ath79_nfc_data.swap_dma = enable;
}
void __init ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode)
{
ath79_nfc_data.ecc_mode = mode;
}
void __init ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts)
{
ath79_nfc_data.parts = parts;
ath79_nfc_data.nr_parts = nr_parts;
}
void __init ath79_register_nfc(void)
{
if (soc_is_ar934x())
ar934x_nfc_setup();
else if (soc_is_qca955x())
qca955x_nfc_setup();
else
BUG();
}

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target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h
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/*
* Atheros AR934X SoCs built-in NAND Flash Controller support
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _ATH79_DEV_NFC_H
#define _ATH79_DEV_NFC_H
struct mtd_partition;
enum ar934x_nfc_ecc_mode;
#ifdef CONFIG_ATH79_DEV_NFC
void ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts);
void ath79_nfc_set_select_chip(void (*f)(int chip_no));
void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd));
void ath79_nfc_set_swap_dma(bool enable);
void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode);
void ath79_register_nfc(void);
#else
static inline void ath79_nfc_set_parts(struct mtd_partition *parts,
int nr_parts) {}
static inline void ath79_nfc_set_select_chip(void (*f)(int chip_no)) {}
static inline void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) {}
static inline void ath79_nfc_set_swap_dma(bool enable) {}
static inline void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode) {}
static inline void ath79_register_nfc(void) {}
#endif
#endif /* _ATH79_DEV_NFC_H */

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target/linux/ar71xx/files/arch/mips/ath79/mach-a60.c
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/*
* OpenMesh A60 support
*
* Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
* Copyright (C) 2014-2017 Sven Eckelmann <sven@open-mesh.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/platform_data/phy-at803x.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
#include "common.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-leds-gpio.h"
#include "dev-gpio-buttons.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "pci.h"
#include "dev-usb.h"
#define A60_GPIO_LED_RED 22
#define A60_GPIO_LED_GREEN 23
#define A60_GPIO_LED_BLUE 13
#define A60_GPIO_BTN_RESET 17
#define A60_KEYS_POLL_INTERVAL 20 /* msecs */
#define A60_KEYS_DEBOUNCE_INTERVAL (3 * A60_KEYS_POLL_INTERVAL)
#define A60_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led a40_leds_gpio[] __initdata = {
{
.name = "a40:red:status",
.gpio = A60_GPIO_LED_RED,
}, {
.name = "a40:green:status",
.gpio = A60_GPIO_LED_GREEN,
}, {
.name = "a40:blue:status",
.gpio = A60_GPIO_LED_BLUE,
}
};
static struct gpio_led a60_leds_gpio[] __initdata = {
{
.name = "a60:red:status",
.gpio = A60_GPIO_LED_RED,
}, {
.name = "a60:green:status",
.gpio = A60_GPIO_LED_GREEN,
}, {
.name = "a60:blue:status",
.gpio = A60_GPIO_LED_BLUE,
}
};
static struct gpio_keys_button a60_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = A60_KEYS_DEBOUNCE_INTERVAL,
.gpio = A60_GPIO_BTN_RESET,
.active_low = 1,
},
};
static struct at803x_platform_data a60_at803x_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 1,
};
static struct mdio_board_info a60_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.mdio_addr = 1,
.platform_data = &a60_at803x_data,
},
{
.bus_id = "ag71xx-mdio.0",
.mdio_addr = 2,
.platform_data = &a60_at803x_data,
},
};
static void __init a60_setup_qca955x_eth_cfg(u32 mask,
unsigned int rxd,
unsigned int rxdv,
unsigned int txd,
unsigned int txe)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = mask;
t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init a60_setup_common(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
ath79_register_usb();
ath79_register_m25p80(NULL);
ath79_register_gpio_keys_polled(-1, A60_KEYS_POLL_INTERVAL,
ARRAY_SIZE(a60_gpio_keys),
a60_gpio_keys);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + A60_WMAC_CALDATA_OFFSET, mac);
a60_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(a60_mdio0_info, ARRAY_SIZE(a60_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY1 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(1);
ath79_eth0_pll_data.pll_1000 = 0x82000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_register_eth(0);
/* GMAC1 is connected to MDIO1 in SGMII mode */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth1_data.phy_mask = BIT(2);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init a40_setup(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(a40_leds_gpio), a40_leds_gpio);
a60_setup_common();
}
MIPS_MACHINE(ATH79_MACH_A40, "A40", "OpenMesh A40", a40_setup);
static void __init a60_setup(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(a60_leds_gpio), a60_leds_gpio);
a60_setup_common();
}
MIPS_MACHINE(ATH79_MACH_A60, "A60", "OpenMesh A60", a60_setup);

147
target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap120c.c
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/*
* ALFA Network AP120C board support
*
* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2016 Luka Perkov <luka@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/ar8216_platform.h>
#include <linux/ath9k_platform.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-spi.h"
#include "dev-ap9x-pci.h"
#include "dev-wmac.h"
#include "machtypes.h"
#define ALFA_AP120C_GPIO_LED 0
#define ALFA_AP120C_GPIO_BUTTON_WIFI 16
#define ALFA_AP120C_GPIO_WATCH_DOG 20
#define ALFA_AP120C_KEYS_POLL_INTERVAL 20 /* msecs */
#define ALFA_AP120C_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_AP120C_KEYS_POLL_INTERVAL)
#define ALFA_AP120C_MAC_OFFSET 0x1002
#define ALFA_AP120C_CAL0_OFFSET 0x1000
static struct gpio_keys_button alfa_ap120c_gpio_keys[] __initdata = {
{
.desc = "Wireless button",
.type = EV_KEY,
.code = KEY_RFKILL,
.debounce_interval = ALFA_AP120C_KEYS_DEBOUNCE_INTERVAL,
.gpio = ALFA_AP120C_GPIO_BUTTON_WIFI,
.active_low = 1,
}
};
static struct gpio_led alfa_ap120c_leds_gpio[] __initdata = {
{
.name = "ap120c:red:wlan",
.gpio = ALFA_AP120C_GPIO_LED,
.active_low = 0,
}
};
static struct ar8327_pad_cfg ap120c_ar8327_pad0_cfg = {
.mode = AR8327_PAD_MAC_RGMII,
.txclk_delay_en = true,
.rxclk_delay_en = true,
.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
};
static struct ar8327_platform_data ap120c_ar8327_data = {
.pad0_cfg = &ap120c_ar8327_pad0_cfg,
.port0_cfg = {
.force_link = 1,
.speed = AR8327_PORT_SPEED_1000,
.duplex = 1,
.txpause = 1,
.rxpause = 1,
},
};
static struct mdio_board_info ap120c_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.mdio_addr = 0,
.platform_data = &ap120c_ar8327_data,
},
};
static struct flash_platform_data flash __initdata = { NULL, NULL, 0 };
#define ALFA_AP120C_LAN_PHYMASK BIT(5)
#define ALFA_AP120C_MDIO_PHYMASK ALFA_AP120C_LAN_PHYMASK
static void __init alfa_ap120c_init(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 mac[ETH_ALEN];
struct ath9k_platform_data *pdata;
ath79_register_leds_gpio(-1, ARRAY_SIZE(alfa_ap120c_leds_gpio),
alfa_ap120c_leds_gpio);
ath79_register_gpio_keys_polled(-1, ALFA_AP120C_KEYS_POLL_INTERVAL,
ARRAY_SIZE(alfa_ap120c_gpio_keys),
alfa_ap120c_gpio_keys);
ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
AR71XX_GPIO_FUNC_SPI_CS2_EN);
ath79_register_m25p80_multi(&flash);
ath79_init_mac(mac, art + ALFA_AP120C_MAC_OFFSET, 1);
ath79_register_wmac(art + ALFA_AP120C_CAL0_OFFSET, mac);
ath79_init_mac(mac, art + ALFA_AP120C_MAC_OFFSET, 2);
ap91_pci_init(NULL, mac);
pdata = ap9x_pci_get_wmac_data(0);
if (!pdata) {
pr_err("ap120c: unable to get address of wlan data\n");
return;
}
pdata->use_eeprom = true;
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
BIT(15) | BIT(17) | BIT(19) | BIT(21));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + ALFA_AP120C_MAC_OFFSET, 0);
mdiobus_register_board_info(ap120c_mdio0_info, ARRAY_SIZE(ap120c_mdio0_info));
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = ALFA_AP120C_LAN_PHYMASK;
ath79_eth0_pll_data.pll_1000 = 0x42000000;
ath79_eth0_pll_data.pll_10 = 0x00001313;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
}
MIPS_MACHINE(ATH79_MACH_ALFA_AP120C, "ALFA-AP120C", "ALFA Network AP120C",
alfa_ap120c_init);

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target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c
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/*
* ALFA Network AP96 board support
*
* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <linux/spi/spi.h>
#include <linux/spi/mmc_spi.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "machtypes.h"
#include "pci.h"
#define ALFA_AP96_GPIO_PCIE_RESET 2
#define ALFA_AP96_GPIO_SIM_DETECT 3
#define ALFA_AP96_GPIO_MICROSD_CD 4
#define ALFA_AP96_GPIO_PCIE_W_DISABLE 5
#define ALFA_AP96_GPIO_BUTTON_RESET 11
#define ALFA_AP96_KEYS_POLL_INTERVAL 20 /* msecs */
#define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_AP96_KEYS_POLL_INTERVAL)
static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL,
.gpio = ALFA_AP96_GPIO_BUTTON_RESET,
.active_low = 1,
}
};
static struct mmc_spi_platform_data alfa_ap96_mmc_data = {
.flags = MMC_SPI_USE_CD_GPIO,
.cd_gpio = ALFA_AP96_GPIO_MICROSD_CD,
.cd_debounce = 1,
.caps = MMC_CAP_NEEDS_POLL,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
};
static struct spi_board_info alfa_ap96_spi_info[] = {
{
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 25000000,
.modalias = "m25p80",
}, {
.bus_num = 0,
.chip_select = 1,
.max_speed_hz = 25000000,
.modalias = "mmc_spi",
.platform_data = &alfa_ap96_mmc_data,
}, {
.bus_num = 0,
.chip_select = 2,
.max_speed_hz = 6250000,
.modalias = "rtc-pcf2123",
},
};
static struct ath79_spi_platform_data alfa_ap96_spi_data = {
.bus_num = 0,
.num_chipselect = 3,
};
static void __init alfa_ap96_gpio_setup(void)
{
ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
AR71XX_GPIO_FUNC_SPI_CS2_EN);
gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD");
gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD);
gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset");
gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1);
gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable");
gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1);
}
#define ALFA_AP96_WAN_PHYMASK BIT(4)
#define ALFA_AP96_LAN_PHYMASK BIT(5)
#define ALFA_AP96_MDIO_PHYMASK (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK)
static void __init alfa_ap96_init(void)
{
alfa_ap96_gpio_setup();
ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK);
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK;
ath79_eth1_pll_data.pll_1000 = 0x110000;
ath79_register_eth(0);
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK;
ath79_eth1_pll_data.pll_1000 = 0x110000;
ath79_register_eth(1);
ath79_register_pci();
ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info,
ARRAY_SIZE(alfa_ap96_spi_info));
ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL,
ARRAY_SIZE(alfa_ap96_gpio_keys),
alfa_ap96_gpio_keys);
ath79_register_usb();
}
MIPS_MACHINE(ATH79_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96",
alfa_ap96_init);

113
target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c
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/*
* ALFA Network N2/N5 board support
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-ap9x-pci.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "machtypes.h"
#define ALFA_NX_GPIO_LED_2 17
#define ALFA_NX_GPIO_LED_3 16
#define ALFA_NX_GPIO_LED_5 12
#define ALFA_NX_GPIO_LED_6 8
#define ALFA_NX_GPIO_LED_7 6
#define ALFA_NX_GPIO_LED_8 7
#define ALFA_NX_GPIO_BTN_RESET 11
#define ALFA_NX_KEYS_POLL_INTERVAL 20 /* msecs */
#define ALFA_NX_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_NX_KEYS_POLL_INTERVAL)
#define ALFA_NX_MAC0_OFFSET 0
#define ALFA_NX_MAC1_OFFSET 6
#define ALFA_NX_CALDATA_OFFSET 0x1000
static struct gpio_keys_button alfa_nx_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ALFA_NX_KEYS_DEBOUNCE_INTERVAL,
.gpio = ALFA_NX_GPIO_BTN_RESET,
.active_low = 1,
}
};
static struct gpio_led alfa_nx_leds_gpio[] __initdata = {
{
.name = "alfa:green:led_2",
.gpio = ALFA_NX_GPIO_LED_2,
.active_low = 1,
}, {
.name = "alfa:green:led_3",
.gpio = ALFA_NX_GPIO_LED_3,
.active_low = 1,
}, {
.name = "alfa:red:led_5",
.gpio = ALFA_NX_GPIO_LED_5,
.active_low = 1,
}, {
.name = "alfa:amber:led_6",
.gpio = ALFA_NX_GPIO_LED_6,
.active_low = 1,
}, {
.name = "alfa:green:led_7",
.gpio = ALFA_NX_GPIO_LED_7,
.active_low = 1,
}, {
.name = "alfa:green:led_8",
.gpio = ALFA_NX_GPIO_LED_8,
.active_low = 1,
}
};
static void __init alfa_nx_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(0, ARRAY_SIZE(alfa_nx_leds_gpio),
alfa_nx_leds_gpio);
ath79_register_gpio_keys_polled(-1, ALFA_NX_KEYS_POLL_INTERVAL,
ARRAY_SIZE(alfa_nx_gpio_keys),
alfa_nx_gpio_keys);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr,
art + ALFA_NX_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr,
art + ALFA_NX_MAC1_OFFSET, 0);
/* WAN port */
ath79_register_eth(0);
/* LAN port */
ath79_register_eth(1);
ap91_pci_init(art + ALFA_NX_CALDATA_OFFSET, NULL);
}
MIPS_MACHINE(ATH79_MACH_ALFA_NX, "ALFA-NX", "ALFA Network N2/N5",
alfa_nx_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c
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/*
* Allnet ALL0258N support
*
* Copyright (C) 2011 Daniel Golle <dgolle@allnet.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <asm/mach-ath79/ath79.h>
#include "dev-eth.h"
#include "dev-ap9x-pci.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "machtypes.h"
/* found via /sys/gpio/... try and error */
#define ALL0258N_GPIO_BTN_RESET 1
#define ALL0258N_GPIO_LED_RSSIHIGH 13
#define ALL0258N_GPIO_LED_RSSIMEDIUM 15
#define ALL0258N_GPIO_LED_RSSILOW 14
/* defaults taken from others machs */
#define ALL0258N_KEYS_POLL_INTERVAL 20 /* msecs */
#define ALL0258N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0258N_KEYS_POLL_INTERVAL)
/* showed up in the original firmware's bootlog */
#define ALL0258N_SEC_PHYMASK BIT(3)
static struct gpio_led all0258n_leds_gpio[] __initdata = {
{
.name = "all0258n:green:rssihigh",
.gpio = ALL0258N_GPIO_LED_RSSIHIGH,
.active_low = 1,
}, {
.name = "all0258n:yellow:rssimedium",
.gpio = ALL0258N_GPIO_LED_RSSIMEDIUM,
.active_low = 1,
}, {
.name = "all0258n:red:rssilow",
.gpio = ALL0258N_GPIO_LED_RSSILOW,
.active_low = 1,
}
};
static struct gpio_keys_button all0258n_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ALL0258N_KEYS_DEBOUNCE_INTERVAL,
.gpio = ALL0258N_GPIO_BTN_RESET,
.active_low = 1,
}
};
static void __init all0258n_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f7f0000);
u8 *ee = (u8 *) KSEG1ADDR(0x1f7f1000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(all0258n_leds_gpio),
all0258n_leds_gpio);
ath79_register_gpio_keys_polled(-1, ALL0258N_KEYS_POLL_INTERVAL,
ARRAY_SIZE(all0258n_gpio_keys),
all0258n_gpio_keys);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_eth1_data.phy_mask = ALL0258N_SEC_PHYMASK;
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ap91_pci_init(ee, mac);
}
MIPS_MACHINE(ATH79_MACH_ALL0258N, "ALL0258N", "Allnet ALL0258N",
all0258n_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c
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/*
* Allnet ALL0315N support
*
* Copyright (C) 2012 Daniel Golle <dgolle@allnet.de>
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-ap9x-pci.h"
#include "dev-gpio-buttons.h"
#include "dev-m25p80.h"
#include "dev-leds-gpio.h"
#include "machtypes.h"
#include "pci.h"
#define ALL0315N_GPIO_BTN_RESET 0
#define ALL0315N_GPIO_LED_RSSIHIGH 14
#define ALL0315N_GPIO_LED_RSSIMEDIUM 15
#define ALL0315N_GPIO_LED_RSSILOW 16
#define ALL0315N_KEYS_POLL_INTERVAL 20 /* msecs */
#define ALL0315N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0315N_KEYS_POLL_INTERVAL)
static struct gpio_led all0315n_leds_gpio[] __initdata = {
{
.name = "all0315n:green:rssihigh",
.gpio = ALL0315N_GPIO_LED_RSSIHIGH,
.active_low = 1,
}, {
.name = "all0315n:yellow:rssimedium",
.gpio = ALL0315N_GPIO_LED_RSSIMEDIUM,
.active_low = 1,
}, {
.name = "all0315n:red:rssilow",
.gpio = ALL0315N_GPIO_LED_RSSILOW,
.active_low = 1,
}
};
static struct gpio_keys_button all0315n_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ALL0315N_KEYS_DEBOUNCE_INTERVAL,
.gpio = ALL0315N_GPIO_BTN_RESET,
.active_low = 1,
}
};
static void __init all0315n_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1ffc0000);
u8 *ee = (u8 *) KSEG1ADDR(0x1ffc1000);
ath79_register_m25p80(NULL);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(all0315n_leds_gpio),
all0315n_leds_gpio);
ath79_register_gpio_keys_polled(-1, ALL0315N_KEYS_POLL_INTERVAL,
ARRAY_SIZE(all0315n_gpio_keys),
all0315n_gpio_keys);
ap9x_pci_setup_wmac_led_pin(0, 1);
ap91_pci_init(ee, NULL);
}
MIPS_MACHINE(ATH79_MACH_ALL0315N, "ALL0315N", "Allnet ALL0315N",
all0315n_setup);

98
target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s1.c
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/*
* Bitmain Antminer S1 board support
*
* Copyright (C) 2015 L. D. Pinney <ldpinney@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "dev-usb.h"
#define ANTMINER_S1_GPIO_BTN_RESET 11
#define ANTMINER_S1_GPIO_LED_SYSTEM 23
#define ANTMINER_S1_GPIO_LED_WLAN 0
#define ANTMINER_S1_GPIO_USB_POWER 26
#define ANTMINER_S1_KEYSPOLL_INTERVAL 20 /* msecs */
#define ANTMINER_S1_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S1_KEYSPOLL_INTERVAL)
static const char *ANTMINER_S1_part_probes[] = {
"tp-link",
NULL,
};
static struct flash_platform_data ANTMINER_S1_flash_data = {
.part_probes = ANTMINER_S1_part_probes,
};
static struct gpio_led ANTMINER_S1_leds_gpio[] __initdata = {
{
.name = "antminer-s1:green:system",
.gpio = ANTMINER_S1_GPIO_LED_SYSTEM,
.active_low = 0,
},{
.name = "antminer-s1:green:wlan",
.gpio = ANTMINER_S1_GPIO_LED_WLAN,
.active_low = 0,
},
};
static struct gpio_keys_button ANTMINER_S1_GPIO_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ANTMINER_S1_KEYSDEBOUNCE_INTERVAL,
.gpio = ANTMINER_S1_GPIO_BTN_RESET,
.active_low = 0,
},
};
static void __init antminer_s1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S1_leds_gpio),
ANTMINER_S1_leds_gpio);
ath79_register_gpio_keys_polled(-1, ANTMINER_S1_KEYSPOLL_INTERVAL,
ARRAY_SIZE(ANTMINER_S1_GPIO_keys),
ANTMINER_S1_GPIO_keys);
gpio_request_one(ANTMINER_S1_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_m25p80(&ANTMINER_S1_flash_data);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
MIPS_MACHINE(ATH79_MACH_ANTMINER_S1, "ANTMINER-S1",
"Antminer-S1", antminer_s1_setup);

103
target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s3.c
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/*
* Bitmain Antminer S3 board support
*
* Copyright (C) 2015 L. D. Pinney <ldpinney@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "dev-usb.h"
#define ANTMINER_S3_GPIO_LED_WLAN 0
#define ANTMINER_S3_GPIO_LED_SYSTEM 17
#define ANTMINER_S3_GPIO_LED_LAN 22
#define ANTMINER_S3_GPIO_USB_POWER 26
#define ANTMINER_S3_GPIO_BTN_RESET 11
#define ANTMINER_S3_KEYSPOLL_INTERVAL 88 /* msecs */
#define ANTMINER_S3_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S3_KEYSPOLL_INTERVAL)
static const char *ANTMINER_S3_part_probes[] = {
"tp-link",
NULL,
};
static struct flash_platform_data ANTMINER_S3_flash_data = {
.part_probes = ANTMINER_S3_part_probes,
};
static struct gpio_led ANTMINER_S3_leds_gpio[] __initdata = {
{
.name = "antminer-s3:green:wlan",
.gpio = ANTMINER_S3_GPIO_LED_WLAN,
.active_low = 0,
},{
.name = "antminer-s3:green:system",
.gpio = ANTMINER_S3_GPIO_LED_SYSTEM,
.active_low = 0,
},{
.name = "antminer-s3:yellow:lan",
.gpio = ANTMINER_S3_GPIO_LED_LAN,
.active_low = 0,
},
};
static struct gpio_keys_button ANTMINER_S3_GPIO_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ANTMINER_S3_KEYSDEBOUNCE_INTERVAL,
.gpio = ANTMINER_S3_GPIO_BTN_RESET,
.active_low = 0,
},
};
static void __init antminer_s3_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S3_leds_gpio),
ANTMINER_S3_leds_gpio);
ath79_register_gpio_keys_polled(-1, ANTMINER_S3_KEYSPOLL_INTERVAL,
ARRAY_SIZE(ANTMINER_S3_GPIO_keys),
ANTMINER_S3_GPIO_keys);
gpio_request_one(ANTMINER_S3_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_m25p80(&ANTMINER_S3_flash_data);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
MIPS_MACHINE(ATH79_MACH_ANTMINER_S3, "ANTMINER-S3",
"Antminer-S3", antminer_s3_setup);

98
target/linux/ar71xx/files/arch/mips/ath79/mach-antrouter-r1.c
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/*
* Bitmain Antrouter R1 board support
*
* Copyright (C) 2015 L. D. Pinney <ldpinney@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "dev-usb.h"
#define ANTROUTER_R1_GPIO_BTN_RESET 11
#define ANTROUTER_R1_GPIO_LED_WLAN 0
#define ANTROUTER_R1_GPIO_LED_BTC 22
#define ANTROUTER_R1_GPIO_USB_POWER 18
#define ANTROUTER_R1_KEYSPOLL_INTERVAL 44 /* msecs */
#define ANTROUTER_R1_KEYSDEBOUNCE_INTERVAL (4 * ANTROUTER_R1_KEYSPOLL_INTERVAL)
static const char *ANTROUTER_R1_part_probes[] = {
"tp-link",
NULL,
};
static struct flash_platform_data ANTROUTER_R1_flash_data = {
.part_probes = ANTROUTER_R1_part_probes,
};
static struct gpio_led ANTROUTER_R1_leds_gpio[] __initdata = {
{
.name = "antrouter-r1:green:wlan",
.gpio = ANTROUTER_R1_GPIO_LED_WLAN,
.active_low = 0,
},{
.name = "antrouter-r1:green:system",
.gpio = ANTROUTER_R1_GPIO_LED_BTC,
.active_low = 0,
},
};
static struct gpio_keys_button ANTROUTER_R1_GPIO_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ANTROUTER_R1_KEYSDEBOUNCE_INTERVAL,
.gpio = ANTROUTER_R1_GPIO_BTN_RESET,
.active_low = 0,
},
};
static void __init antrouter_r1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTROUTER_R1_leds_gpio),
ANTROUTER_R1_leds_gpio);
ath79_register_gpio_keys_polled(-1, ANTROUTER_R1_KEYSPOLL_INTERVAL,
ARRAY_SIZE(ANTROUTER_R1_GPIO_keys),
ANTROUTER_R1_GPIO_keys);
gpio_request_one(ANTROUTER_R1_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_m25p80(&ANTROUTER_R1_flash_data);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
MIPS_MACHINE(ATH79_MACH_ANTROUTER_R1, "ANTROUTER-R1",
"Antrouter-R1", antrouter_r1_setup);

103
target/linux/ar71xx/files/arch/mips/ath79/mach-ap121f.c
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@ -1,103 +0,0 @@
/*
* ALFA Network AP121F board support
*
* Copyright (C) 2017 Piotr Dymacz <pepe2k@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include "machtypes.h"
#define AP121F_GPIO_LED_LAN 17
#define AP121F_GPIO_LED_VPN 27
#define AP121F_GPIO_LED_WLAN 0
#define AP121F_GPIO_MICROSD_EN 26
#define AP121F_GPIO_BTN_RESET 12
#define AP121F_GPIO_BTN_SWITCH 21
#define AP121F_KEYS_POLL_INTERVAL 20
#define AP121F_KEYS_DEBOUNCE_INTERVAL (3 * AP121F_KEYS_POLL_INTERVAL)
#define AP121F_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led ap121f_leds_gpio[] __initdata = {
{
.name = "ap121f:green:lan",
.gpio = AP121F_GPIO_LED_LAN,
.active_low = 1,
}, {
.name = "ap121f:green:vpn",
.gpio = AP121F_GPIO_LED_VPN,
.active_low = 1,
}, {
.name = "ap121f:green:wlan",
.gpio = AP121F_GPIO_LED_WLAN,
.active_low = 0,
},
};
static struct gpio_keys_button ap121f_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = AP121F_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP121F_GPIO_BTN_RESET,
.active_low = 1,
}, {
.desc = "switch",
.type = EV_KEY,
.code = BTN_0,
.debounce_interval = AP121F_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP121F_GPIO_BTN_SWITCH,
.active_low = 0,
},
};
static void __init ap121f_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f040000);
ath79_register_m25p80(NULL);
ath79_setup_ar933x_phy4_switch(false, false);
/* LAN */
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
ath79_register_eth(0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121f_leds_gpio),
ap121f_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP121F_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap121f_gpio_keys),
ap121f_gpio_keys);
gpio_request_one(AP121F_GPIO_MICROSD_EN,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"microSD enable");
ath79_register_wmac(art + AP121F_WMAC_CALDATA_OFFSET, NULL);
ath79_register_usb();
}
MIPS_MACHINE(ATH79_MACH_AP121F, "AP121F", "ALFA Network AP121F", ap121f_setup);

189
target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c
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/*
* Atheros AP132 reference board support
*
* Copyright (c) 2012 Qualcomm Atheros
* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (c) 2013 Embedded Wireless GmbH <info@embeddedwireless.de>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include <linux/platform_device.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-ap9x-pci.h"
#include "dev-gpio-buttons.h"
#include "dev-eth.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include "machtypes.h"
#define AP132_GPIO_LED_USB 4
#define AP132_GPIO_LED_WLAN_5G 12
#define AP132_GPIO_LED_WLAN_2G 13
#define AP132_GPIO_LED_STATUS_RED 14
#define AP132_GPIO_LED_WPS_RED 15
#define AP132_GPIO_BTN_WPS 16
#define AP132_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP132_KEYS_DEBOUNCE_INTERVAL (3 * AP132_KEYS_POLL_INTERVAL)
#define AP132_MAC0_OFFSET 0
#define AP132_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led ap132_leds_gpio[] __initdata = {
{
.name = "ap132:red:status",
.gpio = AP132_GPIO_LED_STATUS_RED,
.active_low = 1,
},
{
.name = "ap132:red:wps",
.gpio = AP132_GPIO_LED_WPS_RED,
.active_low = 1,
},
{
.name = "ap132:red:wlan-2g",
.gpio = AP132_GPIO_LED_WLAN_2G,
.active_low = 1,
},
{
.name = "ap132:red:usb",
.gpio = AP132_GPIO_LED_USB,
.active_low = 1,
}
};
static struct gpio_keys_button ap132_gpio_keys[] __initdata = {
{
.desc = "WPS button",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = AP132_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP132_GPIO_BTN_WPS,
.active_low = 1,
},
};
static struct ar8327_pad_cfg ap132_ar8327_pad0_cfg;
static struct ar8327_platform_data ap132_ar8327_data = {
.pad0_cfg = &ap132_ar8327_pad0_cfg,
.port0_cfg = {
.force_link = 1,
.speed = AR8327_PORT_SPEED_1000,
.duplex = 1,
.txpause = 1,
.rxpause = 1,
},
};
static struct mdio_board_info ap132_mdio1_info[] = {
{
.bus_id = "ag71xx-mdio.1",
.mdio_addr = 0,
.platform_data = &ap132_ar8327_data,
},
};
static void __init ap132_mdio_setup(void)
{
void __iomem *base;
u32 t;
#define GPIO_IN_ENABLE3_ADDRESS 0x0050
#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000
#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16
#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)
#define GPIO_OUT_FUNCTION4_ADDRESS 0x003c
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)
base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
t = __raw_readl(base + GPIO_IN_ENABLE3_ADDRESS);
t &= ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK;
t |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19);
__raw_writel(t, base + GPIO_IN_ENABLE3_ADDRESS);
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 19), base + AR71XX_GPIO_REG_OE);
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 17), base + AR71XX_GPIO_REG_OE);
t = __raw_readl(base + GPIO_OUT_FUNCTION4_ADDRESS);
t &= ~(GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK);
t |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21);
__raw_writel(t, base + GPIO_OUT_FUNCTION4_ADDRESS);
iounmap(base);
}
static void __init ap132_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio),
ap132_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap132_gpio_keys),
ap132_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL);
/* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
ap132_ar8327_pad0_cfg.sgmii_delay_en = true;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ap132_mdio_setup();
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0);
mdiobus_register_board_info(ap132_mdio1_info,
ARRAY_SIZE(ap132_mdio1_info));
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_mask = BIT(0);
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(1);
}
MIPS_MACHINE(ATH79_MACH_AP132, "AP132",
"Atheros AP132 reference board",
ap132_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-ap143.c
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/*
* Atheros AP143 reference board support
*
* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include "machtypes.h"
#define AP143_GPIO_LED_WLAN 12
#define AP143_GPIO_LED_WPS 13
#define AP143_GPIO_LED_STATUS 13
#define AP143_GPIO_LED_WAN 4
#define AP143_GPIO_LED_LAN1 16
#define AP143_GPIO_LED_LAN2 15
#define AP143_GPIO_LED_LAN3 14
#define AP143_GPIO_LED_LAN4 11
#define AP143_GPIO_BTN_WPS 17
#define AP143_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP143_KEYS_DEBOUNCE_INTERVAL (3 * AP143_KEYS_POLL_INTERVAL)
#define AP143_MAC0_OFFSET 0
#define AP143_MAC1_OFFSET 6
#define AP143_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led ap143_leds_gpio[] __initdata = {
{
.name = "ap143:green:status",
.gpio = AP143_GPIO_LED_STATUS,
.active_low = 1,
},
{
.name = "ap143:green:wlan",
.gpio = AP143_GPIO_LED_WLAN,
.active_low = 1,
}
};
static struct gpio_keys_button ap143_gpio_keys[] __initdata = {
{
.desc = "WPS button",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = AP143_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP143_GPIO_BTN_WPS,
.active_low = 1,
},
};
static void __init ap143_gpio_led_setup(void)
{
ath79_gpio_direction_select(AP143_GPIO_LED_WAN, true);
ath79_gpio_direction_select(AP143_GPIO_LED_LAN1, true);
ath79_gpio_direction_select(AP143_GPIO_LED_LAN2, true);
ath79_gpio_direction_select(AP143_GPIO_LED_LAN3, true);
ath79_gpio_direction_select(AP143_GPIO_LED_LAN4, true);
ath79_gpio_output_select(AP143_GPIO_LED_WAN,
QCA953X_GPIO_OUT_MUX_LED_LINK5);
ath79_gpio_output_select(AP143_GPIO_LED_LAN1,
QCA953X_GPIO_OUT_MUX_LED_LINK1);
ath79_gpio_output_select(AP143_GPIO_LED_LAN2,
QCA953X_GPIO_OUT_MUX_LED_LINK2);
ath79_gpio_output_select(AP143_GPIO_LED_LAN3,
QCA953X_GPIO_OUT_MUX_LED_LINK3);
ath79_gpio_output_select(AP143_GPIO_LED_LAN4,
QCA953X_GPIO_OUT_MUX_LED_LINK4);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap143_leds_gpio),
ap143_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP143_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap143_gpio_keys),
ap143_gpio_keys);
}
static void __init ap143_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ap143_gpio_led_setup();
ath79_register_usb();
ath79_wmac_set_led_pin(AP143_GPIO_LED_WLAN);
ath79_register_wmac(art + AP143_WMAC_CALDATA_OFFSET, NULL);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + AP143_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + AP143_MAC1_OFFSET, 0);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
}
MIPS_MACHINE(ATH79_MACH_AP143, "AP143", "Qualcomm Atheros AP143 reference board",
ap143_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-ap147.c
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/*
* Atheros AP147 reference board support
*
* Copyright (C) 2014 Matthias Schiffer <mschiffer@universe-factory.net>
* Copyright (C) 2015 Sven Eckelmann <sven@open-mesh.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
#include "common.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "pci.h"
#define AP147_GPIO_LED_WAN 4
#define AP147_GPIO_LED_LAN1 16
#define AP147_GPIO_LED_LAN2 15
#define AP147_GPIO_LED_LAN3 14
#define AP147_GPIO_LED_LAN4 11
#define AP147_GPIO_LED_STATUS 13
#define AP147_GPIO_LED_WLAN_2G 12
#define AP147_GPIO_BTN_WPS 17
#define AP147_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP147_KEYS_DEBOUNCE_INTERVAL (3 * AP147_KEYS_POLL_INTERVAL)
#define AP147_MAC0_OFFSET 0x1000
static struct gpio_led ap147_leds_gpio[] __initdata = {
{
.name = "ap147:green:status",
.gpio = AP147_GPIO_LED_STATUS,
.active_low = 1,
}, {
.name = "ap147:green:wlan-2g",
.gpio = AP147_GPIO_LED_WLAN_2G,
.active_low = 1,
}, {
.name = "ap147:green:lan1",
.gpio = AP147_GPIO_LED_LAN1,
.active_low = 1,
}, {
.name = "ap147:green:lan2",
.gpio = AP147_GPIO_LED_LAN2,
.active_low = 1,
}, {
.name = "ap147:green:lan3",
.gpio = AP147_GPIO_LED_LAN3,
.active_low = 1,
}, {
.name = "ap147:green:lan4",
.gpio = AP147_GPIO_LED_LAN4,
.active_low = 1,
}, {
.name = "ap147:green:wan",
.gpio = AP147_GPIO_LED_WAN,
.active_low = 1,
},
};
static struct gpio_keys_button ap147_gpio_keys[] __initdata = {
{
.desc = "wps button",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = AP147_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP147_GPIO_BTN_WPS,
.active_low = 1,
}
};
static void __init ap147_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap147_leds_gpio),
ap147_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP147_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap147_gpio_keys),
ap147_gpio_keys);
ath79_register_usb();
ath79_register_pci();
ath79_register_wmac(art + AP147_MAC0_OFFSET, NULL);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
/* LAN */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0);
ath79_register_eth(1);
/* WAN */
ath79_switch_data.phy4_mii_en = 1;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.phy_mask = BIT(4);
ath79_init_mac(ath79_eth0_data.mac_addr, art, 1);
ath79_register_eth(0);
}
MIPS_MACHINE(ATH79_MACH_AP147_010, "AP147-010", "Atheros AP147-010 reference board", ap147_setup);

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/*
* Qualcomm Atheros AP152 reference board support
*
* Copyright (c) 2015 Qualcomm Atheros
* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-m25p80.h"
#include "machtypes.h"
#include "pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#define AP152_GPIO_LED_USB0 7
#define AP152_GPIO_LED_USB1 8
#define AP152_GPIO_BTN_RESET 2
#define AP152_GPIO_BTN_WPS 1
#define AP152_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP152_KEYS_DEBOUNCE_INTERVAL (3 * AP152_KEYS_POLL_INTERVAL)
#define AP152_MAC0_OFFSET 0
#define AP152_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led ap152_leds_gpio[] __initdata = {
{
.name = "ap152:green:usb0",
.gpio = AP152_GPIO_LED_USB0,
.active_low = 1,
},
{
.name = "ap152:green:usb1",
.gpio = AP152_GPIO_LED_USB1,
.active_low = 1,
},
};
static struct gpio_keys_button ap152_gpio_keys[] __initdata = {
{
.desc = "WPS button",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP152_GPIO_BTN_WPS,
.active_low = 1,
},
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP152_GPIO_BTN_RESET,
.active_low = 1,
},
};
static struct ar8327_pad_cfg ap152_ar8337_pad0_cfg = {
.mode = AR8327_PAD_MAC_SGMII,
.sgmii_delay_en = true,
};
static struct ar8327_platform_data ap152_ar8337_data = {
.pad0_cfg = &ap152_ar8337_pad0_cfg,
.port0_cfg = {
.force_link = 1,
.speed = AR8327_PORT_SPEED_1000,
.duplex = 1,
.txpause = 1,
.rxpause = 1,
},
};
static struct mdio_board_info ap152_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.mdio_addr = 0,
.platform_data = &ap152_ar8337_data,
},
};
static void __init ap152_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap152_leds_gpio),
ap152_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP152_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap152_gpio_keys),
ap152_gpio_keys);
ath79_register_usb();
platform_device_register(&ath79_mdio0_device);
mdiobus_register_board_info(ap152_mdio0_info,
ARRAY_SIZE(ap152_mdio0_info));
ath79_register_wmac(art + AP152_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
ath79_init_mac(ath79_eth0_data.mac_addr, art + AP152_MAC0_OFFSET, 0);
/* GMAC0 is connected to an AR8337 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
}
MIPS_MACHINE(ATH79_MACH_AP152, "AP152", "Qualcomm Atheros AP152 reference board",
ap152_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-ap531b0.c
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/*
* Rockeetech AP531B0 11ng wireless AP board support
*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2016 Shuanglin Liu <roboidler@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "pci.h"
#include "dev-ap9x-pci.h"
#define AP531B0_GPIO_LED_WLAN 12
#define AP531B0_GPIO_LED_STATUS 11
#define AP531B0_GPIO_RST_BTN 17
#define AP531B0_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP531B0_KEYS_DEBOUNCE_INTERVAL (3 * AP531B0_KEYS_POLL_INTERVAL)
#define AP531B0_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led ap531b0_leds_gpio[] __initdata = {
{
.name = "ap531b0:green:status",
.gpio = AP531B0_GPIO_LED_STATUS,
.active_low = 1,
},
{
.name = "ap531b0:green:wlan",
.gpio = AP531B0_GPIO_LED_WLAN,
.active_low = 1,
}
};
static struct gpio_keys_button ap531b0_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = AP531B0_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP531B0_GPIO_RST_BTN,
.active_low = 1,
},
};
static void __init ap531b0_gpio_led_setup(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap531b0_leds_gpio),
ap531b0_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP531B0_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap531b0_gpio_keys),
ap531b0_gpio_keys);
}
static void __init ap531b0_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *pmac;
ath79_register_m25p80(NULL);
ap531b0_gpio_led_setup();
ath79_register_usb();
ath79_register_pci();
ath79_register_mdio(0, 0x0);
pmac = art + AP531B0_WMAC_CALDATA_OFFSET + 2;
ath79_init_mac(ath79_eth0_data.mac_addr, pmac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, pmac, 2);
ath79_register_wmac(art + AP531B0_WMAC_CALDATA_OFFSET, pmac);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
}
MIPS_MACHINE(ATH79_MACH_AP531B0, "AP531B0", "Rockeetech AP531B0",
ap531b0_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-ap90q.c
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/*
* Support for YunCore boards:
* - AP80Q/AP90Q
* - CPE830
*
* Copyright (C) 2016 Piotr Dymacz <pepe2k@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include "machtypes.h"
/* AP90Q */
#define AP90Q_GPIO_LED_WAN 4
#define AP90Q_GPIO_LED_WLAN 12
#define AP90Q_GPIO_LED_LAN 16
#define AP90Q_GPIO_BTN_RESET 17
#define AP90Q_KEYS_POLL_INTERVAL 20
#define AP90Q_KEYS_DEBOUNCE_INTERVAL (3 * AP90Q_KEYS_POLL_INTERVAL)
static struct gpio_led ap90q_leds_gpio[] __initdata = {
{
.name = "ap90q:green:lan",
.gpio = AP90Q_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "ap90q:green:wan",
.gpio = AP90Q_GPIO_LED_WAN,
.active_low = 1,
},
{
.name = "ap90q:green:wlan",
.gpio = AP90Q_GPIO_LED_WLAN,
.active_low = 1,
},
};
static struct gpio_keys_button ap90q_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = AP90Q_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP90Q_GPIO_BTN_RESET,
.active_low = 1,
},
};
/* CPE830 */
#define CPE830_GPIO_LED_LINK4 0
#define CPE830_GPIO_LED_LINK1 1
#define CPE830_GPIO_LED_LINK2 2
#define CPE830_GPIO_LED_LINK3 3
#define CPE830_GPIO_LED_WAN 4
#define CPE830_GPIO_LED_WLAN 12
#define CPE830_GPIO_LED_LAN 16
#define CPE830_GPIO_BTN_RESET 17
static struct gpio_led cpe830_leds_gpio[] __initdata = {
{
.name = "cpe830:green:lan",
.gpio = CPE830_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "cpe830:green:wan",
.gpio = CPE830_GPIO_LED_WAN,
.active_low = 1,
},
{
.name = "cpe830:green:wlan",
.gpio = CPE830_GPIO_LED_WLAN,
.active_low = 1,
},
{
.name = "cpe830:green:link1",
.gpio = CPE830_GPIO_LED_LINK1,
.active_low = 1,
},
{
.name = "cpe830:green:link2",
.gpio = CPE830_GPIO_LED_LINK2,
.active_low = 1,
},
{
.name = "cpe830:green:link3",
.gpio = CPE830_GPIO_LED_LINK3,
.active_low = 1,
},
{
.name = "cpe830:green:link4",
.gpio = CPE830_GPIO_LED_LINK4,
.active_low = 1,
},
};
static void __init ap90q_cpe830_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff1000);
u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask |= BIT(4);
/* LAN */
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
ath79_register_eth(1);
/* WAN */
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.phy_mask = BIT(4);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
ath79_register_wmac(art, NULL);
/* For LED on GPIO4 */
ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_gpio_direction_select(AP90Q_GPIO_LED_LAN, true);
ath79_gpio_direction_select(AP90Q_GPIO_LED_WAN, true);
ath79_gpio_direction_select(AP90Q_GPIO_LED_WLAN, true);
/* Mute LEDs on boot */
gpio_set_value(AP90Q_GPIO_LED_LAN, 1);
gpio_set_value(AP90Q_GPIO_LED_WAN, 1);
ath79_gpio_output_select(AP90Q_GPIO_LED_LAN, 0);
ath79_gpio_output_select(AP90Q_GPIO_LED_WAN, 0);
ath79_gpio_output_select(AP90Q_GPIO_LED_WLAN, 0);
ath79_register_gpio_keys_polled(-1, AP90Q_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap90q_gpio_keys),
ap90q_gpio_keys);
}
static void __init ap90q_setup(void)
{
ap90q_cpe830_common_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap90q_leds_gpio),
ap90q_leds_gpio);
}
MIPS_MACHINE(ATH79_MACH_AP90Q, "AP90Q", "YunCore AP80Q/AP90Q", ap90q_setup);
static void __init cpe830_setup(void)
{
ap90q_cpe830_common_setup();
ath79_gpio_direction_select(CPE830_GPIO_LED_LINK1, true);
ath79_gpio_direction_select(CPE830_GPIO_LED_LINK2, true);
ath79_gpio_direction_select(CPE830_GPIO_LED_LINK3, true);
ath79_gpio_direction_select(CPE830_GPIO_LED_LINK4, true);
/* Mute LEDs on boot */
gpio_set_value(CPE830_GPIO_LED_LINK1, 1);
gpio_set_value(CPE830_GPIO_LED_LINK2, 1);
gpio_set_value(CPE830_GPIO_LED_LINK3, 1);
gpio_set_value(CPE830_GPIO_LED_LINK4, 1);
ath79_gpio_output_select(CPE830_GPIO_LED_LINK1, 0);
ath79_gpio_output_select(CPE830_GPIO_LED_LINK2, 0);
ath79_gpio_output_select(CPE830_GPIO_LED_LINK3, 0);
ath79_gpio_output_select(CPE830_GPIO_LED_LINK4, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe830_leds_gpio),
cpe830_leds_gpio);
}
MIPS_MACHINE(ATH79_MACH_CPE830, "CPE830", "YunCore CPE830", cpe830_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-ap91-5g.c
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/*
* ALFA Network AP91-5G board support
*
* Copyright (C) 2018 Piotr Dymacz <pepe2k@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "machtypes.h"
#define AP91_5G_GPIO_LED_LAN 17
#define AP91_5G_GPIO_LED_SIGNAL1 12
#define AP91_5G_GPIO_LED_SIGNAL2 8
#define AP91_5G_GPIO_LED_SIGNAL3 6
#define AP91_5G_GPIO_LED_SIGNAL4 7
#define AP91_5G_GPIO_WDT_EN 1
#define AP91_5G_GPIO_WDT_IN 0
#define AP91_5G_GPIO_BTN_RESET 11
#define AP91_5G_KEYS_POLL_INTERVAL 20
#define AP91_5G_KEYS_DEBOUNCE_INTERVAL (3 * AP91_5G_KEYS_POLL_INTERVAL)
#define AP91_5G_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led ap91_5g_leds_gpio[] __initdata = {
{
.name = "ap91-5g:green:lan",
.gpio = AP91_5G_GPIO_LED_LAN,
.active_low = 1,
}, {
.name = "ap91-5g:red:signal1",
.gpio = AP91_5G_GPIO_LED_SIGNAL1,
.active_low = 1,
}, {
.name = "ap91-5g:orange:signal2",
.gpio = AP91_5G_GPIO_LED_SIGNAL2,
.active_low = 1,
}, {
.name = "ap91-5g:green:signal3",
.gpio = AP91_5G_GPIO_LED_SIGNAL3,
.active_low = 1,
}, {
.name = "ap91-5g:green:signal4",
.gpio = AP91_5G_GPIO_LED_SIGNAL4,
.active_low = 1,
},
};
static struct gpio_keys_button ap91_5g_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = AP91_5G_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP91_5G_GPIO_BTN_RESET,
.active_low = 1,
},
};
static void __init ap91_5g_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
gpio_set_value(AP91_5G_GPIO_LED_LAN, 1);
gpio_set_value(AP91_5G_GPIO_LED_SIGNAL3, 1);
gpio_set_value(AP91_5G_GPIO_LED_SIGNAL4, 1);
ath79_register_m25p80(NULL);
ath79_register_mdio(0, 0x0);
/* LAN */
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.speed = SPEED_100;
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
ath79_register_eth(0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap91_5g_leds_gpio),
ap91_5g_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP91_5G_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap91_5g_gpio_keys),
ap91_5g_gpio_keys);
gpio_request_one(AP91_5G_GPIO_WDT_IN,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"WDT input");
gpio_request_one(AP91_5G_GPIO_WDT_EN,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"WDT enable");
ap91_pci_init(art + AP91_5G_WMAC_CALDATA_OFFSET, NULL);
}
MIPS_MACHINE(ATH79_MACH_AP91_5G, "AP91-5G", "ALFA Network AP91-5G",
ap91_5g_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c
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/*
* Atheros AP96 board support
*
* Copyright (C) 2009 Marco Porsch
* Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2010 Atheros Communications
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/mach-ath79/ath79.h>
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-usb.h"
#include "machtypes.h"
#define AP96_GPIO_LED_12_GREEN 0
#define AP96_GPIO_LED_3_GREEN 1
#define AP96_GPIO_LED_2_GREEN 2
#define AP96_GPIO_LED_WPS_GREEN 4
#define AP96_GPIO_LED_5_GREEN 5
#define AP96_GPIO_LED_4_ORANGE 6
/* Reset button - next to the power connector */
#define AP96_GPIO_BTN_RESET 3
/* WPS button - next to a led on right */
#define AP96_GPIO_BTN_WPS 8
#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL)
#define AP96_WMAC0_MAC_OFFSET 0x120c
#define AP96_WMAC1_MAC_OFFSET 0x520c
#define AP96_CALDATA0_OFFSET 0x1000
#define AP96_CALDATA1_OFFSET 0x5000
/*
* AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12
* below (from left to right on the board). Led 1 seems to be on whenever the
* board is powered. Led 11 shows LAN link activity actity. Led 3 is orange;
* others are green.
*
* In addition, there is one led next to a button on the right side for WPS.
*/
static struct gpio_led ap96_leds_gpio[] __initdata = {
{
.name = "ap96:green:led2",
.gpio = AP96_GPIO_LED_2_GREEN,
.active_low = 1,
}, {
.name = "ap96:green:led3",
.gpio = AP96_GPIO_LED_3_GREEN,
.active_low = 1,
}, {
.name = "ap96:orange:led4",
.gpio = AP96_GPIO_LED_4_ORANGE,
.active_low = 1,
}, {
.name = "ap96:green:led5",
.gpio = AP96_GPIO_LED_5_GREEN,
.active_low = 1,
}, {
.name = "ap96:green:led12",
.gpio = AP96_GPIO_LED_12_GREEN,
.active_low = 1,
}, { /* next to a button on right */
.name = "ap96:green:wps",
.gpio = AP96_GPIO_LED_WPS_GREEN,
.active_low = 1,
}
};
static struct gpio_keys_button ap96_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP96_GPIO_BTN_RESET,
.active_low = 1,
}, {
.desc = "wps",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP96_GPIO_BTN_WPS,
.active_low = 1,
}
};
#define AP96_WAN_PHYMASK 0x10
#define AP96_LAN_PHYMASK 0x0f
static void __init ap96_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK;
ath79_eth1_pll_data.pll_1000 = 0x1f000000;
ath79_register_eth(1);
ath79_register_usb();
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio),
ap96_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap96_gpio_keys),
ap96_gpio_keys);
ap94_pci_init(art + AP96_CALDATA0_OFFSET,
art + AP96_WMAC0_MAC_OFFSET,
art + AP96_CALDATA1_OFFSET,
art + AP96_WMAC1_MAC_OFFSET);
}
MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup);

227
target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c25-v1.c
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/*
* TP-Link Archer C25 v1 board support
*
* Copyright (C) 2017 Ludwig Thomeczek <ledesrc@wxorx.net>
* based on mach-archer-c60/C59-v1.c
* Copyright (C) 2016 Henryk Heisig <hyniu@o2.pl>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <linux/gpio.h>
#include "common.h"
#include "dev-m25p80.h"
#include "machtypes.h"
#include "pci.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include <linux/spi/spi_gpio.h>
#include <linux/spi/74x164.h>
#define ARCHER_C25_GPIO_SHIFT_OE 21 /* OE, Output Enable */
#define ARCHER_C25_GPIO_SHIFT_SER 14 /* DS, Data Serial Input */
#define ARCHER_C25_GPIO_SHIFT_SRCLK 15 /* SHCP, Shift Reg Clock Input */
#define ARCHER_C25_GPIO_SHIFT_SRCLR 19 /* MR, Master Reset */
#define ARCHER_C25_GPIO_SHIFT_RCLK 16 /* STCP, Storage Reg Clock Input */
#define ARCHER_C25_74HC_GPIO_BASE 32
#define ARCHER_C25_74HC_GPIO_LED_WAN_AMBER (ARCHER_C25_74HC_GPIO_BASE + 4)
#define ARCHER_C25_74HC_GPIO_LED_WAN_GREEN (ARCHER_C25_74HC_GPIO_BASE + 5)
#define ARCHER_C25_74HC_GPIO_LED_WLAN2 (ARCHER_C25_74HC_GPIO_BASE + 6)
#define ARCHER_C25_74HC_GPIO_LED_WLAN5 (ARCHER_C25_74HC_GPIO_BASE + 7)
#define ARCHER_C25_74HC_GPIO_LED_LAN1 (ARCHER_C25_74HC_GPIO_BASE + 0)
#define ARCHER_C25_74HC_GPIO_LED_LAN2 (ARCHER_C25_74HC_GPIO_BASE + 1)
#define ARCHER_C25_74HC_GPIO_LED_LAN3 (ARCHER_C25_74HC_GPIO_BASE + 2)
#define ARCHER_C25_74HC_GPIO_LED_LAN4 (ARCHER_C25_74HC_GPIO_BASE + 3)
#define ARCHER_C25_V1_SSR_BIT_0 0
#define ARCHER_C25_V1_SSR_BIT_1 1
#define ARCHER_C25_V1_SSR_BIT_2 2
#define ARCHER_C25_V1_SSR_BIT_3 3
#define ARCHER_C25_V1_SSR_BIT_4 4
#define ARCHER_C25_V1_SSR_BIT_5 5
#define ARCHER_C25_V1_SSR_BIT_6 6
#define ARCHER_C25_V1_SSR_BIT_7 7
#define ARCHER_C25_V1_KEYS_POLL_INTERVAL 20
#define ARCHER_C25_V1_KEYS_DEBOUNCE_INTERVAL \
(3 * ARCHER_C25_V1_KEYS_POLL_INTERVAL)
#define ARCHER_C25_V1_GPIO_BTN_RESET 1
#define ARCHER_C25_V1_GPIO_BTN_RFKILL 22
#define ARCHER_C25_V1_GPIO_LED_POWER 17
#define ARCHER_C25_V1_GPIO_LED_WPS 2
#define ARCHER_C25_V1_WMAC_CALDATA_OFFSET 0x1000
static struct spi_gpio_platform_data archer_c25_v1_spi_data = {
.sck = ARCHER_C25_GPIO_SHIFT_SRCLK,
.miso = SPI_GPIO_NO_MISO,
.mosi = ARCHER_C25_GPIO_SHIFT_SER,
.num_chipselect = 1,
};
static u8 archer_c25_v1_ssr_initdata[] = {
BIT(ARCHER_C25_V1_SSR_BIT_7) |
BIT(ARCHER_C25_V1_SSR_BIT_6) |
BIT(ARCHER_C25_V1_SSR_BIT_5) |
BIT(ARCHER_C25_V1_SSR_BIT_4) |
BIT(ARCHER_C25_V1_SSR_BIT_3) |
BIT(ARCHER_C25_V1_SSR_BIT_2) |
BIT(ARCHER_C25_V1_SSR_BIT_1)
};
static struct gen_74x164_chip_platform_data archer_c25_v1_ssr_data = {
.base = ARCHER_C25_74HC_GPIO_BASE,
.num_registers = ARRAY_SIZE(archer_c25_v1_ssr_initdata),
.init_data = archer_c25_v1_ssr_initdata,
};
static struct platform_device archer_c25_v1_spi_device = {
.name = "spi_gpio",
.id = 1,
.dev = {
.platform_data = &archer_c25_v1_spi_data,
},
};
static struct spi_board_info archer_c25_v1_spi_info[] = {
{
.bus_num = 1,
.chip_select = 0,
.max_speed_hz = 10000000,
.modalias = "74x164",
.platform_data = &archer_c25_v1_ssr_data,
.controller_data = (void *) ARCHER_C25_GPIO_SHIFT_RCLK,
},
};
static struct gpio_led archer_c25_v1_leds_gpio[] __initdata = {
{
.name = "archer-c25-v1:green:power",
.gpio = ARCHER_C25_V1_GPIO_LED_POWER,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:wps",
.gpio = ARCHER_C25_V1_GPIO_LED_WPS,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:wlan2g",
.gpio = ARCHER_C25_74HC_GPIO_LED_WLAN2,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:wlan5g",
.gpio = ARCHER_C25_74HC_GPIO_LED_WLAN5,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:lan1",
.gpio = ARCHER_C25_74HC_GPIO_LED_LAN1,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:lan2",
.gpio = ARCHER_C25_74HC_GPIO_LED_LAN2,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:lan3",
.gpio = ARCHER_C25_74HC_GPIO_LED_LAN3,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:lan4",
.gpio = ARCHER_C25_74HC_GPIO_LED_LAN4,
.active_low = 1,
}, {
.name = "archer-c25-v1:green:wan",
.gpio = ARCHER_C25_74HC_GPIO_LED_WAN_GREEN,
.active_low = 1,
}, {
.name = "archer-c25-v1:amber:wan",
.gpio = ARCHER_C25_74HC_GPIO_LED_WAN_AMBER,
.active_low = 1,
},
};
static struct gpio_keys_button archer_c25_v1_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ARCHER_C25_V1_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C25_V1_GPIO_BTN_RESET,
.active_low = 1,
}, {
.desc = "RFKILL button",
.type = EV_KEY,
.code = KEY_RFKILL,
.debounce_interval = ARCHER_C25_V1_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C25_V1_GPIO_BTN_RFKILL,
.active_low = 1,
},
};
static void __init archer_c25_v1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0008);
u8 *art = (u8 *) KSEG1ADDR(0x1f7f0000);
ath79_register_m25p80(NULL);
spi_register_board_info(archer_c25_v1_spi_info,
ARRAY_SIZE(archer_c25_v1_spi_info));
platform_device_register(&archer_c25_v1_spi_device);
gpio_request_one(ARCHER_C25_GPIO_SHIFT_OE,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"LED control");
gpio_request_one(ARCHER_C25_GPIO_SHIFT_SRCLR,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"LED reset");
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c25_v1_leds_gpio),
archer_c25_v1_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C25_V1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c25_v1_gpio_keys),
archer_c25_v1_gpio_keys);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_register_wmac(art + ARCHER_C25_V1_WMAC_CALDATA_OFFSET, mac);
ap91_pci_init(NULL, NULL);
}
MIPS_MACHINE(ATH79_MACH_ARCHER_C25_V1, "ARCHER-C25-V1", "TP-LINK Archer C25 v1",
archer_c25_v1_setup);

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target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c59-v1.c
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/*
* TP-Link Archer C58/C59 v1 board support
*
* Copyright (C) 2017 Henryk Heisig <hyniu@o2.pl>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/spi/spi_gpio.h>
#include <linux/spi/74x164.h>
#include "common.h"
#include "dev-m25p80.h"
#include "machtypes.h"
#include "pci.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#define ARCHER_C59_V1_KEYS_POLL_INTERVAL 20
#define ARCHER_C59_V1_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C59_V1_KEYS_POLL_INTERVAL)
#define ARCHER_C59_V1_GPIO_BTN_RESET 21
#define ARCHER_C59_V1_GPIO_BTN_RFKILL 2
#define ARCHER_C59_V1_GPIO_BTN_WPS 1
#define ARCHER_C59_V1_GPIO_USB_POWER 22
#define ARCHER_C59_GPIO_SHIFT_OE 16
#define ARCHER_C59_GPIO_SHIFT_SER 17
#define ARCHER_C59_GPIO_SHIFT_SRCLK 18
#define ARCHER_C59_GPIO_SHIFT_SRCLR 19
#define ARCHER_C59_GPIO_SHIFT_RCLK 20
#define ARCHER_C59_74HC_GPIO_BASE 32
#define ARCHER_C59_74HC_GPIO_LED_POWER (ARCHER_C59_74HC_GPIO_BASE + 0)
#define ARCHER_C59_74HC_GPIO_LED_WLAN2 (ARCHER_C59_74HC_GPIO_BASE + 1)
#define ARCHER_C59_74HC_GPIO_LED_WLAN5 (ARCHER_C59_74HC_GPIO_BASE + 2)
#define ARCHER_C59_74HC_GPIO_LED_LAN (ARCHER_C59_74HC_GPIO_BASE + 3)
#define ARCHER_C59_74HC_GPIO_LED_WAN_GREEN (ARCHER_C59_74HC_GPIO_BASE + 4)
#define ARCHER_C59_74HC_GPIO_LED_WAN_AMBER (ARCHER_C59_74HC_GPIO_BASE + 5)
#define ARCHER_C59_74HC_GPIO_LED_WPS (ARCHER_C59_74HC_GPIO_BASE + 6)
#define ARCHER_C59_74HC_GPIO_LED_USB (ARCHER_C59_74HC_GPIO_BASE + 7)
#define ARCHER_C59_V1_SSR_BIT_0 0
#define ARCHER_C59_V1_SSR_BIT_1 1
#define ARCHER_C59_V1_SSR_BIT_2 2
#define ARCHER_C59_V1_SSR_BIT_3 3
#define ARCHER_C59_V1_SSR_BIT_4 4
#define ARCHER_C59_V1_SSR_BIT_5 5
#define ARCHER_C59_V1_SSR_BIT_6 6
#define ARCHER_C59_V1_SSR_BIT_7 7
#define ARCHER_C59_V1_WMAC_CALDATA_OFFSET 0x1000
#define ARCHER_C59_V1_PCI_CALDATA_OFFSET 0x5000
static struct gpio_led archer_c58_v1_leds_gpio[] __initdata = {
{
.name = "archer-c58-v1:green:power",
.gpio = ARCHER_C59_74HC_GPIO_LED_POWER,
.active_low = 1,
},
{
.name = "archer-c58-v1:green:wlan2g",
.gpio = ARCHER_C59_74HC_GPIO_LED_WLAN2,
.active_low = 1,
},
{
.name = "archer-c58-v1:green:wlan5g",
.gpio = ARCHER_C59_74HC_GPIO_LED_WLAN5,
.active_low = 1,
},
{
.name = "archer-c58-v1:green:lan",
.gpio = ARCHER_C59_74HC_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "archer-c58-v1:green:wan",
.gpio = ARCHER_C59_74HC_GPIO_LED_WAN_GREEN,
.active_low = 1,
},
{
.name = "archer-c58-v1:amber:wan",
.gpio = ARCHER_C59_74HC_GPIO_LED_WAN_AMBER,
.active_low = 1,
},
{
.name = "archer-c58-v1:green:wps",
.gpio = ARCHER_C59_74HC_GPIO_LED_WPS,
.active_low = 1,
},
};
static struct gpio_led archer_c59_v1_leds_gpio[] __initdata = {
{
.name = "archer-c59-v1:green:power",
.gpio = ARCHER_C59_74HC_GPIO_LED_POWER,
.active_low = 1,
},
{
.name = "archer-c59-v1:green:wlan2g",
.gpio = ARCHER_C59_74HC_GPIO_LED_WLAN2,
.active_low = 1,
},
{
.name = "archer-c59-v1:green:wlan5g",
.gpio = ARCHER_C59_74HC_GPIO_LED_WLAN5,
.active_low = 1,
},
{
.name = "archer-c59-v1:green:lan",
.gpio = ARCHER_C59_74HC_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "archer-c59-v1:green:wan",
.gpio = ARCHER_C59_74HC_GPIO_LED_WAN_GREEN,
.active_low = 1,
},
{
.name = "archer-c59-v1:amber:wan",
.gpio = ARCHER_C59_74HC_GPIO_LED_WAN_AMBER,
.active_low = 1,
},
{
.name = "archer-c59-v1:green:wps",
.gpio = ARCHER_C59_74HC_GPIO_LED_WPS,
.active_low = 1,
},
{
.name = "archer-c59-v1:green:usb",
.gpio = ARCHER_C59_74HC_GPIO_LED_USB,
.active_low = 1,
},
};
static struct gpio_led archer_c59_v2_leds_gpio[] __initdata = {
{
.name = "archer-c59-v2:green:power",
.gpio = ARCHER_C59_74HC_GPIO_LED_POWER,
.active_low = 1,
},
{
.name = "archer-c59-v2:green:wlan2g",
.gpio = ARCHER_C59_74HC_GPIO_LED_WLAN2,
.active_low = 1,
},
{
.name = "archer-c59-v2:green:wlan5g",
.gpio = ARCHER_C59_74HC_GPIO_LED_WLAN5,
.active_low = 1,
},
{
.name = "archer-c59-v2:green:lan",
.gpio = ARCHER_C59_74HC_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "archer-c59-v2:green:wan",
.gpio = ARCHER_C59_74HC_GPIO_LED_WAN_GREEN,
.active_low = 1,
},
{
.name = "archer-c59-v2:amber:wan",
.gpio = ARCHER_C59_74HC_GPIO_LED_WAN_AMBER,
.active_low = 1,
},
{
.name = "archer-c59-v2:green:wps",
.gpio = ARCHER_C59_74HC_GPIO_LED_WPS,
.active_low = 1,
},
{
.name = "archer-c59-v2:green:usb",
.gpio = ARCHER_C59_74HC_GPIO_LED_USB,
.active_low = 1,
},
};
static struct gpio_keys_button archer_c59_v1_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ARCHER_C59_V1_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C59_V1_GPIO_BTN_RESET,
.active_low = 1,
},
{
.desc = "RFKILL button",
.type = EV_KEY,
.code = KEY_RFKILL,
.debounce_interval = ARCHER_C59_V1_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C59_V1_GPIO_BTN_RFKILL,
.active_low = 1,
},
{
.desc = "WPS button",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = ARCHER_C59_V1_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C59_V1_GPIO_BTN_WPS,
.active_low = 1,
},
};
static struct spi_gpio_platform_data archer_c59_v1_spi_data = {
.sck = ARCHER_C59_GPIO_SHIFT_SRCLK,
.miso = SPI_GPIO_NO_MISO,
.mosi = ARCHER_C59_GPIO_SHIFT_SER,
.num_chipselect = 1,
};
static u8 archer_c59_v1_ssr_initdata[] = {
BIT(ARCHER_C59_V1_SSR_BIT_7) |
BIT(ARCHER_C59_V1_SSR_BIT_6) |
BIT(ARCHER_C59_V1_SSR_BIT_5) |
BIT(ARCHER_C59_V1_SSR_BIT_4) |
BIT(ARCHER_C59_V1_SSR_BIT_3) |
BIT(ARCHER_C59_V1_SSR_BIT_2) |
BIT(ARCHER_C59_V1_SSR_BIT_1)
};
static struct gen_74x164_chip_platform_data archer_c59_v1_ssr_data = {
.base = ARCHER_C59_74HC_GPIO_BASE,
.num_registers = ARRAY_SIZE(archer_c59_v1_ssr_initdata),
.init_data = archer_c59_v1_ssr_initdata,
};
static struct platform_device archer_c59_v1_spi_device = {
.name = "spi_gpio",
.id = 1,
.dev = {
.platform_data = &archer_c59_v1_spi_data,
},
};
static struct spi_board_info archer_c59_v1_spi_info[] = {
{
.bus_num = 1,
.chip_select = 0,
.max_speed_hz = 10000000,
.modalias = "74x164",
.platform_data = &archer_c59_v1_ssr_data,
.controller_data = (void *) ARCHER_C59_GPIO_SHIFT_RCLK,
},
};
static void __init archer_c5x_v1_setup(u32 macLocation)
{
u8 *mac = (u8 *) KSEG1ADDR(macLocation);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
spi_register_board_info(archer_c59_v1_spi_info,
ARRAY_SIZE(archer_c59_v1_spi_info));
platform_device_register(&archer_c59_v1_spi_device);
ath79_register_gpio_keys_polled(-1, ARCHER_C59_V1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c59_v1_gpio_keys),
archer_c59_v1_gpio_keys);
ath79_setup_qca956x_eth_cfg(QCA956X_ETH_CFG_SW_PHY_SWAP |
QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(0);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_register_wmac(art + ARCHER_C59_V1_WMAC_CALDATA_OFFSET, mac);
ap91_pci_init(art + ARCHER_C59_V1_PCI_CALDATA_OFFSET, NULL);
ath79_register_usb();
gpio_request_one(ARCHER_C59_V1_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
gpio_request_one(ARCHER_C59_GPIO_SHIFT_OE,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"LED control");
gpio_request_one(ARCHER_C59_GPIO_SHIFT_SRCLR,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"LED reset");
}
static void __init archer_c58_v1_setup(void)
{
archer_c5x_v1_setup(0x1f010008);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c58_v1_leds_gpio),
archer_c58_v1_leds_gpio);
}
MIPS_MACHINE(ATH79_MACH_ARCHER_C58_V1, "ARCHER-C58-V1",
"TP-LINK Archer C58 v1", archer_c58_v1_setup);
static void __init archer_c59_v1_setup(void)
{
archer_c5x_v1_setup(0x1f010008);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c59_v1_leds_gpio),
archer_c59_v1_leds_gpio);
}
MIPS_MACHINE(ATH79_MACH_ARCHER_C59_V1, "ARCHER-C59-V1",
"TP-LINK Archer C59 v1", archer_c59_v1_setup);
static void __init archer_c59_v2_setup(void)
{
archer_c5x_v1_setup(0x1f030008);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c59_v2_leds_gpio),
archer_c59_v2_leds_gpio);
}
MIPS_MACHINE(ATH79_MACH_ARCHER_C59_V2, "ARCHER-C59-V2",
"TP-LINK Archer C59 v2", archer_c59_v2_setup);

225
target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c60-v1.c
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@ -1,225 +0,0 @@
/*
* TP-Link Archer C60 v1 board support
*
* Copyright (C) 2017 Henryk Heisig <hyniu@o2.pl>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <linux/gpio.h>
#include "common.h"
#include "dev-m25p80.h"
#include "machtypes.h"
#include "pci.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#define ARCHER_C60_V1_GPIO_LED_LAN 2
#define ARCHER_C60_V1_GPIO_LED_POWER 16
#define ARCHER_C60_V1_GPIO_LED_WLAN2 17
#define ARCHER_C60_V1_GPIO_LED_WLAN5 18
#define ARCHER_C60_V1_GPIO_LED_WPS 19
#define ARCHER_C60_V1_GPIO_LED_WAN_GREEN 20
#define ARCHER_C60_V1_GPIO_LED_WAN_AMBER 22
#define ARCHER_C60_V1_KEYS_POLL_INTERVAL 20
#define ARCHER_C60_V1_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C60_V1_KEYS_POLL_INTERVAL)
#define ARCHER_C60_V1_GPIO_BTN_RESET 21
#define ARCHER_C60_V1_GPIO_BTN_RFKILL 1
#define ARCHER_C60_V1_WMAC_CALDATA_OFFSET 0x1000
#define ARCHER_C60_V1_PCI_CALDATA_OFFSET 0x5000
static struct gpio_led archer_c60_v1_leds_gpio[] __initdata = {
{
.name = "archer-c60-v1:green:power",
.gpio = ARCHER_C60_V1_GPIO_LED_POWER,
.active_low = 1,
},
{
.name = "archer-c60-v1:green:wlan2g",
.gpio = ARCHER_C60_V1_GPIO_LED_WLAN2,
.active_low = 1,
},
{
.name = "archer-c60-v1:green:wlan5g",
.gpio = ARCHER_C60_V1_GPIO_LED_WLAN5,
.active_low = 1,
},
{
.name = "archer-c60-v1:green:lan",
.gpio = ARCHER_C60_V1_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "archer-c60-v1:green:wan",
.gpio = ARCHER_C60_V1_GPIO_LED_WAN_GREEN,
.active_low = 1,
},
{
.name = "archer-c60-v1:amber:wan",
.gpio = ARCHER_C60_V1_GPIO_LED_WAN_AMBER,
.active_low = 1,
},
{
.name = "archer-c60-v1:green:wps",
.gpio = ARCHER_C60_V1_GPIO_LED_WPS,
.active_low = 1,
},
};
static struct gpio_led archer_c60_v2_leds_gpio[] __initdata = {
{
.name = "archer-c60-v2:green:power",
.gpio = ARCHER_C60_V1_GPIO_LED_POWER,
.active_low = 1,
},
{
.name = "archer-c60-v2:green:wlan2g",
.gpio = ARCHER_C60_V1_GPIO_LED_WLAN2,
.active_low = 1,
},
{
.name = "archer-c60-v2:green:wlan5g",
.gpio = ARCHER_C60_V1_GPIO_LED_WLAN5,
.active_low = 1,
},
{
.name = "archer-c60-v2:green:lan",
.gpio = ARCHER_C60_V1_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "archer-c60-v2:green:wan",
.gpio = ARCHER_C60_V1_GPIO_LED_WAN_GREEN,
.active_low = 1,
},
{
.name = "archer-c60-v2:amber:wan",
.gpio = ARCHER_C60_V1_GPIO_LED_WAN_AMBER,
.active_low = 1,
},
{
.name = "archer-c60-v2:green:wps",
.gpio = ARCHER_C60_V1_GPIO_LED_WPS,
.active_low = 1,
},
};
static struct gpio_keys_button archer_c60_v1_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ARCHER_C60_V1_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C60_V1_GPIO_BTN_RESET,
.active_low = 1,
},
{
.desc = "RFKILL button",
.type = EV_KEY,
.code = KEY_RFKILL,
.debounce_interval = ARCHER_C60_V1_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C60_V1_GPIO_BTN_RFKILL,
.active_low = 1,
},
};
static void __init archer_c60_v1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f010008);
u8 *art = (u8 *) KSEG1ADDR(0x1f7f0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c60_v1_leds_gpio),
archer_c60_v1_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C60_V1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c60_v1_gpio_keys),
archer_c60_v1_gpio_keys);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_register_wmac(art + ARCHER_C60_V1_WMAC_CALDATA_OFFSET, mac);
ap91_pci_init(art + ARCHER_C60_V1_PCI_CALDATA_OFFSET, NULL);
}
MIPS_MACHINE(ATH79_MACH_ARCHER_C60_V1, "ARCHER-C60-V1",
"TP-LINK Archer C60 v1", archer_c60_v1_setup);
static void __init archer_c60_v2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fb08);
u8 *art = (u8 *) KSEG1ADDR(0x1f7f0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c60_v2_leds_gpio),
archer_c60_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C60_V1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c60_v1_gpio_keys),
archer_c60_v1_gpio_keys);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_register_wmac(art + ARCHER_C60_V1_WMAC_CALDATA_OFFSET, mac);
ap91_pci_init(art + ARCHER_C60_V1_PCI_CALDATA_OFFSET, NULL);
}
MIPS_MACHINE(ATH79_MACH_ARCHER_C60_V2, "ARCHER-C60-V2",
"TP-LINK Archer C60 v2", archer_c60_v2_setup);

260
target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7-v4.c
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@ -1,260 +0,0 @@
/*
* Atheros ARCHER_C7 reference board support
*
* Copyright (c) 2017 Felix Fietkau <nbd@nbd.name>
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <linux/ar8216_platform.h>
#include <linux/proc_fs.h>
#include <linux/gpio.h>
#include <linux/spi/spi_gpio.h>
#include <linux/spi/74x164.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-m25p80.h"
#include "machtypes.h"
#include "pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#define ARCHER_C7_GPIO_SHIFT_OE 1
#define ARCHER_C7_GPIO_SHIFT_SER 14
#define ARCHER_C7_GPIO_SHIFT_SRCLK 15
#define ARCHER_C7_GPIO_SHIFT_RCLK 16
#define ARCHER_C7_GPIO_SHIFT_SRCLR 21
#define ARCHER_C7_GPIO_BTN_RESET 5
#define ARCHER_C7_GPIO_BTN_WPS_WIFI 2
#define ARCHER_C7_GPIO_LED_WLAN5 9
#define ARCHER_C7_GPIO_LED_POWER 6
#define ARCHER_C7_GPIO_LED_USB1 7
#define ARCHER_C7_GPIO_LED_USB2 8
#define ARCHER_C7_74HC_GPIO_BASE 32
#define ARCHER_C7_GPIO_LED_WPS (ARCHER_C7_74HC_GPIO_BASE + 0)
#define ARCHER_C7_GPIO_LED_LAN1 (ARCHER_C7_74HC_GPIO_BASE + 1)
#define ARCHER_C7_GPIO_LED_LAN2 (ARCHER_C7_74HC_GPIO_BASE + 2)
#define ARCHER_C7_GPIO_LED_LAN3 (ARCHER_C7_74HC_GPIO_BASE + 3)
#define ARCHER_C7_GPIO_LED_LAN4 (ARCHER_C7_74HC_GPIO_BASE + 4)
#define ARCHER_C7_GPIO_LED_WAN_GREEN (ARCHER_C7_74HC_GPIO_BASE + 5)
#define ARCHER_C7_GPIO_LED_WAN_AMBER (ARCHER_C7_74HC_GPIO_BASE + 6)
#define ARCHER_C7_GPIO_LED_WLAN2 (ARCHER_C7_74HC_GPIO_BASE + 7)
#define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */
#define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL)
#define ARCHER_C7_MAC0_OFFSET 0
#define ARCHER_C7_MAC1_OFFSET 6
#define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000
#define ARCHER_C7_GPIO_MDC 3
#define ARCHER_C7_GPIO_MDIO 4
static struct spi_gpio_platform_data archer_c7_v4_spi_data = {
.sck = ARCHER_C7_GPIO_SHIFT_SRCLK,
.miso = SPI_GPIO_NO_MISO,
.mosi = ARCHER_C7_GPIO_SHIFT_SER,
.num_chipselect = 1,
};
static u8 archer_c7_v4_ssr_initdata = 0xff;
static struct gen_74x164_chip_platform_data archer_c7_v4_ssr_data = {
.base = ARCHER_C7_74HC_GPIO_BASE,
.num_registers = 1,
.init_data = &archer_c7_v4_ssr_initdata,
};
static struct platform_device archer_c7_v4_spi_device = {
.name = "spi_gpio",
.id = 1,
.dev = {
.platform_data = &archer_c7_v4_spi_data,
},
};
static struct spi_board_info archer_c7_v4_spi_info[] = {
{
.bus_num = 1,
.chip_select = 0,
.max_speed_hz = 10000000,
.modalias = "74x164",
.platform_data = &archer_c7_v4_ssr_data,
.controller_data = (void *) ARCHER_C7_GPIO_SHIFT_RCLK,
},
};
static struct gpio_led archer_c7_v4_leds_gpio[] __initdata = {
{
.name = "archer-c7-v4:green:power",
.gpio = ARCHER_C7_GPIO_LED_POWER,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:wps",
.gpio = ARCHER_C7_GPIO_LED_WPS,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:wlan2g",
.gpio = ARCHER_C7_GPIO_LED_WLAN2,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:wlan5g",
.gpio = ARCHER_C7_GPIO_LED_WLAN5,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:lan1",
.gpio = ARCHER_C7_GPIO_LED_LAN1,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:lan2",
.gpio = ARCHER_C7_GPIO_LED_LAN2,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:lan3",
.gpio = ARCHER_C7_GPIO_LED_LAN3,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:lan4",
.gpio = ARCHER_C7_GPIO_LED_LAN4,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:wan",
.gpio = ARCHER_C7_GPIO_LED_WAN_GREEN,
.active_low = 1,
}, {
.name = "archer-c7-v4:amber:wan",
.gpio = ARCHER_C7_GPIO_LED_WAN_AMBER,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:usb1",
.gpio = ARCHER_C7_GPIO_LED_USB1,
.active_low = 1,
}, {
.name = "archer-c7-v4:green:usb2",
.gpio = ARCHER_C7_GPIO_LED_USB2,
.active_low = 1,
},
};
static struct gpio_keys_button archer_c7_v4_gpio_keys[] __initdata = {
{
.desc = "WPS and WIFI button",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C7_GPIO_BTN_WPS_WIFI,
.active_low = 1,
},
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
.gpio = ARCHER_C7_GPIO_BTN_RESET,
.active_low = 1,
},
};
static struct ar8327_pad_cfg archer_c7_v4_ar8337_pad0_cfg = {
.mode = AR8327_PAD_MAC_SGMII,
.sgmii_delay_en = true,
};
static struct ar8327_platform_data archer_c7_v4_ar8337_data = {
.pad0_cfg = &archer_c7_v4_ar8337_pad0_cfg,
.port0_cfg = {
.force_link = 1,
.speed = AR8327_PORT_SPEED_1000,
.duplex = 1,
.txpause = 1,
.rxpause = 1,
},
};
static struct mdio_board_info archer_c7_v4_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.mdio_addr = 0,
.platform_data = &archer_c7_v4_ar8337_data,
},
};
static void __init archer_c7_v4_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1ff00008);
ath79_register_m25p80(NULL);
spi_register_board_info(archer_c7_v4_spi_info,
ARRAY_SIZE(archer_c7_v4_spi_info));
platform_device_register(&archer_c7_v4_spi_device);
gpio_request_one(ARCHER_C7_GPIO_SHIFT_OE,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"LED control");
gpio_request_one(ARCHER_C7_GPIO_SHIFT_SRCLR,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"LED reset");
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_v4_leds_gpio),
archer_c7_v4_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c7_v4_gpio_keys),
archer_c7_v4_gpio_keys);
ath79_register_usb();
ath79_gpio_output_select(ARCHER_C7_GPIO_MDC, QCA956X_GPIO_OUT_MUX_GE0_MDC);
ath79_gpio_output_select(ARCHER_C7_GPIO_MDIO, QCA956X_GPIO_OUT_MUX_GE0_MDO);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(archer_c7_v4_mdio0_info,
ARRAY_SIZE(archer_c7_v4_mdio0_info));
ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, mac);
ath79_register_pci();
/* GMAC0 is connected to an AR8337 switch */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
}
MIPS_MACHINE(ATH79_MACH_ARCHER_C7_V4, "ARCHER-C7-V4", "TP-LINK Archer C7 v4",
archer_c7_v4_setup);

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