bcm53xx: use more upsteam DT patches from 5.16 / 5.17
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
(cherry picked from commit 5901917b93)
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Rafał Miłecki
parent
37d535129b
commit
35e470ad0a
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@ -0,0 +1,104 @@
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From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Thu, 28 Oct 2021 09:03:44 +0200
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Subject: [PATCH] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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replaces the bit-banged i2c-gpio provided i2c functionality
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with the hardware in the SoC.
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During review of the MR32, Florian Fainelli pointed out that the
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SoC has a real I2C-controller. Furthermore, the connected pins
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(SDA and SCL) would line up perfectly for use. Back then I couldn't
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get it working though and I left it with i2c-gpio (which worked).
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Now we know the reason: the interrupt was incorrectly specified.
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(Hence, this patch depends on Florian Fainelli's
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"ARM: dts: BCM5301X: Fix I2C controller interrupt" patch).
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Cc: Florian Fainelli <f.fainelli@gmail.com>
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Cc: Rafał Miłecki <zajec5@gmail.com>
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Cc: Matthew Hagan <mnhagan88@gmail.com>
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------
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1 file changed, 28 insertions(+), 34 deletions(-)
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--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
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+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
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@@ -84,40 +84,6 @@
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max-brightness = <255>;
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};
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};
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-
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- i2c {
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- /*
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- * The platform provided I2C does not budge.
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- * This is a replacement until I can figure
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- * out what are the missing bits...
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- */
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-
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- compatible = "i2c-gpio";
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- sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
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- scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
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- i2c-gpio,delay-us = <10>; /* close to 100 kHz */
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- current_sense: ina219@45 {
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- compatible = "ti,ina219";
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- reg = <0x45>;
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- shunt-resistor = <60000>; /* = 60 mOhms */
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- };
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-
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- eeprom: eeprom@50 {
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- compatible = "atmel,24c64";
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- reg = <0x50>;
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- pagesize = <32>;
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- read-only;
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- #address-cells = <1>;
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- #size-cells = <1>;
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-
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- mac_address: mac-address@66 {
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- reg = <0x66 0x6>;
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- };
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- };
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- };
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};
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&uart0 {
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@@ -228,3 +194,31 @@
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};
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};
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};
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinmux_i2c>;
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+
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+ clock-frequency = <100000>;
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+
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+ current_sense: ina219@45 {
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+ compatible = "ti,ina219";
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+ reg = <0x45>;
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+ shunt-resistor = <60000>; /* = 60 mOhms */
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+ };
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+
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+ eeprom: eeprom@50 {
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+ compatible = "atmel,24c64";
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+ reg = <0x50>;
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+ pagesize = <32>;
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+ read-only;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ mac_address: mac-address@66 {
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+ reg = <0x66 0x6>;
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+ };
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+ };
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+};
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@ -0,0 +1,60 @@
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From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 29 Oct 2021 18:05:23 +0200
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Subject: [PATCH] ARM: dts: BCM5301X: update CRU block description
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This describes CRU in a way matching documentation and fixes:
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arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
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From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++----
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1 file changed, 9 insertions(+), 4 deletions(-)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -423,14 +423,14 @@
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#address-cells = <1>;
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#size-cells = <1>;
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- cru@100 {
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- compatible = "simple-bus";
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+ cru-bus@100 {
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+ compatible = "brcm,ns-cru", "simple-mfd";
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reg = <0x100 0x1a4>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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- lcpll0: lcpll0@100 {
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+ lcpll0: clock-controller@100 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-lcpll0";
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reg = <0x100 0x14>;
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@@ -439,7 +439,7 @@
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"sdio", "ddr_phy";
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};
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- genpll: genpll@140 {
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+ genpll: clock-controller@140 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-genpll";
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reg = <0x140 0x24>;
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@@ -450,6 +450,11 @@
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"sata1", "sata2";
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};
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+ syscon@180 {
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+ compatible = "brcm,cru-clkset", "syscon";
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+ reg = <0x180 0x4>;
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+ };
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+
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pinctrl: pin-controller@1c0 {
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compatible = "brcm,bcm4708-pinmux";
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reg = <0x1c0 0x24>;
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