imx6: add 4.4 support

Build and boot tested on the following hardware: * GW54xx * GW53xx * GW52xx * GW51xx * GW552x * GW551x Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com> SVN-Revision: 48248
2016-01-15 15:18:18 +00:00 · 2016-01-15 15:18:18 +00:00 · 321823ba05
parent 82c5e2c497
commit 321823ba05
18 changed files with 2922 additions and 0 deletions
--- a/target/linux/imx6/config-4.4
+++ b/target/linux/imx6/config-4.4
@ -0,0 +1,405 @@
+CONFIG_AHCI_IMX=y
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_ARM=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_IMX6Q_CPUFREQ=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+# CONFIG_ATA_SFF is not set
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_XZ=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_IMX_UART_PORT=1
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DTC=y
+# CONFIG_DW_DMAC_PCI is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+CONFIG_FEC=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_FSL_PQ_MDIO is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTRACE=y
+# CONFIG_FTRACE_SYSCALLS is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IMX_ANATOP=y
+CONFIG_HAVE_IMX_GPC=y
+CONFIG_HAVE_IMX_MMDC=y
+CONFIG_HAVE_IMX_SRC=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_IMX=y
+CONFIG_IMX2_WDT=y
+CONFIG_IMX_DMA=y
+CONFIG_IMX_SDMA=y
+CONFIG_IMX_THERMAL=y
+# CONFIG_IMX_WEIM is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IOMMU_HELPER=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICREL_PHY=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+# CONFIG_MTD_PHYSMAP_OF is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_MX3_IPU is not set
+CONFIG_MXS_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_IMX6=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX=y
+CONFIG_PINCTRL_IMX6Q=y
+CONFIG_PINCTRL_IMX6SL=y
+CONFIG_PINCTRL_IMX6SX=y
+CONFIG_PINCTRL_IMX6UL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+# CONFIG_PL310_ERRATA_753970 is not set
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PM_OPP=y
+CONFIG_PPS=y
+# CONFIG_PROBE_EVENTS is not set
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_MXC is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+CONFIG_SOC_IMX6=y
+CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_IMX6SX=y
+CONFIG_SOC_IMX6UL=y
+# CONFIG_SOC_IMX7D is not set
+# CONFIG_SOC_LS1021A is not set
+# CONFIG_SOC_VF610 is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_MASTER=y
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_STMP_DEVICE=y
+# CONFIG_SUNXI_SRAM is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TRACING_EVENTS_GPIO=y
+CONFIG_TREE_RCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_XZ=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+# CONFIG_USB_MXS_PHY is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/imx6/files-4.4/drivers/net/phy/gw16083.c
+++ b/target/linux/imx6/files-4.4/drivers/net/phy/gw16083.c
--- a/target/linux/imx6/files-4.4/drivers/net/phy/gw16083.h
+++ b/target/linux/imx6/files-4.4/drivers/net/phy/gw16083.h
@ -0,0 +1,123 @@
+/*
+ * drivers/net/phy/mv88e6176.h
+ *
+ * Driver for Marvell Switch
+ *
+ * Author: Tim Harvey
+ *
+ * Copyright (c) 2014 Tim Harvey <tharvey@gateworks.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _GW16083_H_
+#define _GW16083_H_
+
+#define MII_MARVELL_PHY_PAGE		22
+
+/*
+ * I2C Addresses
+ */
+#define GW16083_I2C_ADDR_SFP1		0x50
+#define GW16083_I2C_ADDR_SFP2		0x51
+#define GW16083_I2C_ADDR_EEPROM		0x52
+#define GW16083_I2C_ADDR_PCA9543	0x70
+
+/*
+ * MV88E1111 PHY Registers
+ */
+enum {
+	MII_M1111_PHY_CONTROL		= 0,
+	MII_M1111_PHY_STATUS 		= 1,
+	MII_M1111_PHY_IDENT0		= 2,
+	MII_M1111_PHY_IDENT1		= 3,
+	MII_M1111_PHY_EXT_CR		= 20,
+	MII_M1111_PHY_LED_CONTROL	= 24,
+	MII_M1111_PHY_EXT_SR		= 27,
+};
+
+#define MII_M1111_PHY_ID_MASK		0xfffffff0
+#define MII_M1111_PHY_ID		0x01410cc0
+
+#define MII_M1111_PHY_CONTROL_RESET	(1 << 15)
+#define MII_M1111_PHY_LED_DIRECT	0x4100
+#define MII_M1111_PHY_LED_PULSE_STR	0x4111
+#define MII_M1111_PHY_LED_COMBINE	0x411c
+#define MII_M1111_RX_DELAY		0x80
+#define MII_M1111_TX_DELAY		0x2
+
+/*
+ * MV88E6176 Switch Registers
+ */
+
+/* PHY Addrs */
+#define MV_BASE		0x10
+#define MV_GLOBAL1	0x1b
+#define MV_GLOBAL2	0x1c
+#define MV_GLOBAL3	0x1d
+
+/* Global2 Registers */
+enum {
+	MV_SMI_PHY_COMMAND	= 0x18,
+	MV_SMI_PHY_DATA		= 0x19,
+	MV_SCRATCH_MISC		= 0x1A,
+};
+
+/* Scratch And Misc Reg offsets */
+enum {
+	MV_GPIO_MODE		= 0x60,
+	MV_GPIO_DIR		= 0x62,
+	MV_GPIO_DATA		= 0x64,
+	MV_GPIO76_CNTL		= 0x6B,
+	MV_GPIO54_CNTL		= 0x6A,
+	MV_GPIO32_CNTL		= 0x69,
+	MV_GPIO10_CNTL		= 0x68,
+	MV_CONFIG0		= 0x70,
+	MV_CONFIG1		= 0x71,
+	MV_CONFIG2		= 0x72,
+	MV_CONFIG3		= 0x73,
+};
+
+/* PHY Registers */
+enum {
+	MV_PHY_CONTROL      = 0x00,
+	MV_PHY_STATUS       = 0x01,
+	MV_PHY_IDENT0       = 0x02,
+	MV_PHY_IDENT1       = 0x03,
+	MV_PHY_ANEG         = 0x04,
+	MV_PHY_LINK_ABILITY = 0x05,
+	MV_PHY_ANEG_EXPAND  = 0x06,
+	MV_PHY_XMIT_NEXTP   = 0x07,
+	MV_PHY_LINK_NEXTP   = 0x08,
+	MV_PHY_CONTROL1     = 0x10,
+	MV_PHY_STATUS1      = 0x11,
+	MV_PHY_INTR_EN      = 0x12,
+};
+
+/* Port Registers */
+enum {
+	MV_PORT_STATUS      	= 0x00,
+	MV_PORT_PHYS_CONTROL	= 0x01,
+	MV_PORT_IDENT       	= 0x03,
+	MV_PORT_CONTROL     	= 0x04,
+	MV_PORT_VLANMAP     	= 0x06,
+	MV_PORT_ASSOC       	= 0x0b,
+	MV_PORT_RXCOUNT     	= 0x10,
+	MV_PORT_TXCOUNT     	= 0x11,
+};
+
+#define SMIBUSY		(1<<15)
+#define SMIMODE22	(1<<12)
+#define SMIOP_READ	(2<<10)
+#define SMIOP_WRITE	(1<<10)
+#define DEVADDR		5
+#define REGADDR		0
+
+#define MV_IDENT_MASK		0x0000fff0
+#define MV_IDENT_VALUE		0x00001760
+
+#endif /* _GW16083_H_ */
--- a/target/linux/imx6/patches-4.4/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch
+++ b/target/linux/imx6/patches-4.4/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch
@ -0,0 +1,26 @@
+From 57b82d9e79d77442bae3d2c13b98ceccb39fe5e2 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Thu, 5 Nov 2015 10:49:31 -0800
+Subject: [PATCH 1/3] ARM: dts: imx: ventana: set GW54xx PMIC swbst regulator
+ as always-on
+
+The GW54xx PMIC swbst regulator is used for LVDS power, CANbus xceiver
+and HDMI DDC and is enabled by the bootloader. Set the regulator to
+always-on so that Linux doesn't turn it off thinking its not needed.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+---
+ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -260,6 +260,8 @@
+ 			swbst_reg: swbst {
+ 				regulator-min-microvolt = <5000000>;
+ 				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on;
+ 			};
+ 
+ 			snvs_reg: vsnvs {
--- a/target/linux/imx6/patches-4.4/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch
+++ b/target/linux/imx6/patches-4.4/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch
@ -0,0 +1,33 @@
+From 473d0353979db3673a7aa365265ba9b00decd414 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Thu, 5 Nov 2015 10:52:53 -0800
+Subject: [PATCH 2/3] ARM: dts: imx: ventana: fix GW53xx/GW54xx lvds channel
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+---
+ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 2 +-
+ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -247,7 +247,7 @@
+ &ldb {
+ 	status = "okay";
+ 
+-	lvds-channel@1 {
+	lvds-channel@0 {
+ 		fsl,data-mapping = "spwg";
+ 		fsl,data-width = <18>;
+ 		status = "okay";
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -338,7 +338,7 @@
+ &ldb {
+ 	status = "okay";
+ 
+-	lvds-channel@1 {
+	lvds-channel@0 {
+ 		fsl,data-mapping = "spwg";
+ 		fsl,data-width = <18>;
+ 		status = "okay";
--- a/target/linux/imx6/patches-4.4/037-ARM-dts-imx-ventana-Allow-HDMI-and-LVDS-to-work-simultaneously.patch
+++ b/target/linux/imx6/patches-4.4/037-ARM-dts-imx-ventana-Allow-HDMI-and-LVDS-to-work-simultaneously.patch
@ -0,0 +1,70 @@
+From d86b202436b6f3111c4c37b8701daa0764d2ca55 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Thu, 5 Nov 2015 11:10:00 -0800
+Subject: [PATCH 3/3] ARM: dts: imx: ventana: Allow HDMI and LVDS to work
+ simultaneously
+
+Currently it is not possible to have HDMI and LVDS working simultaneously,
+because both ports try to use PLL5.
+
+Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
+driven from independent sources.
+
+With this change the LDB pixel clock goes to 68.57 MHz, which is still
+within the valid range for the displays supported by the Ventana boards.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+---
+ arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 7 +++++++
+ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 7 +++++++
+ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 7 +++++++
+ 3 files changed, 21 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -151,6 +151,13 @@
+ 	status = "okay";
+ };
+ 
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+	                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+ &fec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_enet>;
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -152,6 +152,13 @@
+ 	status = "okay";
+ };
+ 
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+	                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+ &fec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_enet>;
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -142,6 +142,13 @@
+ 	status = "okay";
+ };
+ 
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+	                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+ &fec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_enet>;
--- a/target/linux/imx6/patches-4.4/040-ARM-dts-imx-ventana-add-pwm-nodes.patch
+++ b/target/linux/imx6/patches-4.4/040-ARM-dts-imx-ventana-add-pwm-nodes.patch
@ -0,0 +1,264 @@
+--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+@@ -174,6 +174,24 @@
+ 	status = "okay";
+ };
+ 
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+	status = "disabled";
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+	status = "disabled";
+};
+
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_uart1>;
+@@ -294,6 +312,24 @@
+ 			>;
+ 		};
+ 
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm4: pwm4grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
+			>;
+		};
+
+ 		pinctrl_uart1: uart1grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -282,6 +282,18 @@
+ 	status = "okay";
+ };
+ 
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+	status = "disabled";
+};
+
+ &pwm4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_pwm4>;
+@@ -436,6 +448,18 @@
+ 			>;
+ 		};
+ 
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+ 		pinctrl_pwm4: pwm4grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -287,6 +287,18 @@
+ 	};
+ };
+ 
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+	status = "disabled";
+};
+
+ &pwm4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_pwm4>;
+@@ -442,6 +454,18 @@
+ 			>;
+ 		};
+ 
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+ 		pinctrl_pwm4: pwm4grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -378,6 +378,24 @@
+ 	};
+ };
+ 
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+	status = "disabled";
+};
+
+ &pwm4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_pwm4>;
+@@ -537,6 +555,24 @@
+ 			>;
+ 		};
+ 
+		pinctrl_pwm1: pwm1grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+ 		pinctrl_pwm4: pwm4grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+@@ -198,6 +198,18 @@
+ 	status = "okay";
+ };
+ 
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+	status = "disabled";
+};
+
+ &ssi1 {
+ 	status = "okay";
+ };
+@@ -290,6 +302,18 @@
+ 			>;
+ 		};
+ 
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+ 		pinctrl_uart2: uart2grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+@@ -164,6 +164,18 @@
+ 	status = "okay";
+ };
+ 
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+	status = "disabled";
+};
+
+ &uart2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_uart2>;
+@@ -242,6 +254,18 @@
+ 			>;
+ 		};
+ 
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+ 		pinctrl_uart2: uart2grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
--- a/target/linux/imx6/patches-4.4/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch
+++ b/target/linux/imx6/patches-4.4/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch
@ -0,0 +1,33 @@
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -158,6 +158,14 @@
+ 	                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ };
+ 
+&ecspi3 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi3>;
+	status = "okay";
+};
+
+ &fec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_enet>;
+@@ -357,6 +365,15 @@
+ 			>;
+ 		};
+ 
+		pinctrl_ecspi3: escpi3grp {
+			fsl,pins = <
+				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
+				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
+				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
+				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x100b1
+			>;
+		};
+
+ 		pinctrl_enet: enetgrp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
--- a/target/linux/imx6/patches-4.4/042-ARM-dts-imx-ventana-fix-PWM-pinmux-for-Ventana-boards.patch
+++ b/target/linux/imx6/patches-4.4/042-ARM-dts-imx-ventana-fix-PWM-pinmux-for-Ventana-boards.patch
@ -0,0 +1,61 @@
+commit 3371600cc36d2a6c19cc985660a21c6830f7e7cd
+Author: Tim Harvey <tharvey@gateworks.com>
+Date:   Thu Jan 7 09:03:03 2016 -0800
+
+    ARM: dts: imx: ventana: fix PWM pinmux for Ventana boards
+    
+    Fix some invalid pwm pinmux configurations.
+    
+    Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+
+--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+@@ -320,13 +320,13 @@
+ 
+ 		pinctrl_pwm3: pwm3grp {
+ 			fsl,pins = <
+-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+ 			>;
+ 		};
+ 
+ 		pinctrl_pwm4: pwm4grp {
+ 			fsl,pins = <
+-				MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+ 			>;
+ 		};
+ 
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -473,7 +473,7 @@
+ 
+ 		pinctrl_pwm3: pwm3grp {
+ 			fsl,pins = <
+-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+ 			>;
+ 		};
+ 
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -462,7 +462,7 @@
+ 
+ 		pinctrl_pwm3: pwm3grp {
+ 			fsl,pins = <
+-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+ 			>;
+ 		};
+ 
+--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+@@ -262,7 +262,7 @@
+ 
+ 		pinctrl_pwm3: pwm3grp {
+ 			fsl,pins = <
+-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+ 			>;
+ 		};
+ 
--- a/target/linux/imx6/patches-4.4/100-bootargs.patch
+++ b/target/linux/imx6/patches-4.4/100-bootargs.patch
@ -0,0 +1,11 @@
+--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
+@@ -19,4 +19,8 @@
+ 	memory {
+ 		reg = <0x10000000 0x40000000>;
+ 	};
+
+	chosen {
+		bootargs = "console=ttymxc0,115200";
+	};
+ };
--- a/target/linux/imx6/patches-4.4/202-net-igb-add-i210-i211-support-for-phy-read-write.patch
+++ b/target/linux/imx6/patches-4.4/202-net-igb-add-i210-i211-support-for-phy-read-write.patch
@ -0,0 +1,129 @@
+Author: Tim Harvey <tharvey@gateworks.com>
+Date:   Thu May 15 00:12:26 2014 -0700
+
+    net: igb: add i210/i211 support for phy read/write
+    
+    The i210/i211 uses the MDICNFG register for the phy address instead of the
+    MDIC register.
+    
+    Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+
+--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
+@@ -129,7 +129,7 @@ out:
+ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
+ {
+ 	struct e1000_phy_info *phy = &hw->phy;
+-	u32 i, mdic = 0;
+	u32 i, mdicnfg, mdic = 0;
+ 	s32 ret_val = 0;
+ 
+ 	if (offset > MAX_PHY_REG_ADDRESS) {
+@@ -142,11 +142,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+ 	 * Control register.  The MAC will take care of interfacing with the
+ 	 * PHY to retrieve the desired data.
+ 	 */
+-	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+-		(phy->addr << E1000_MDIC_PHY_SHIFT) |
+-		(E1000_MDIC_OP_READ));
+	switch (hw->mac.type) {
+	case e1000_i210:
+	case e1000_i211:
+		mdicnfg = rd32(E1000_MDICNFG);
+		mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+		mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+		wr32(E1000_MDICNFG, mdicnfg);
+		mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+			(E1000_MDIC_OP_READ));
+		break;
+	default:
+		mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+			(phy->addr << E1000_MDIC_PHY_SHIFT) |
+			(E1000_MDIC_OP_READ));
+		break;
+	}
+ 
+ 	wr32(E1000_MDIC, mdic);
+	wrfl();
+ 
+ 	/* Poll the ready bit to see if the MDI read completed
+ 	 * Increasing the time out as testing showed failures with
+@@ -171,6 +185,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+ 	*data = (u16) mdic;
+ 
+ out:
+	switch (hw->mac.type) {
+		/* restore MDICNFG to have phy's addr */
+		case e1000_i210:
+		case e1000_i211:
+			mdicnfg = rd32(E1000_MDICNFG);
+			mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+			mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
+			wr32(E1000_MDICNFG, mdicnfg);
+			break;
+		default:
+			break;
+	}
+ 	return ret_val;
+ }
+ 
+@@ -185,7 +211,7 @@ out:
+ s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
+ {
+ 	struct e1000_phy_info *phy = &hw->phy;
+-	u32 i, mdic = 0;
+	u32 i, mdicnfg, mdic = 0;
+ 	s32 ret_val = 0;
+ 
+ 	if (offset > MAX_PHY_REG_ADDRESS) {
+@@ -198,12 +224,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+ 	 * Control register.  The MAC will take care of interfacing with the
+ 	 * PHY to retrieve the desired data.
+ 	 */
+-	mdic = (((u32)data) |
+-		(offset << E1000_MDIC_REG_SHIFT) |
+-		(phy->addr << E1000_MDIC_PHY_SHIFT) |
+-		(E1000_MDIC_OP_WRITE));
+	switch (hw->mac.type) {
+		case e1000_i210:
+		case e1000_i211:
+			mdicnfg = rd32(E1000_MDICNFG);
+			mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+			mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+			wr32(E1000_MDICNFG, mdicnfg);
+			mdic = (((u32)data) |
+				(offset << E1000_MDIC_REG_SHIFT) |
+				(E1000_MDIC_OP_WRITE));
+			break;
+		default:
+			mdic = (((u32)data) |
+				(offset << E1000_MDIC_REG_SHIFT) |
+				(phy->addr << E1000_MDIC_PHY_SHIFT) |
+				(E1000_MDIC_OP_WRITE));
+			break;
+	}
+ 
+ 	wr32(E1000_MDIC, mdic);
+	wrfl();
+ 
+ 	/* Poll the ready bit to see if the MDI read completed
+ 	 * Increasing the time out as testing showed failures with
+@@ -227,6 +268,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+ 	}
+ 
+ out:
+	switch (hw->mac.type) {
+		/* restore MDICNFG to have phy's addr */
+		case e1000_i210:
+		case e1000_i211:
+			mdicnfg = rd32(E1000_MDICNFG);
+			mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+			mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
+			wr32(E1000_MDICNFG, mdicnfg);
+			break;
+		default:
+			break;
+	}
+ 	return ret_val;
+ }
+ 
--- a/target/linux/imx6/patches-4.4/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch
+++ b/target/linux/imx6/patches-4.4/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch
@ -0,0 +1,260 @@
+From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Thu, 15 May 2014 00:29:18 -0700
+Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr
+
+Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
+The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
+to this function.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+---
+ drivers/net/ethernet/intel/igb/e1000_82575.c |  4 +-
+ drivers/net/ethernet/intel/igb/e1000_phy.c   | 74 +++++++++++++++++++---------
+ drivers/net/ethernet/intel/igb/e1000_phy.h   |  6 ++-
+ 3 files changed, 58 insertions(+), 26 deletions(-)
+
+--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
+@@ -2153,7 +2153,7 @@ static s32 igb_read_phy_reg_82580(struct
+ 	if (ret_val)
+ 		goto out;
+ 
+-	ret_val = igb_read_phy_reg_mdic(hw, offset, data);
+	ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
+ 
+ 	hw->phy.ops.release(hw);
+ 
+@@ -2178,7 +2178,7 @@ static s32 igb_write_phy_reg_82580(struc
+ 	if (ret_val)
+ 		goto out;
+ 
+-	ret_val = igb_write_phy_reg_mdic(hw, offset, data);
+	ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
+ 
+ 	hw->phy.ops.release(hw);
+ 
+--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
+@@ -126,9 +126,8 @@ out:
+  *  Reads the MDI control regsiter in the PHY at offset and stores the
+  *  information read to data.
+  **/
+-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
+ {
+-	struct e1000_phy_info *phy = &hw->phy;
+ 	u32 i, mdicnfg, mdic = 0;
+ 	s32 ret_val = 0;
+ 
+@@ -147,14 +146,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+ 	case e1000_i211:
+ 		mdicnfg = rd32(E1000_MDICNFG);
+ 		mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+-		mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+		mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
+ 		wr32(E1000_MDICNFG, mdicnfg);
+ 		mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+ 			(E1000_MDIC_OP_READ));
+ 		break;
+ 	default:
+ 		mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+-			(phy->addr << E1000_MDIC_PHY_SHIFT) |
+			(addr << E1000_MDIC_PHY_SHIFT) |
+ 			(E1000_MDIC_OP_READ));
+ 		break;
+ 	}
+@@ -208,9 +207,8 @@ out:
+  *
+  *  Writes data to MDI control register in the PHY at offset.
+  **/
+-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
+ {
+-	struct e1000_phy_info *phy = &hw->phy;
+ 	u32 i, mdicnfg, mdic = 0;
+ 	s32 ret_val = 0;
+ 
+@@ -229,7 +227,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+ 		case e1000_i211:
+ 			mdicnfg = rd32(E1000_MDICNFG);
+ 			mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+-			mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+			mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
+ 			wr32(E1000_MDICNFG, mdicnfg);
+ 			mdic = (((u32)data) |
+ 				(offset << E1000_MDIC_REG_SHIFT) |
+@@ -238,7 +236,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+ 		default:
+ 			mdic = (((u32)data) |
+ 				(offset << E1000_MDIC_REG_SHIFT) |
+-				(phy->addr << E1000_MDIC_PHY_SHIFT) |
+				(addr << E1000_MDIC_PHY_SHIFT) |
+ 				(E1000_MDIC_OP_WRITE));
+ 			break;
+ 	}
+@@ -458,7 +456,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
+ 		goto out;
+ 
+ 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
+-		ret_val = igb_write_phy_reg_mdic(hw,
+		ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
+ 						 IGP01E1000_PHY_PAGE_SELECT,
+ 						 (u16)offset);
+ 		if (ret_val) {
+@@ -467,8 +465,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
+ 		}
+ 	}
+ 
+-	ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+-					data);
+	ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
+					MAX_PHY_REG_ADDRESS & offset, data);
+ 
+ 	hw->phy.ops.release(hw);
+ 
+@@ -497,7 +495,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
+ 		goto out;
+ 
+ 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
+-		ret_val = igb_write_phy_reg_mdic(hw,
+		ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
+ 						 IGP01E1000_PHY_PAGE_SELECT,
+ 						 (u16)offset);
+ 		if (ret_val) {
+@@ -506,8 +504,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
+ 		}
+ 	}
+ 
+-	ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+-					 data);
+	ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
+					 MAX_PHY_REG_ADDRESS & offset, data);
+ 
+ 	hw->phy.ops.release(hw);
+ 
+@@ -2547,8 +2545,9 @@ out:
+ }
+ 
+ /**
+- *  igb_write_phy_reg_gs40g - Write GS40G PHY register
+ *  igb_write_reg_gs40g - Write GS40G PHY register
+  *  @hw: pointer to the HW structure
+ *  @addr: phy address to write to
+  *  @offset: lower half is register offset to write to
+  *     upper half is page to use.
+  *  @data: data to write at register offset
+@@ -2556,7 +2555,7 @@ out:
+  *  Acquires semaphore, if necessary, then writes the data to PHY register
+  *  at the offset.  Release any acquired semaphores before exiting.
+  **/
+-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
+ {
+ 	s32 ret_val;
+ 	u16 page = offset >> GS40G_PAGE_SHIFT;
+@@ -2566,10 +2565,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
+ 	if (ret_val)
+ 		return ret_val;
+ 
+-	ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
+	ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
+ 	if (ret_val)
+ 		goto release;
+-	ret_val = igb_write_phy_reg_mdic(hw, offset, data);
+	ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
+ 
+ release:
+ 	hw->phy.ops.release(hw);
+@@ -2577,8 +2576,24 @@ release:
+ }
+ 
+ /**
+- *  igb_read_phy_reg_gs40g - Read GS40G  PHY register
+ *  igb_write_phy_reg_gs40g - Write GS40G PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: lower half is register offset to write to
+ *     upper half is page to use.
+ *  @data: data to write at register offset
+ *
+ *  Acquires semaphore, if necessary, then writes the data to PHY register
+ *  at the offset.  Release any acquired semaphores before exiting.
+ **/
+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
+{
+	return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
+}
+
+/**
+ *  igb_read_reg_gs40g - Read GS40G  PHY register
+  *  @hw: pointer to the HW structure
+ *  @addr: phy address to read from
+  *  @offset: lower half is register offset to read to
+  *     upper half is page to use.
+  *  @data: data to read at register offset
+@@ -2586,7 +2601,7 @@ release:
+  *  Acquires semaphore, if necessary, then reads the data in the PHY register
+  *  at the offset.  Release any acquired semaphores before exiting.
+  **/
+-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
+ {
+ 	s32 ret_val;
+ 	u16 page = offset >> GS40G_PAGE_SHIFT;
+@@ -2596,10 +2611,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
+ 	if (ret_val)
+ 		return ret_val;
+ 
+-	ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
+	ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
+ 	if (ret_val)
+ 		goto release;
+-	ret_val = igb_read_phy_reg_mdic(hw, offset, data);
+	ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
+ 
+ release:
+ 	hw->phy.ops.release(hw);
+@@ -2607,6 +2622,21 @@ release:
+ }
+ 
+ /**
+ *  igb_read_phy_reg_gs40g - Read GS40G  PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: lower half is register offset to read to
+ *     upper half is page to use.
+ *  @data: data to read at register offset
+ *
+ *  Acquires semaphore, if necessary, then reads the data in the PHY register
+ *  at the offset.  Release any acquired semaphores before exiting.
+ **/
+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
+{
+	return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
+}
+
+/**
+  *  igb_set_master_slave_mode - Setup PHY for Master/slave mode
+  *  @hw: pointer to the HW structure
+  *
+--- a/drivers/net/ethernet/intel/igb/e1000_phy.h
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
+@@ -62,8 +62,8 @@ void igb_power_up_phy_copper(struct e100
+ void igb_power_down_phy_copper(struct e1000_hw *hw);
+ s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
+ s32  igb_initialize_M88E1512_phy(struct e1000_hw *hw);
+-s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
+-s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
+s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
+s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
+ s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
+ s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
+ s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
+@@ -73,6 +73,8 @@ s32  igb_phy_force_speed_duplex_82580(st
+ s32  igb_get_cable_length_82580(struct e1000_hw *hw);
+ s32  igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
+ s32  igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
+s32  igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
+s32  igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
+ s32  igb_check_polarity_m88(struct e1000_hw *hw);
+ 
+ /* IGP01E1000 Specific Registers */
--- a/target/linux/imx6/patches-4.4/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch
+++ b/target/linux/imx6/patches-4.4/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch
@ -0,0 +1,308 @@
+From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Thu, 15 May 2014 12:36:23 -0700
+Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy
+
+If an i210 is configured for 1000BASE-BX link_mode and has an external phy
+specified, then register an mii bus using the external phy address as
+a mask.
+
+An i210 hooked to an external standard phy will be configured with a link_mo
+of SGMII in which case phy ops will be configured and used internall in the
+igb driver for link status. However, in certain cases one might be using a
+backplane SerDes connection to something that talks on the mdio bus but is
+not a standard phy, such as a switch. In this case by registering an mdio
+bus a phy driver can manage the device.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+---
+ drivers/net/ethernet/intel/igb/e1000_82575.c |  15 +++
+ drivers/net/ethernet/intel/igb/e1000_hw.h    |   7 ++
+ drivers/net/ethernet/intel/igb/igb_main.c    | 168 ++++++++++++++++++++++++++-
+ 3 files changed, 185 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
+@@ -612,13 +612,25 @@ static s32 igb_get_invariants_82575(stru
+ 	switch (link_mode) {
+ 	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
+ 		hw->phy.media_type = e1000_media_type_internal_serdes;
+		if (igb_sgmii_uses_mdio_82575(hw)) {
+			u32 mdicnfg = rd32(E1000_MDICNFG);
+			mdicnfg &= E1000_MDICNFG_PHY_MASK;
+			hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT;
+			hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n",
+			       hw->phy.addr);
+		} else {
+			hw_dbg("1000BASE_KX");
+		}
+ 		break;
+ 	case E1000_CTRL_EXT_LINK_MODE_SGMII:
+ 		/* Get phy control interface type set (MDIO vs. I2C)*/
+ 		if (igb_sgmii_uses_mdio_82575(hw)) {
+ 			hw->phy.media_type = e1000_media_type_copper;
+ 			dev_spec->sgmii_active = true;
+			hw_dbg("SGMII with external MDIO PHY");
+ 			break;
+		} else {
+			hw_dbg("SGMII with external I2C PHY");
+ 		}
+ 		/* fall through for I2C based SGMII */
+ 	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
+@@ -635,8 +647,11 @@ static s32 igb_get_invariants_82575(stru
+ 				hw->phy.media_type = e1000_media_type_copper;
+ 				dev_spec->sgmii_active = true;
+ 			}
+			hw_dbg("SERDES with external SFP");
+ 
+ 			break;
+		} else {
+			hw_dbg("SERDES");
+ 		}
+ 
+ 		/* do not change link mode for 100BaseFX */
+--- a/drivers/net/ethernet/intel/igb/e1000_hw.h
+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h
+@@ -27,6 +27,7 @@
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/netdevice.h>
+#include <linux/phy.h>
+ 
+ #include "e1000_regs.h"
+ #include "e1000_defines.h"
+@@ -543,6 +544,12 @@ struct e1000_hw {
+ 	struct e1000_mbx_info mbx;
+ 	struct e1000_host_mng_dhcp_cookie mng_cookie;
+ 
+#ifdef CONFIG_PHYLIB
+	/* Phylib and MDIO interface */
+	struct mii_bus *mii_bus;
+	struct phy_device *phy_dev;
+	phy_interface_t phy_interface;
+#endif
+ 	union {
+ 		struct e1000_dev_spec_82575	_82575;
+ 	} dev_spec;
+--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
+@@ -41,6 +41,7 @@
+ #include <linux/if_vlan.h>
+ #include <linux/pci.h>
+ #include <linux/pci-aspm.h>
+#include <linux/phy.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+ #include <linux/ip.h>
+@@ -2223,6 +2224,126 @@ static s32 igb_init_i2c(struct igb_adapt
+ 	return status;
+ }
+ 
+
+#ifdef CONFIG_PHYLIB
+/*
+ * MMIO/PHYdev support
+ */
+
+static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct e1000_hw *hw = bus->priv;
+	u16 out;
+	int err;
+
+	err = igb_read_reg_gs40g(hw, mii_id, regnum, &out);
+	if (err)
+		return err;
+	return out;
+}
+
+static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+                               u16 val)
+{
+	struct e1000_hw *hw = bus->priv;
+
+	return igb_write_reg_gs40g(hw, mii_id, regnum, val);
+}
+
+static int igb_enet_mdio_reset(struct mii_bus *bus)
+{
+	udelay(300);
+	return 0;
+}
+
+static void igb_enet_mii_link(struct net_device *netdev)
+{
+}
+
+/* Probe the mdio bus for phys and connect them */
+static int igb_enet_mii_probe(struct net_device *netdev)
+{
+	struct igb_adapter *adapter = netdev_priv(netdev);
+	struct e1000_hw *hw = &adapter->hw;
+	struct phy_device *phy_dev = NULL;
+	int phy_id;
+
+	/* check for attached phy */
+	for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
+		if (hw->mii_bus->phy_map[phy_id]) {
+			phy_dev = hw->mii_bus->phy_map[phy_id];
+			break;
+		}
+	}
+	if (!phy_dev) {
+		netdev_err(netdev, "no PHY found\n");
+		return -ENODEV;
+	}
+
+	hw->phy_interface = PHY_INTERFACE_MODE_RGMII;
+	phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev),
+			      igb_enet_mii_link, hw->phy_interface);
+	if (IS_ERR(phy_dev)) {
+		netdev_err(netdev, "could not attach to PHY\n");
+		return PTR_ERR(phy_dev);
+	}
+
+	hw->phy_dev = phy_dev;
+	netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n",
+		hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev));
+
+	return 0;
+}
+
+/* Create and register mdio bus */
+static int igb_enet_mii_init(struct pci_dev *pdev)
+{
+	struct mii_bus *mii_bus;
+	struct net_device *netdev = pci_get_drvdata(pdev);
+	struct igb_adapter *adapter = netdev_priv(netdev);
+	struct e1000_hw *hw = &adapter->hw;
+	int err;
+
+	mii_bus = mdiobus_alloc();
+	if (mii_bus == NULL) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	mii_bus->name = "igb_enet_mii_bus";
+	mii_bus->read = igb_enet_mdio_read;
+	mii_bus->write = igb_enet_mdio_write;
+	mii_bus->reset = igb_enet_mdio_reset;
+	snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+		 pci_name(pdev), hw->device_id + 1);
+	mii_bus->priv = hw;
+	mii_bus->parent = &pdev->dev;
+	mii_bus->phy_mask = ~(1 << hw->phy.addr);
+
+	err = mdiobus_register(mii_bus);
+	if (err) {
+		printk(KERN_ERR "failed to register mii_bus: %d\n", err);
+		goto err_out_free_mdiobus;
+	}
+	hw->mii_bus = mii_bus;
+
+	return 0;
+
+err_out_free_mdiobus:
+	mdiobus_free(mii_bus);
+err_out:
+	return err;
+}
+
+static void igb_enet_mii_remove(struct e1000_hw *hw)
+{
+	if (hw->mii_bus) {
+		mdiobus_unregister(hw->mii_bus);
+		mdiobus_free(hw->mii_bus);
+	}
+}
+#endif /* CONFIG_PHYLIB */
+
+ /**
+  *  igb_probe - Device Initialization Routine
+  *  @pdev: PCI device information struct
+@@ -2645,6 +2766,13 @@ static int igb_probe(struct pci_dev *pde
+ 		}
+ 	}
+ 	pm_runtime_put_noidle(&pdev->dev);
+
+#ifdef CONFIG_PHYLIB
+	/* create and register the mdio bus if using ext phy */
+	if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
+		igb_enet_mii_init(pdev);
+#endif
+
+ 	return 0;
+ 
+ err_register:
+@@ -2792,6 +2920,10 @@ static void igb_remove(struct pci_dev *p
+ 	struct e1000_hw *hw = &adapter->hw;
+ 
+ 	pm_runtime_get_noresume(&pdev->dev);
+#ifdef CONFIG_PHYLIB
+	if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
+		igb_enet_mii_remove(hw);
+#endif
+ #ifdef CONFIG_IGB_HWMON
+ 	igb_sysfs_exit(adapter);
+ #endif
+@@ -3108,6 +3240,12 @@ static int __igb_open(struct net_device
+ 	if (!resuming)
+ 		pm_runtime_put(&pdev->dev);
+ 
+#ifdef CONFIG_PHYLIB
+	/* Probe and connect to PHY if using ext phy */
+	if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
+		igb_enet_mii_probe(netdev);
+#endif
+
+ 	/* start the watchdog. */
+ 	hw->mac.get_link_status = 1;
+ 	schedule_work(&adapter->watchdog_task);
+@@ -7099,21 +7237,41 @@ void igb_alloc_rx_buffers(struct igb_rin
+ static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+ {
+ 	struct igb_adapter *adapter = netdev_priv(netdev);
+	struct e1000_hw *hw = &adapter->hw;
+ 	struct mii_ioctl_data *data = if_mii(ifr);
+ 
+-	if (adapter->hw.phy.media_type != e1000_media_type_copper)
+	if (adapter->hw.phy.media_type != e1000_media_type_copper &&
+	    !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO))
+ 		return -EOPNOTSUPP;
+ 
+ 	switch (cmd) {
+ 	case SIOCGMIIPHY:
+-		data->phy_id = adapter->hw.phy.addr;
+		data->phy_id = hw->phy.addr;
+ 		break;
+ 	case SIOCGMIIREG:
+-		if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
+-				     &data->val_out))
+-			return -EIO;
+		if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
+			if (igb_read_reg_gs40g(&adapter->hw, data->phy_id,
+					       data->reg_num & 0x1F,
+			                       &data->val_out))
+				return -EIO;
+		} else {
+			if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
+			                     &data->val_out))
+				return -EIO;
+		}
+ 		break;
+ 	case SIOCSMIIREG:
+		if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
+			if (igb_write_reg_gs40g(hw, data->phy_id,
+					        data->reg_num & 0x1F,
+					        data->val_in))
+				return -EIO;
+		} else {
+			if (igb_write_phy_reg(hw, data->reg_num & 0x1F,
+					      data->val_in))
+				return -EIO;
+		}
+		break;
+ 	default:
+ 		return -EOPNOTSUPP;
+ 	}
--- a/target/linux/imx6/patches-4.4/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch
+++ b/target/linux/imx6/patches-4.4/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch
@ -0,0 +1,27 @@
+--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
+@@ -336,6 +336,14 @@ endif # RTL8366_SMI
+ 
+ source "drivers/net/phy/b53/Kconfig"
+ 
+config GATEWORKS_GW16083
+	tristate "Gateworks GW16083 Ethernet Expansion Mezzanine"
+	---help---
+	  The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a
+	  Gateworks Ventana baseboard and provides a 7-port GbE managed
+	  Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP
+	  ports"
+
+ endif # PHYLIB
+ 
+ config MICREL_KS8995MA
+--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
+@@ -46,6 +46,7 @@ obj-$(CONFIG_DP83848_PHY)	+= dp83848.o
+ obj-$(CONFIG_DP83867_PHY)	+= dp83867.o
+ obj-$(CONFIG_STE10XP)		+= ste10Xp.o
+ obj-$(CONFIG_MICREL_PHY)	+= micrel.o
+obj-$(CONFIG_GATEWORKS_GW16083)	+= gw16083.o
+ obj-$(CONFIG_MDIO_OCTEON)	+= mdio-octeon.o
+ obj-$(CONFIG_MICREL_KS8995MA)	+= spi_ks8995.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
--- a/target/linux/imx6/patches-4.4/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch
+++ b/target/linux/imx6/patches-4.4/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch
@ -0,0 +1,56 @@
+--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+@@ -158,6 +158,11 @@
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_i2c2>;
+ 	status = "okay";
+
+	gw16083: gw16083@52 {
+		compatible = "gateworks,gw16083";
+		reg = <0x52>;
+	};
+ };
+ 
+ &i2c3 {
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -233,6 +233,11 @@
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_i2c2>;
+ 	status = "okay";
+
+	gw16083: gw16083@52 {
+		compatible = "gateworks,gw16083";
+		reg = <0x52>;
+	};
+ };
+ 
+ &i2c3 {
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -226,6 +226,11 @@
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_i2c2>;
+ 	status = "okay";
+
+	gw16083: gw16083@52 {
+		compatible = "gateworks,gw16083";
+		reg = <0x52>;
+	};
+ };
+ 
+ &i2c3 {
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -317,6 +317,11 @@
+ 			};
+ 		};
+ 	};
+
+	gw16083: gw16083@52 {
+		compatible = "gateworks,gw16083";
+		reg = <0x52>;
+	};
+ };
+ 
+ &i2c3 {
--- a/target/linux/imx6/patches-4.4/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch
+++ b/target/linux/imx6/patches-4.4/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch
@ -0,0 +1,22 @@
+--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
+@@ -468,6 +468,8 @@ static int i2c_imx_acked(struct imx_i2c_
+ {
+ 	if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
+ 		dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
+		if (i2c_imx->adapter.retries)
+			return -EAGAIN;
+ 		return -ENXIO;  /* No ACK */
+ 	}
+ 
+@@ -1073,6 +1075,10 @@ static int i2c_imx_probe(struct platform
+ 	i2c_imx->adapter.nr		= pdev->id;
+ 	i2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
+ 	i2c_imx->base			= base;
+	if (of_machine_is_compatible("gw,ventana") && phy_addr == 0x021a0000) {
+		dev_info(&pdev->dev, "Adding retries for Ventana GSC\n");
+		i2c_imx->adapter.retries = 3;
+	}
+ 
+ 	/* Get I2C clock */
+ 	i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
--- a/target/linux/imx6/patches-4.4/208-sky2-allow-mac-to-come-from-dt.patch
+++ b/target/linux/imx6/patches-4.4/208-sky2-allow-mac-to-come-from-dt.patch
@ -0,0 +1,28 @@
+--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
+@@ -4812,7 +4812,24 @@ static struct net_device *sky2_init_netd
+ 	 * 1) from device tree data
+ 	 * 2) from internal registers set by bootloader
+ 	 */
+-	iap = of_get_mac_address(hw->pdev->dev.of_node);
+
+	iap = NULL;
+	if (IS_ENABLED(CONFIG_OF)) {
+		struct device_node *np;
+		np = of_find_node_by_path("/aliases");
+		if (np) {
+			const char *path = of_get_property(np, "sky2", NULL);
+			if (path)
+				np = of_find_node_by_path(path);
+			if (np)
+				path = of_get_mac_address(np);
+			if (path)
+				iap = (unsigned char *) path;
+		}
+	}
+
+	if (!iap)
+		iap = of_get_mac_address(hw->pdev->dev.of_node);
+ 	if (iap)
+ 		memcpy(dev->dev_addr, iap, ETH_ALEN);
+ 	else
--- a/target/linux/imx6/patches-4.4/209-ARM-imx-ventana-add-sky2-alias.patch
+++ b/target/linux/imx6/patches-4.4/209-ARM-imx-ventana-add-sky2-alias.patch
@ -0,0 +1,20 @@
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -15,6 +15,7 @@
+ 	/* these are used by bootloader for disabling nodes */
+ 	aliases {
+ 		ethernet1 = &eth1;
+		sky2 = &eth1;
+ 		led0 = &led0;
+ 		led1 = &led1;
+ 		led2 = &led2;
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -15,6 +15,7 @@
+ 	/* these are used by bootloader for disabling nodes */
+ 	aliases {
+ 		ethernet1 = &eth1;
+		sky2 = &eth1;
+ 		led0 = &led0;
+ 		led1 = &led1;
+ 		led2 = &led2;