mediatek: add Airoha EN8801SC PHY driver
Airoha EN8801SC PHY is a gigabit PHY used on Edgecore EAP111 so, include the MTK driver with some cleanups. Unfortunatelly, there is no specification sheet nor datasheet available in order to demistify the magic PBUS writes and work on upstreaming this driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Robert Marko
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98f9154316
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// SPDX-License-Identifier: GPL-2.0
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/* FILE NAME: en8801sc.h
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* PURPOSE:
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* Define EN8801SC driver function
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*
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* NOTES:
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*
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*/
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#ifndef __EN8801SC_H
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#define __EN8801SC_H
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/* NAMING DECLARATIONS
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*/
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#define EN8801S_DRIVER_VERSION "1.1.8_Generic"
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#define EN8801S_PBUS_DEFAULT_ADDR 0x1e
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#define EN8801S_PHY_DEFAULT_ADDR 0x1d
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#define EN8801S_RG_ETHER_PHY_OUI 0x19a4
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#define EN8801S_RG_SMI_ADDR 0x19a8
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#define EN8801S_RG_BUCK_CTL 0x1a20
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#define EN8801S_RG_LTR_CTL 0x0cf8
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#define EN8801S_RG_PROD_VER 0x18e0
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#define EN8801S_PBUS_OUI 0x17a5
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#define EN8801S_PHY_ID1 0x03a2
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#define EN8801S_PHY_ID2 0x9461
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#define EN8801SC_PHY_ID 0x03a29471
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#define LED_ON_CTRL(i) (0x024 + ((i)*2))
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#define LED_ON_EN (1 << 15)
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#define LED_ON_POL (1 << 14)
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#define LED_ON_EVT_MASK (0x7f)
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/* LED ON Event Option.B */
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#define LED_ON_EVT_FORCE (1 << 6)
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#define LED_ON_EVT_LINK_DOWN (1 << 3)
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#define LED_ON_EVT_LINK_10M (1 << 2)
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#define LED_ON_EVT_LINK_100M (1 << 1)
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#define LED_ON_EVT_LINK_1000M (1 << 0)
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/* LED ON Event Option.E */
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#define LED_BLK_CTRL(i) (0x025 + ((i)*2))
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#define LED_BLK_EVT_MASK (0x3ff)
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/* LED Blinking Event Option.B*/
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#define LED_BLK_EVT_FORCE (1 << 9)
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#define LED_BLK_EVT_10M_RX_ACT (1 << 5)
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#define LED_BLK_EVT_10M_TX_ACT (1 << 4)
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#define LED_BLK_EVT_100M_RX_ACT (1 << 3)
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#define LED_BLK_EVT_100M_TX_ACT (1 << 2)
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#define LED_BLK_EVT_1000M_RX_ACT (1 << 1)
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#define LED_BLK_EVT_1000M_TX_ACT (1 << 0)
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/* LED Blinking Event Option.E*/
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#define LED_ENABLE 1
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#define LED_DISABLE 0
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#define LINK_UP 1
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#define LINK_DOWN 0
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/*
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SFP Sample for verification
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Tx Reverse, Rx Reverse
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*/
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#define EN8801S_TX_POLARITY_NORMAL 0x0
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#define EN8801S_TX_POLARITY_REVERSE 0x1
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#define EN8801S_RX_POLARITY_NORMAL (0x1 << 1)
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#define EN8801S_RX_POLARITY_REVERSE (0x0 << 1)
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/*
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The following led_cfg example is for reference only.
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LED5 1000M/LINK/ACT (GPIO5) <-> BASE_T_LED0,
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LED6 10/100M/LINK/ACT(GPIO9) <-> BASE_T_LED1,
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LED4 100M/LINK/ACT (GPIO8) <-> BASE_T_LED2,
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*/
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/* User-defined.B */
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#define BASE_T_LED0_ON_CFG (LED_ON_EVT_LINK_1000M)
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#define BASE_T_LED0_BLK_CFG \
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(LED_BLK_EVT_1000M_TX_ACT | \
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LED_BLK_EVT_1000M_RX_ACT)
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#define BASE_T_LED1_ON_CFG \
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(LED_ON_EVT_LINK_100M | \
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LED_ON_EVT_LINK_10M)
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#define BASE_T_LED1_BLK_CFG \
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(LED_BLK_EVT_100M_TX_ACT | \
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LED_BLK_EVT_100M_RX_ACT | \
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LED_BLK_EVT_10M_TX_ACT | \
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LED_BLK_EVT_10M_RX_ACT)
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#define BASE_T_LED2_ON_CFG \
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(LED_ON_EVT_LINK_100M)
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#define BASE_T_LED2_BLK_CFG \
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(LED_BLK_EVT_100M_TX_ACT | \
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LED_BLK_EVT_100M_RX_ACT)
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#define BASE_T_LED3_ON_CFG (0x0)
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#define BASE_T_LED3_BLK_CFG (0x0)
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/* User-defined.E */
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#define EN8801S_LED_COUNT 4
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#define MAX_RETRY 5
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#define MAX_OUI_CHECK 2
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/* CL45 MDIO control */
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#define MII_MMD_ACC_CTL_REG 0x0d
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#define MII_MMD_ADDR_DATA_REG 0x0e
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#define MMD_OP_MODE_DATA BIT(14)
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#define MAX_TRG_COUNTER 5
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/* CL22 Reg Support Page Select */
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#define RgAddr_Reg1Fh 0x1f
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#define CL22_Page_Reg 0x0000
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#define CL22_Page_ExtReg 0x0001
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#define CL22_Page_MiscReg 0x0002
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#define CL22_Page_LpiReg 0x0003
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#define CL22_Page_tReg 0x02A3
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#define CL22_Page_TrReg 0x52B5
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/* CL45 Reg Support DEVID */
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#define DEVID_03 0x03
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#define DEVID_07 0x07
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#define DEVID_1E 0x1E
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#define DEVID_1F 0x1F
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/* TokenRing Reg Access */
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#define TrReg_PKT_XMT_STA 0x8000
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#define TrReg_WR 0x8000
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#define TrReg_RD 0xA000
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#define RgAddr_LPI_1Ch 0x1c
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#define RgAddr_AUXILIARY_1Dh 0x1d
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#define RgAddr_PMA_00h 0x0f80
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#define RgAddr_PMA_01h 0x0f82
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#define RgAddr_PMA_17h 0x0fae
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#define RgAddr_PMA_18h 0x0fb0
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#define RgAddr_DSPF_03h 0x1686
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#define RgAddr_DSPF_06h 0x168c
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#define RgAddr_DSPF_08h 0x1690
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#define RgAddr_DSPF_0Ch 0x1698
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#define RgAddr_DSPF_0Dh 0x169a
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#define RgAddr_DSPF_0Fh 0x169e
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#define RgAddr_DSPF_10h 0x16a0
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#define RgAddr_DSPF_11h 0x16a2
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#define RgAddr_DSPF_13h 0x16a6
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#define RgAddr_DSPF_14h 0x16a8
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#define RgAddr_DSPF_1Bh 0x16b6
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#define RgAddr_DSPF_1Ch 0x16b8
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#define RgAddr_TR_26h 0x0ecc
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#define RgAddr_R1000DEC_15h 0x03aa
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#define RgAddr_R1000DEC_17h 0x03ae
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#define LED_BCR (0x021)
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#define LED_BCR_EXT_CTRL (1 << 15)
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#define LED_BCR_CLK_EN (1 << 3)
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#define LED_BCR_TIME_TEST (1 << 2)
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#define LED_BCR_MODE_MASK (3)
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#define LED_BCR_MODE_DISABLE (0)
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#define LED_ON_DUR (0x022)
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#define LED_ON_DUR_MASK (0xffff)
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#define LED_BLK_DUR (0x023)
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#define LED_BLK_DUR_MASK (0xffff)
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#define LED_GPIO_SEL_MASK 0x7FFFFFF
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#define UNIT_LED_BLINK_DURATION 1024
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/* Invalid data */
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#define INVALID_DATA 0xffffffff
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#define LED_SET_GPIO_SEL(gpio, led, val) \
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(val |= (led << (8 * (gpio % 4)))) \
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#define GET_BIT(val, bit) ((val & BIT(bit)) >> bit)
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/* DATA TYPE DECLARATIONS
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*/
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struct AIR_BASE_T_LED_CFG_S {
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u16 en;
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u16 gpio;
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u16 pol;
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u16 on_cfg;
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u16 blk_cfg;
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};
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union gephy_all_REG_LpiReg1Ch {
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struct {
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/* b[15:00] */
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u16 smi_deton_wt : 3;
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u16 smi_det_mdi_inv : 1;
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u16 smi_detoff_wt : 3;
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u16 smi_sigdet_debouncing_en : 1;
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u16 smi_deton_th : 6;
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u16 rsv_14 : 2;
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} DataBitField;
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u16 DATA;
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};
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union gephy_all_REG_dev1Eh_reg324h {
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struct {
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/* b[15:00] */
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u16 rg_smi_detcnt_max : 6;
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u16 rsv_6 : 2;
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u16 rg_smi_det_max_en : 1;
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u16 smi_det_deglitch_off : 1;
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u16 rsv_10 : 6;
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} DataBitField;
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u16 DATA;
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};
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union gephy_all_REG_dev1Eh_reg012h {
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struct {
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/* b[15:00] */
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u16 da_tx_i2mpb_a_tbt : 6;
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u16 rsv_6 : 4;
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u16 da_tx_i2mpb_a_gbe : 6;
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} DataBitField;
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u16 DATA;
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};
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union gephy_all_REG_dev1Eh_reg017h {
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struct {
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/* b[15:00] */
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u16 da_tx_i2mpb_b_tbt : 6;
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u16 rsv_6 : 2;
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u16 da_tx_i2mpb_b_gbe : 6;
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u16 rsv_14 : 2;
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} DataBitField;
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u16 DATA;
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};
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enum {
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AIR_LED_BLK_DUR_32M,
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AIR_LED_BLK_DUR_64M,
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AIR_LED_BLK_DUR_128M,
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AIR_LED_BLK_DUR_256M,
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AIR_LED_BLK_DUR_512M,
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AIR_LED_BLK_DUR_1024M,
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AIR_LED_BLK_DUR_LAST
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};
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enum {
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AIR_ACTIVE_LOW,
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AIR_ACTIVE_HIGH,
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};
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enum {
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AIR_LED_MODE_DISABLE,
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AIR_LED_MODE_USER_DEFINE,
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AIR_LED_MODE_LAST
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};
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#endif /* End of __EN8801SC_H */
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CONFIG_64BIT=y
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# CONFIG_AHCI_MTK is not set
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_64BIT=y
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# CONFIG_AHCI_MTK is not set
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
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CONFIG_64BIT=y
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# CONFIG_AHCI_MTK is not set
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_AQUANTIA_PHY=y
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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CONFIG_64BIT=y
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# CONFIG_AHCI_MTK is not set
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_AQUANTIA_PHY=y
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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# CONFIG_AIO is not set
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_FORCE_MAX_ORDER=11
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# CONFIG_AIO is not set
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_FORCE_MAX_ORDER=11
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# CONFIG_AIROHA_EN8801SC_PHY is not set
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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@ -0,0 +1,38 @@
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From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Sat, 23 Mar 2024 20:21:14 +0100
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Subject: [PATCH] net: phy: add Airoha EN8801SC PHY
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Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a
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modified version of MTK SDK driver.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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drivers/net/phy/Kconfig | 5 +++++
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drivers/net/phy/Makefile | 1 +
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2 files changed, 6 insertions(+)
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -143,6 +143,11 @@ endif # RTL8366_SMI
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comment "MII PHY device drivers"
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+config AIROHA_EN8801SC_PHY
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+ tristate "Airoha EN8801SC Gigabit PHY"
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+ help
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+ Currently supports the Airoha EN8801SC PHY.
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+
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config AIR_EN8811H_PHY
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tristate "Airoha EN8811H 2.5 Gigabit PHY"
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help
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -47,6 +47,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
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obj-$(CONFIG_ADIN_PHY) += adin.o
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obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
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+obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o
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obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
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obj-$(CONFIG_AMD_PHY) += amd.o
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obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
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@ -0,0 +1,38 @@
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From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Sat, 23 Mar 2024 20:21:14 +0100
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Subject: [PATCH] net: phy: add Airoha EN8801SC PHY
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Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a
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modified version of MTK SDK driver.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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drivers/net/phy/Kconfig | 5 +++++
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drivers/net/phy/Makefile | 1 +
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2 files changed, 6 insertions(+)
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -142,6 +142,11 @@ endif # RTL8366_SMI
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comment "MII PHY device drivers"
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+config AIROHA_EN8801SC_PHY
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+ tristate "Airoha EN8801SC Gigabit PHY"
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+ help
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+ Currently supports the Airoha EN8801SC PHY.
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+
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config AIR_EN8811H_PHY
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tristate "Airoha EN8811H 2.5 Gigabit PHY"
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help
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -49,6 +49,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
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obj-$(CONFIG_ADIN_PHY) += adin.o
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obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
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+obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o
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obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
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obj-$(CONFIG_AMD_PHY) += amd.o
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obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
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