realtek: Add RTL931X sub-target
We add the RTL931X sub-target with kernel configuration for a dual core MIPS InterAptive CPU. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz
Daniel Golle
parent
9ed6097054
commit
0b8dfe0851
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@ -7,7 +7,7 @@ BOARD:=realtek
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BOARDNAME:=Realtek MIPS
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DEVICE_TYPE:=basic
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FEATURES:=ramdisk squashfs
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SUBTARGETS:=rtl838x rtl839x rtl930x
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SUBTARGETS:=rtl838x rtl839x rtl930x rtl931x
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KERNEL_PATCHVER:=5.10
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@ -0,0 +1,181 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl838x-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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frequency = <1000000000>;
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cpu@0 {
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compatible = "mti,interaptive";
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reg = <0>;
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};
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cpu@1 {
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compatible = "mti,interaptive";
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reg = <1>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,38400";
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};
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lx_clk: lx_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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cpuclock: cpuclock@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* FIXME: there should be way to detect this */
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clock-frequency = <1000000000>;
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};
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cpuintc: cpuintc {
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compatible = "mti,cpu-interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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gic: interrupt-controller@1ddc0000 {
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compatible = "mti,gic";
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reg = <0x1ddc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/*
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* Declare the interrupt-parent even though the mti,gic
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* binding doesn't require it, such that the kernel can
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* figure out that cpu_intc is the root interrupt
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpuintc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&cpuclock>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x18000000 0x10000>;
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spi0: spi@1200 {
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status = "okay";
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compatible = "realtek,rtl8380-spi";
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reg = <0x1200 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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watchdog0: watchdog@3260 {
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compatible = "realtek,rtl9310-wdt";
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reg = <0x3260 0xc>;
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realtek,reset-mode = "soc";
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clocks = <&lx_clk>;
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timeout-sec = <30>;
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interrupt-parent = <&gic>;
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interrupt-names = "phase1", "phase2";
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interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio0: gpio-controller@3300 {
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compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio";
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reg = <0x3300 0x1c>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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uart0: uart@2000 {
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compatible = "ns16550a";
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reg = <0x2000 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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uart1: uart@2100 {
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compatible = "ns16550a";
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reg = <0x2100 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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status = "disabled";
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};
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};
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ethernet0: ethernet@1b00a300 {
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status = "okay";
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compatible = "realtek,rtl838x-eth";
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reg = <0x1b00a300 0x100>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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switch0: switch@1b000000 {
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compatible = "realtek,rtl83xx-switch";
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status = "okay";
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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@ -45,6 +45,7 @@
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#define RTL838X_STAT_PRVTE_DROP_COUNTERS (0x6A00)
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#define RTL839X_STAT_PRVTE_DROP_COUNTERS (0x3E00)
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#define RTL930X_STAT_PRVTE_DROP_COUNTERS (0xB5B8)
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#define RTL931X_STAT_PRVTE_DROP_COUNTERS (0xd800)
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int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port);
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void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
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@ -106,6 +107,25 @@ const char *rtl930x_drop_cntr[] = {
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"STACK_NONUC_BLOCKING_PMSK", "STACK_PORT_NOT_FOUND", "ACL_LOOPBACK_DROP", "IP6_ROUTING_EXT_HEADER"
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};
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const char *rtl931x_drop_cntr[] = {
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"ALE_RX_GOOD_PKTS", "RX_MAX_FRAME_SIZE", "MAC_RX_DROP", "OPENFLOW_IP_MPLS_TTL", "OPENFLOW_TBL_MISS",
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"IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", // 10
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"STACK_NONUC_BLOCKING_PMSK", "L2_CRC", "SRC_PORT_FILTER", "PARSER_PACKET_TOO_LONG", "PARSER_MALFORM_PACKET",
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"MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", // 20
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"MAC_IP_SUBNET_BASED_VLAN", "OAM_PARSER", "UC_MC_RPF", "IP_MAC_BINDING_MATCH_MISMATCH", "SA_BLOCK",
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"TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", // 30,
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"OAMPDU", "CCM_RX", "CFM_UNKNOWN_TYPE", "LBM_LBR_LTM_LTR", "Y_1731", "VLAN_LIMIT_LEARN",
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"VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", // 40
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"L3_CRC", "BPDU_PTP_LLDP_EAPOL_RMA", "MSTP_SRC_DROP_DISABLED_BLOCKING", "INVALID_SA", "NEW_SA",
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"VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", // 50
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"MPLS_UNKNOWN_LBL", "L3_IPUC_NON_IP", "TTL", "MTU", "ICMP_REDIRECT", "STORM_CONTROL", "L3_DIP_DMAC_MISMATCH",
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"IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", // 60
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"ROUTING_IP_ADDR_CHECK", "ROUTING_EXCEPTION", "DA_BLOCK", "OAM_MUX", "PORT_ISOLATION", "VLAN_EGR_FILTER",
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"MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", // 70
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"L2_UC", "L2_MC", "IP4_MC", "IP6_MC", "L3_UC_MC_ROUTE", "UNKNOWN_L2_UC_FLPM", "BC_FLPM",
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"VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM" // 80,
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};
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static ssize_t rtl838x_common_read(char __user *buffer, size_t count,
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loff_t *ppos, unsigned int value)
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{
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@ -217,6 +237,11 @@ static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t
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offset = RTL930X_STAT_PRVTE_DROP_COUNTERS;
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num = 85;
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break;
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case RTL9310_FAMILY_ID:
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d = rtl931x_drop_cntr;
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offset = RTL931X_STAT_PRVTE_DROP_COUNTERS;
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num = 81;
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break;
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}
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buf = kmalloc(30 * num, GFP_KERNEL);
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@ -0,0 +1 @@
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# SPDX-License-Identifier: GPL-2.0-only
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@ -0,0 +1,74 @@
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -307,14 +307,24 @@ endif
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KBUILD_AFLAGS += $(cflags-y)
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KBUILD_CFLAGS += $(cflags-y)
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+ifdef CONFIG_931X
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+KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
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+bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
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+ VMLINUX_ENTRY_ADDRESS=$(entry-y) \
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+ PLATFORM="$(platform-y)" \
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+ ITS_INPUTS="$(its-y)"
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+else
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KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) -DLINKER_LOAD_ADDRESS=$(load-ld)
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-KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
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-
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bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
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LINKER_LOAD_ADDRESS=$(load-ld) \
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VMLINUX_ENTRY_ADDRESS=$(entry-y) \
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PLATFORM="$(platform-y)" \
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ITS_INPUTS="$(its-y)"
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+endif
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+KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
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+
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+
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+
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ifdef CONFIG_32BIT
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bootvars-y += ADDR_BITS=32
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endif
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--- a/arch/mips/kernel/head.S
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+++ b/arch/mips/kernel/head.S
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@@ -60,12 +60,14 @@
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.endm
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#ifndef CONFIG_NO_EXCEPT_FILL
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+#ifndef CONFIG_RTL931X
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/*
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* Reserved space for exception handlers.
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* Necessary for machines which link their kernels at KSEG0.
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*/
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.fill 0x400
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#endif
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+#endif
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EXPORT(_stext)
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@@ -79,11 +81,13 @@ FEXPORT(__kernel_entry)
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j kernel_entry
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#endif /* CONFIG_BOOT_RAW */
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+#ifndef CONFIG_RTL931X
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#ifdef CONFIG_IMAGE_CMDLINE_HACK
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.ascii "CMDLINE:"
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EXPORT(__image_cmdline)
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.fill 0x400
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#endif /* CONFIG_IMAGE_CMDLINE_HACK */
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+#endif
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__REF
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--- a/arch/mips/kernel/vmlinux.lds.S
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+++ b/arch/mips/kernel/vmlinux.lds.S
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@@ -55,7 +55,11 @@ SECTIONS
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/* . = 0xa800000000300000; */
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. = 0xffffffff80300000;
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#endif
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+#ifdef CONFIG_RTL931X
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+ . = 0x80220000;
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+#else
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. = LINKER_LOAD_ADDRESS;
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+#endif
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/* read-only */
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_text = .; /* Text and read-only data */
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.text : {
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@ -0,0 +1,223 @@
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MMAP_RND_BITS_MAX=15
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_COUNT=16
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CONFIG_BLK_DEV_RAM_SIZE=4096
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CONFIG_CEVT_R4K=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_BOSTON=y
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_DIEI=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_RIXI=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_MIPS32=y
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# CONFIG_CPU_MIPS32_R1 is not set
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
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CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CPU_SUPPORTS_MSA=y
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CONFIG_MIPS_MT=y
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CONFIG_MIPS_MT_FPAFF=y
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CONFIG_MIPS_MT_SMP=y
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# CONFIG_MIPS_NO_APPENDED_DTB is not set
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CONFIG_MIPS_NR_CPU_NR_MAP=4
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CONFIG_HIGHMEM=y
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CONFIG_CRYPTO_GF128MUL=y
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CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
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CONFIG_CRYPTO_NULL2=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CSRC_R4K=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_SECTION_MISMATCH=y
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CONFIG_DMA_NONCOHERENT=y
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CONFIG_DTC=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_FIXED_PHY=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IOMAP=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_LIB_ASHLDI3=y
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CONFIG_GENERIC_LIB_ASHRDI3=y
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CONFIG_GENERIC_LIB_CMPDI2=y
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CONFIG_GENERIC_LIB_LSHRDI3=y
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CONFIG_GENERIC_LIB_UCMPDI2=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_PINCTRL_GROUPS=y
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CONFIG_GENERIC_PINMUX_FUNCTIONS=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_REALTEK_OTTO=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_RTL8231=y
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CONFIG_GRO_CELLS=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_HWMON=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_ALGOBIT=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_GPIO=y
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CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_RTL9300=y
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CONFIG_I2C_RTL9300=y
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CONFIG_I2C_SMBUS=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_MIPS_CPU=y
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CONFIG_IRQ_WORK=y
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CONFIG_JFFS2_ZLIB=y
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CONFIG_LEDS_GPIO=y
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CONFIG_LEGACY_PTYS=y
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CONFIG_LEGACY_PTY_COUNT=256
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||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LLD_VERSION=0
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MDIO_I2C=y
|
||||
CONFIG_MDIO_SMBUS=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MIPS=y
|
||||
CONFIG_MIPS_ASID_BITS=8
|
||||
CONFIG_MIPS_ASID_SHIFT=0
|
||||
CONFIG_MIPS_CBPF_JIT=y
|
||||
CONFIG_MIPS_CLOCK_VSYSCALL=y
|
||||
# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
|
||||
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
|
||||
CONFIG_MIPS_CMDLINE_FROM_DTB=y
|
||||
# CONFIG_MIPS_ELF_APPENDED_DTB is not set
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
|
||||
# CONFIG_MIPS_NO_APPENDED_DTB is not set
|
||||
CONFIG_MIPS_RAW_APPENDED_DTB=y
|
||||
CONFIG_MIPS_SPRAM=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_GEOMETRY=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
|
||||
CONFIG_MTD_SPLIT_EVA_FW=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MTD_SPLIT_TPLINK_FW=y
|
||||
CONFIG_MTD_SPLIT_UIMAGE_FW=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_PER_CPU_KM=y
|
||||
CONFIG_NET_DEVLINK=y
|
||||
CONFIG_NET_DSA=y
|
||||
CONFIG_NET_DSA_RTL83XX=y
|
||||
CONFIG_NET_DSA_TAG_RTL83XX=y
|
||||
CONFIG_NET_DSA_TAG_TRAILER=y
|
||||
CONFIG_NET_RTL838X=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_PCI_DRIVERS_LEGACY=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=2
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_REALTEK_PHY is not set
|
||||
CONFIG_REALTEK_SOC_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RTL838X=y
|
||||
# CONFIG_RTL9300_TIMER is not set
|
||||
CONFIG_SENSORS_GPIO_FAN=y
|
||||
CONFIG_SENSORS_LM75=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SFP=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
|
||||
CONFIG_SYS_SUPPORTS_MIPS16=y
|
||||
CONFIG_TARGET_ISA_REV=2
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TINY_SRCU=y
|
||||
# CONFIG_USE_GENERIC_EARLY_PRINTK_8250 is not set
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=13
|
||||
# CONFIG_MIPS_VPE_LOADER is not set
|
||||
CONFIG_MIPS_CPU_SCACHE=y
|
||||
CONFIG_SPI_RTL838X=y
|
||||
CONFIG_MIPS_MT_SMP=y
|
||||
CONFIG_MIPS_CPC=y
|
||||
CONFIG_MIPS_CPS=y
|
||||
CONFIG_MIPS_PM=y
|
||||
# CONFIG_MIPS_CMP is not set
|
||||
CONFIG_MIPS_CPS_CPUIDLE=y
|
||||
# CONFIG_MIPS_CPS_NS16550_BOOL is not set
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_RTL83XX=y
|
||||
# CONFIG_RTL838X is not set
|
||||
# CONFIG_RTL839X is not set
|
||||
CONFIG_RTL930X=y
|
||||
CONFIG_RTL931X=y
|
||||
CONFIG_REALTEK_OTTO_WDT=y
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
ARCH:=mips
|
||||
SUBTARGET:=rtl931x
|
||||
CPU_TYPE:=24kc
|
||||
BOARD:=realtek
|
||||
BOARDNAME:=Realtek MIPS RTL931X
|
||||
|
||||
KERNEL_PATCHVER:=5.10
|
||||
|
||||
define Target/Description
|
||||
Build firmware images for Realtek RTL931x based boards.
|
||||
endef
|
||||
Loading…
Reference in New Issue