ath79: add support for TP-Link CPE210 v1

Specifications:

    * SoC: Qualcomm Atheros AR9344 (560 MHz)
    * RAM: 64MB
    * Storage: 8 MB
    * Wireless: 2.4GHz N based built into SoC 2x2
    * Ethernet: 2x 100/10 Mbps, integrated into SoC, 24V POE IN

Installation:

Flash factory image through stock firmware WEB UI
or through TFTP:
To get to TFTP recovery just hold reset button while powering on for
around 4-5 seconds and release.
Rename factory image to recovery.bin
Stock TFTP server IP:192.168.0.100
Stock device TFTP address:192.168.0.254

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This commit is contained in:
Adrian Schmutzler 2019-07-20 12:01:14 +02:00 committed by David Bauer
parent 198eae2862
commit 08857e69be
6 changed files with 117 additions and 0 deletions

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@ -158,6 +158,15 @@ tplink,archer-d50-v1)
ucidef_set_led_switch "wan_data" "WAN Data" "tp-link:white:internet" "switch0" "0x02" "" "tx rx"
ucidef_set_led_switch "wan_link" "WAN Link" "tp-link:white:wan" "switch0" "0x02" "" "link"
;;
tplink,cpe210-v1)
ucidef_set_led_netdev "lan0" "LAN0" "tp-link:green:lan0" "eth1"
ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10"
ucidef_set_rssimon "wlan0" "200000" "1"
ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:green:link1" "wlan0" "1" "100"
ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:green:link2" "wlan0" "30" "100"
ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:green:link3" "wlan0" "60" "100"
ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:green:link4" "wlan0" "80" "100"
;;
tplink,cpe210-v2|\
tplink,cpe210-v3)
ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0"

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@ -102,6 +102,7 @@ ath79_setup_interfaces()
;;
comfast,cf-e110n-v2|\
comfast,cf-e120a-v3|\
tplink,cpe210-v1|\
ubnt,nanostation-m|\
ubnt,routerstation)
ucidef_set_interfaces_lan_wan "eth1" "eth0"

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@ -42,6 +42,9 @@ tplink,archer-c25-v1)
ucidef_add_gpio_switch "led_control" "LED control" "21" "0"
ucidef_add_gpio_switch "led_reset" "LED reset" "19" "1"
;;
tplink,cpe210-v1)
ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "20"
;;
ubnt,nanostation-ac)
ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "3"
;;

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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar9344_tplink_cpexxx-v1.dtsi"
/ {
compatible = "tplink,cpe210-v1", "qca,ar9344";
model = "TP-Link CPE210 v1";
};

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@ -0,0 +1,83 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar9344_tplink_cpexxx.dtsi"
/ {
aliases {
led-boot = &system;
led-failsafe = &system;
led-running = &system;
led-upgrade = &system;
};
leds {
compatible = "gpio-leds";
lan0 {
label = "tp-link:green:lan0";
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "tp-link:green:lan1";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
link1 {
label = "tp-link:green:link1";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
};
link2 {
label = "tp-link:green:link2";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
link3 {
label = "tp-link:green:link3";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
system: link4 {
label = "tp-link:green:link4";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};
&gpio {
gpio_ext_lna0 {
gpio-hog;
gpios = <18 0>;
output-high;
line-name = "tp-link:ext:lna0";
};
gpio_ext_lna1 {
gpio-hog;
gpios = <19 0>;
output-high;
line-name = "tp-link:ext:lna1";
};
};
&eth1 {
status = "okay";
mtd-mac-address = <&info 0x8>;
gmac-config {
device = <&gmac>;
switch-phy-swap = <0>;
switch-only-mode = <1>;
};
};
&eth0 {
status = "okay";
phy-handle = <&swphy4>;
mtd-mac-address = <&info 0x8>;
};

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@ -157,6 +157,18 @@ define Device/tplink_archer-c7-v5
endef
TARGET_DEVICES += tplink_archer-c7-v5
define Device/tplink_cpe210-v1
$(Device/tplink-loader-okli)
ATH_SOC := ar9344
IMAGE_SIZE := 7680k
DEVICE_MODEL := CPE210
DEVICE_VARIANT := v1
DEVICE_PACKAGES := rssileds
TPLINK_BOARD_ID := CPE210
SUPPORTED_DEVICES += cpe210
endef
TARGET_DEVICES += tplink_cpe210-v1
define Device/tplink_cpe210-v2
$(Device/tplink-safeloader)
ATH_SOC := qca9533