306 lines
9.6 KiB
Diff
306 lines
9.6 KiB
Diff
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From 8554f6a7914d28b179671540f527897d85c88809 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Fri, 1 Mar 2024 12:43:01 +0200
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Subject: [PATCH 41/48] net: dsa: mt7530: get rid of
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priv->info->cpu_port_config()
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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priv->info->cpu_port_config() is used for MT7531 and the switch on the
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MT7988 SoC. It sets up the ports described as a CPU port earlier than the
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phylink code path would do.
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This function is useless as:
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- Configuring the MACs can be done from the phylink_mac_config code path
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instead.
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- All the link configuration it does on the CPU ports are later undone with
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the port_enable, phylink_mac_config, and then phylink_mac_link_up code
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path [1].
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priv->p5_interface and priv->p6_interface were being used to prevent
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configuring the MACs from the phylink_mac_config code path. Remove them now
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that they hold no purpose.
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Remove priv->info->cpu_port_config(). On mt753x_phylink_mac_config, switch
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to if statements to simplify the code.
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Remove the overwriting of the speed and duplex interfaces for certain
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interface modes. Phylink already provides the speed and duplex variables
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with proper values. Phylink already sets the max speed of TRGMII to
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SPEED_1000. Add SPEED_2500 for PHY_INTERFACE_MODE_2500BASEX to where the
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speed and EEE bits are set instead.
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On the switch on the MT7988 SoC, PHY_INTERFACE_MODE_INTERNAL is being used
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to describe the interface mode of the 10G MAC, which is of port 6. On
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mt7988_cpu_port_config() PMCR_FORCE_SPEED_1000 was set via the
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PMCR_CPU_PORT_SETTING() mask. Add SPEED_10000 case to where the speed bits
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are set to cover this. No need to add it to where the EEE bits are set as
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the "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
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v0.1" document shows that these bits don't exist on the MT7530_PMCR_P(6)
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register.
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Remove the definition of PMCR_CPU_PORT_SETTING() now that it holds no
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purpose.
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Change mt753x_cpu_port_enable() to void now that there're no error cases
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left.
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Link: https://lore.kernel.org/netdev/ZHy2jQLesdYFMQtO@shell.armlinux.org.uk/ [1]
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Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/dsa/mt7530.c | 114 +++------------------------------------
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drivers/net/dsa/mt7530.h | 11 ----
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2 files changed, 7 insertions(+), 118 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -995,18 +995,10 @@ mt753x_trap_frames(struct mt7530_priv *p
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MT753X_BPDU_CPU_ONLY);
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}
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-static int
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+static void
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mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
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{
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struct mt7530_priv *priv = ds->priv;
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- int ret;
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-
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- /* Setup max capability of CPU port at first */
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- if (priv->info->cpu_port_config) {
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- ret = priv->info->cpu_port_config(ds, port);
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- if (ret)
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- return ret;
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- }
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/* Enable Mediatek header mode on the cpu port */
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mt7530_write(priv, MT7530_PVC_P(port),
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@@ -1032,8 +1024,6 @@ mt753x_cpu_port_enable(struct dsa_switch
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/* Set to fallback mode for independent VLAN learning */
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_FALLBACK_MODE);
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-
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- return 0;
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}
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static int
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@@ -2288,8 +2278,6 @@ mt7530_setup(struct dsa_switch *ds)
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val |= MHWTRAP_MANUAL;
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mt7530_write(priv, MT7530_MHWTRAP, val);
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- priv->p6_interface = PHY_INTERFACE_MODE_NA;
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-
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mt753x_trap_frames(priv);
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/* Enable and reset MIB counters */
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@@ -2304,9 +2292,7 @@ mt7530_setup(struct dsa_switch *ds)
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mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
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if (dsa_is_cpu_port(ds, i)) {
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- ret = mt753x_cpu_port_enable(ds, i);
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- if (ret)
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- return ret;
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+ mt753x_cpu_port_enable(ds, i);
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} else {
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mt7530_port_disable(ds, i);
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@@ -2410,9 +2396,7 @@ mt7531_setup_common(struct dsa_switch *d
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mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
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if (dsa_is_cpu_port(ds, i)) {
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- ret = mt753x_cpu_port_enable(ds, i);
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- if (ret)
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- return ret;
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+ mt753x_cpu_port_enable(ds, i);
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} else {
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mt7530_port_disable(ds, i);
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@@ -2501,10 +2485,6 @@ mt7531_setup(struct dsa_switch *ds)
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mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
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MT7531_GPIO0_INTERRUPT);
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- /* Let phylink decide the interface later. */
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- priv->p5_interface = PHY_INTERFACE_MODE_NA;
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- priv->p6_interface = PHY_INTERFACE_MODE_NA;
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-
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/* Enable PHY core PLL, since phy_device has not yet been created
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* provided for phy_[read,write]_mmd_indirect is called, we provide
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* our own mt7531_ind_mmd_phy_[read,write] to complete this
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@@ -2716,26 +2696,9 @@ mt753x_phylink_mac_config(struct dsa_swi
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struct mt7530_priv *priv = ds->priv;
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u32 mcr_cur, mcr_new;
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- switch (port) {
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- case 5:
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- if (priv->p5_interface == state->interface)
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- break;
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-
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+ if (port == 5 || port == 6)
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mt753x_mac_config(ds, port, mode, state);
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- if (priv->p5_intf_sel != P5_DISABLED)
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- priv->p5_interface = state->interface;
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- break;
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- case 6:
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- if (priv->p6_interface == state->interface)
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- break;
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-
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- mt753x_mac_config(ds, port, mode, state);
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-
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- priv->p6_interface = state->interface;
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- break;
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- }
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-
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mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
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mcr_new = mcr_cur;
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mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
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@@ -2771,17 +2734,10 @@ static void mt753x_phylink_mac_link_up(s
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mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
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- /* MT753x MAC works in 1G full duplex mode for all up-clocked
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- * variants.
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- */
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- if (interface == PHY_INTERFACE_MODE_TRGMII ||
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- (phy_interface_mode_is_8023z(interface))) {
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- speed = SPEED_1000;
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- duplex = DUPLEX_FULL;
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- }
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-
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switch (speed) {
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case SPEED_1000:
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+ case SPEED_2500:
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+ case SPEED_10000:
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mcr |= PMCR_FORCE_SPEED_1000;
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break;
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case SPEED_100:
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@@ -2799,6 +2755,7 @@ static void mt753x_phylink_mac_link_up(s
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if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
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switch (speed) {
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case SPEED_1000:
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+ case SPEED_2500:
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mcr |= PMCR_FORCE_EEE1G;
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break;
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case SPEED_100:
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@@ -2810,61 +2767,6 @@ static void mt753x_phylink_mac_link_up(s
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mt7530_set(priv, MT7530_PMCR_P(port), mcr);
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}
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-static int
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-mt7531_cpu_port_config(struct dsa_switch *ds, int port)
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-{
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- struct mt7530_priv *priv = ds->priv;
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- phy_interface_t interface;
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- int speed;
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-
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- switch (port) {
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- case 5:
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- if (!priv->p5_sgmii)
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- interface = PHY_INTERFACE_MODE_RGMII;
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- else
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- interface = PHY_INTERFACE_MODE_2500BASEX;
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-
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- priv->p5_interface = interface;
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- break;
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- case 6:
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- interface = PHY_INTERFACE_MODE_2500BASEX;
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-
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- priv->p6_interface = interface;
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- break;
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- default:
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- return -EINVAL;
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- }
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-
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- if (interface == PHY_INTERFACE_MODE_2500BASEX)
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- speed = SPEED_2500;
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- else
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- speed = SPEED_1000;
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-
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- mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
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-
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- mt7530_write(priv, MT7530_PMCR_P(port),
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- PMCR_CPU_PORT_SETTING(priv->id));
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- mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
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- speed, DUPLEX_FULL, true, true);
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-
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- return 0;
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-}
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-
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-static int
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-mt7988_cpu_port_config(struct dsa_switch *ds, int port)
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-{
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- struct mt7530_priv *priv = ds->priv;
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-
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- mt7530_write(priv, MT7530_PMCR_P(port),
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- PMCR_CPU_PORT_SETTING(priv->id));
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-
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- mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
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- PHY_INTERFACE_MODE_INTERNAL, NULL,
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- SPEED_10000, DUPLEX_FULL, true, true);
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-
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- return 0;
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-}
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-
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static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
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struct phylink_config *config)
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{
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@@ -3122,7 +3024,6 @@ const struct mt753x_info mt753x_table[]
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.sw_setup = mt7531_setup,
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.phy_read = mt7531_ind_phy_read,
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.phy_write = mt7531_ind_phy_write,
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- .cpu_port_config = mt7531_cpu_port_config,
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.mac_port_get_caps = mt7531_mac_port_get_caps,
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.mac_port_config = mt7531_mac_config,
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},
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@@ -3132,7 +3033,6 @@ const struct mt753x_info mt753x_table[]
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.sw_setup = mt7988_setup,
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.phy_read = mt7531_ind_phy_read,
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.phy_write = mt7531_ind_phy_write,
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- .cpu_port_config = mt7988_cpu_port_config,
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.mac_port_get_caps = mt7988_mac_port_get_caps,
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},
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};
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -331,13 +331,6 @@ enum mt7530_vlan_port_acc_frm {
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PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
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PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
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PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
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-#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
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- PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
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- PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
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- PMCR_TX_EN | PMCR_RX_EN | \
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- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
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- PMCR_FORCE_SPEED_1000 | \
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- PMCR_FORCE_FDX | PMCR_FORCE_LNK)
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#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
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#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
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@@ -737,7 +730,6 @@ struct mt753x_info {
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int (*sw_setup)(struct dsa_switch *ds);
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int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
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int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
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- int (*cpu_port_config)(struct dsa_switch *ds, int port);
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void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
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struct phylink_config *config);
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void (*mac_port_validate)(struct dsa_switch *ds, int port,
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@@ -763,7 +755,6 @@ struct mt753x_info {
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* @ports: Holding the state among ports
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* @reg_mutex: The lock for protecting among process accessing
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* registers
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- * @p6_interface Holding the current port 6 interface
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* @p5_intf_sel: Holding the current port 5 interface select
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* @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
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* has got SGMII
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@@ -785,8 +776,6 @@ struct mt7530_priv {
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const struct mt753x_info *info;
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unsigned int id;
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bool mcm;
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- phy_interface_t p6_interface;
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- phy_interface_t p5_interface;
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enum p5_interface_select p5_intf_sel;
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bool p5_sgmii;
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u8 mirror_rx;
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