From 8e4cbfc8b1b86479a4bc64d6034449096d0af3a1 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Thu, 26 Sep 2019 17:00:26 +0800
Subject: [PATCH] drm: imx: mhdp: add dual mode support for imx8qm

Add dual mode support for imx8qm.
imx8qm hdmi/dp driver are ready to support 4K.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c   |  4 ----
 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c |  6 -----
 drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c           | 30 +++++++++++++++++++------
 drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c           |  3 +--
 drivers/gpu/drm/imx/cdns-mhdp-imx.h             | 14 +-----------
 5 files changed, 25 insertions(+), 32 deletions(-)

--- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
@@ -118,9 +118,6 @@ static void cdns_dp_mode_set(struct cdns
 
 	memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
 
-	//Sandor TODO
-//	mhdp->dual_mode = video_is_dual_mode(mode);
-
 	dp_pixel_clk_reset(mhdp);
 
 	cdns_mhdp_plat_call(mhdp, pclk_rate);
@@ -450,7 +447,6 @@ static int __cdns_dp_probe(struct platfo
 
 	cdns_mhdp_plat_call(mhdp, power_on);
 
-//	mhdp->dual_mode = false;
 	cdns_mhdp_plat_call(mhdp, firmware_init);
 
 	/* DP FW alive check */
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -343,9 +343,6 @@ static void cdns_hdmi_bridge_mode_set(st
 
 	memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
 
-	//Sandor TODO
-//	hdmi->dual_mode = video_is_dual_mode(mode);
-
 	hdmi_lanes_config(mhdp);
 
 	cdns_mhdp_plat_call(mhdp, pclk_rate);
@@ -446,9 +443,6 @@ static int __cdns_hdmi_probe(struct plat
 		return -EPROBE_DEFER;
 	}
 
-	/* Initialize dual_mode to false */
-//	hdmi->dual_mode = false;
-
 	cdns_mhdp_plat_call(mhdp, power_on);
 
 	/* Initialize FW */
--- a/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
+++ b/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
@@ -13,19 +13,32 @@
 
 #include "cdns-mhdp-imx.h"
 
+#define PLL_800MHZ (800000000)
+
+#define HDP_DUAL_MODE_MIN_PCLK_RATE	300000	/* KHz */
+#define HDP_SINGLE_MODE_MAX_WIDTH	1920
+
 #define CSR_PIXEL_LINK_MUX_CTL		0x00
 #define CSR_PIXEL_LINK_MUX_VCP_OFFSET		5
 #define CSR_PIXEL_LINK_MUX_HCP_OFFSET		4
 
-#define PLL_800MHZ (800000000)
+static bool imx8qm_video_dual_mode(struct cdns_mhdp_device *mhdp)
+{
+	struct drm_display_mode *mode = &mhdp->mode;
+	return (mode->clock > HDP_DUAL_MODE_MIN_PCLK_RATE ||
+		mode->hdisplay > HDP_SINGLE_MODE_MAX_WIDTH) ? true : false;
+}
 
 static void imx8qm_pixel_link_mux(struct imx_mhdp_device *imx_mhdp)
 {
 	struct drm_display_mode *mode = &imx_mhdp->mhdp.mode;
+	bool dual_mode;
 	u32 val;
 
+	dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
+
 	val = 0x4;	/* RGB */
-	if (imx_mhdp->dual_mode)
+	if (dual_mode)
 		val |= 0x2;	/* pixel link 0 and 1 are active */
 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 		val |= 1 << CSR_PIXEL_LINK_MUX_VCP_OFFSET;
@@ -276,12 +289,13 @@ static void imx8qm_pixel_clk_disable(str
 
 static void imx8qm_pixel_clk_set_rate(struct imx_mhdp_device *imx_mhdp, u32 pclock)
 {
+	bool dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
 	struct imx_hdp_clks *clks = &imx_mhdp->clks;
 
 	/* pixel clock for HDMI */
 	clk_set_rate(clks->av_pll, pclock);
 
-	if (imx_mhdp->dual_mode == true) {
+	if (dual_mode == true) {
 		clk_set_rate(clks->clk_pxl, pclock/2);
 		clk_set_rate(clks->clk_pxl_link, pclock/2);
 	} else {
@@ -471,18 +485,20 @@ void cdns_mhdp_plat_init_imx8qm(struct c
 {
 	struct imx_mhdp_device *imx_mhdp =
 				container_of(mhdp, struct imx_mhdp_device, mhdp);
+	bool dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
 
-	imx8qm_pixel_link_sync_disable(imx_mhdp->dual_mode);
-	imx8qm_pixel_link_invalid(imx_mhdp->dual_mode);
+	imx8qm_pixel_link_sync_disable(dual_mode);
+	imx8qm_pixel_link_invalid(dual_mode);
 }
 
 void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp)
 {
 	struct imx_mhdp_device *imx_mhdp =
 				container_of(mhdp, struct imx_mhdp_device, mhdp);
+	bool dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
 
-	imx8qm_pixel_link_valid(imx_mhdp->dual_mode);
-	imx8qm_pixel_link_sync_enable(imx_mhdp->dual_mode);
+	imx8qm_pixel_link_valid(dual_mode);
+	imx8qm_pixel_link_sync_enable(dual_mode);
 }
 
 void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp)
--- a/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
+++ b/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
@@ -172,7 +172,6 @@ static int cdns_mhdp_imx_bind(struct dev
 	if (ret < 0)
 		drm_encoder_cleanup(encoder);
 
-	imx_mhdp->dual_mode = false;
 	return ret;
 }
 
@@ -205,7 +204,7 @@ static struct platform_driver cdns_mhdp_
 	.probe  = cdns_mhdp_imx_probe,
 	.remove = cdns_mhdp_imx_remove,
 	.driver = {
-		.name = "cdn-hdp-imx8qm",
+		.name = "cdns-mhdp-imx",
 		.of_match_table = cdns_mhdp_imx_dt_ids,
 	},
 };
--- a/drivers/gpu/drm/imx/cdns-mhdp-imx.h
+++ b/drivers/gpu/drm/imx/cdns-mhdp-imx.h
@@ -16,15 +16,6 @@
 #include <drm/drm_encoder_slave.h>
 
 
-#define HDP_DUAL_MODE_MIN_PCLK_RATE	300000	/* KHz */
-#define HDP_SINGLE_MODE_MAX_WIDTH	1920
-
-static inline bool video_is_dual_mode(const struct drm_display_mode *mode)
-{
-	return (mode->clock > HDP_DUAL_MODE_MIN_PCLK_RATE ||
-		mode->hdisplay > HDP_SINGLE_MODE_MAX_WIDTH) ? true : false;
-}
-
 struct imx_mhdp_device;
 
 struct imx_hdp_clks {
@@ -62,17 +53,14 @@ struct imx_mhdp_device {
 
 	int bus_type;
 
-	u32 dual_mode;
-
 	struct device		*pd_mhdp_dev;
 	struct device		*pd_pll0_dev;
 	struct device		*pd_pll1_dev;
 	struct device_link	*pd_mhdp_link;
 	struct device_link	*pd_pll0_link;
 	struct device_link	*pd_pll1_link;
-
-//	u32 phy_init;
 };
+
 void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp);
 void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp);
 void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp);
