forked from freifunk-franken/firmware
Fabian Bläse
774eeade04
Device support is based on the patch set linked in the OpenWrt Wiki. [1][2] The aux-loader blob is not included, as it is only required for initial installation. Two additional kernel patches for mvpp2 are added to allow receive hashing to work properly in the DSA setup of the device. [1] https://openwrt.org/toh/mikrotik/rb5009ug_s_in#installation [2] https://paste.myconan.net/482114 Signed-off-by: Fabian Bläse <fabian@blaese.de>
119 lines
4.5 KiB
Diff
119 lines
4.5 KiB
Diff
From facbe16f6981dccaf682980a2cb18790d6eae0d2 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 30 Jan 2022 13:03:13 +0100
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Subject: [PATCH 12/18] mvebu: add Amethyst specific SMI setup
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Amethyst switches require different external SMI GPIO setup then other
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switches, so provide it since RB5009 uses the external SMI bus.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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...x-add-Amethyst-specific-SMI-GPIO-fun.patch | 95 +++++++++++++++++++
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1 file changed, 95 insertions(+)
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create mode 100644 target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch
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diff --git a/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch b/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch
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new file mode 100644
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index 0000000000..248b8b9d6c
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--- /dev/null
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+++ b/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch
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@@ -0,0 +1,95 @@
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+From 40aa82107e7b1e7f20cbf6e644005c0c606f9f79 Mon Sep 17 00:00:00 2001
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+From: Robert Marko <robimarko@gmail.com>
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+Date: Fri, 14 Jan 2022 15:17:37 +0100
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+Subject: [PATCH] net: dsa: mv88e6xxx: add Amethyst specific SMI GPIO function
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+
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+The existing mv88e6xxx_g2_scratch_gpio_set_smi() cannot be used on the
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+88E6393X as it requires certain P0_MODE, it also checks the CPU mode
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+as it impacts the bit setting value.
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+
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+This is all irrelevant for Amethyst (MV88E6191X/6193X/6393X) as only
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+the default value of the SMI_PHY Config bit is set to CPU_MGD bootstrap
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+pin value but it can be changed without restrictions so that GPIO pins
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+9 and 10 are used as SMI pins.
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+
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+So, introduce Amethyst specific function and call that if the Amethyst
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+family wants to setup the external PHY.
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+
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+Signed-off-by: Robert Marko <robimarko@gmail.com>
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+---
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+ drivers/net/dsa/mv88e6xxx/chip.c | 5 +++-
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+ drivers/net/dsa/mv88e6xxx/global2.h | 2 ++
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+ drivers/net/dsa/mv88e6xxx/global2_scratch.c | 31 +++++++++++++++++++++
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+ 3 files changed, 37 insertions(+), 1 deletion(-)
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+
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+diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
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+index 43d126628610..b3803101d612 100644
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+--- a/drivers/net/dsa/mv88e6xxx/chip.c
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++++ b/drivers/net/dsa/mv88e6xxx/chip.c
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+@@ -3409,7 +3409,10 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
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+
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+ if (external) {
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+ mv88e6xxx_reg_lock(chip);
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+- err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
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++ if (chip->info->family == MV88E6XXX_FAMILY_6393)
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++ err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
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++ else
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++ err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
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+ mv88e6xxx_reg_unlock(chip);
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+
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+ if (err)
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+diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h
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+index f3e27573a386..e0649f21f28e 100644
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+--- a/drivers/net/dsa/mv88e6xxx/global2.h
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++++ b/drivers/net/dsa/mv88e6xxx/global2.h
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+@@ -370,6 +370,8 @@ extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
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+
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+ int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
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+ bool external);
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++int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
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++ bool external);
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+ int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
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+ int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
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+
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+diff --git a/drivers/net/dsa/mv88e6xxx/global2_scratch.c b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
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+index eda710062933..dc3f4645fa52 100644
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+--- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c
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++++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
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+@@ -289,3 +289,34 @@ int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
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+
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+ return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);
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+ }
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++
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++/**
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++ * mv88e6393x_g2_scratch_gpio_set_smi - set gpio muxing for external smi
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++ * @chip: chip private data
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++ * @external: set mux for external smi, or free for gpio usage
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++ *
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++ * MV88E6191X/6193X/6393X GPIO pins 9 and 10 can be configured as an
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++ * external SMI interface or as regular GPIO-s.
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++ *
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++ * They however have a different register layout then the existing
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++ * function.
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++ */
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++
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++int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
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++ bool external)
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++{
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++ int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG;
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++ int err;
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++ u8 val;
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++
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++ err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val);
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++ if (err)
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++ return err;
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++
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++ if (external)
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++ val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
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++ else
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++ val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
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++
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++ return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);
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++}
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+--
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+2.34.1
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+
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--
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2.42.1
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