From 4994d15a2708e3c2e5df3d91061a4899cb44a979 Mon Sep 17 00:00:00 2001 From: Serhii Serhieiev Date: Wed, 9 Feb 2022 09:45:47 +0200 Subject: [PATCH 03/18] mvebu: mvebu: add support for RB5009UG+S+IN. This patch adds support for Mikrotik RB5009UG+S+IN. Specifications: - SoC: Marvell Armada 7040 (88F7040) - 4 cores, ARMv8, 1.4GHz, 64bit - RAM: 1024MB DDR4 - Flash: 16MB SPI NOR flash, 1024MB NAND - Ethernet: One Marvell 88E6393X - Amethyst: one 2.5G + seven 1G ports and one SFP+ - LED: User, SFP, Hdr1, Hdr2 - Buttons: Reset - UART: 115200 8n1 - USB: One USB3 port Signed-off-by: Serhii Serhieiev --- .../base-files/etc/board.d/02_network | 3 + .../base-files/lib/upgrade/platform.sh | 4 + .../boot/dts/marvell/armada-7040-rb5009.dts | 377 ++++++++++++++++++ 3 files changed, 384 insertions(+) create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network index 6a5861084e..ccb89add24 100644 --- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network +++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network @@ -32,6 +32,9 @@ marvell,armada7040-db) marvell,armada8040-clearfog-gt-8k) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 eth2" "eth0 eth1" ;; +mikrotik,rb5009) + ucidef_set_interfaces_lan_wan "p2 p3 p4 p5 p6 p7 p8" "sfp p1" + ;; *) ucidef_set_interface_lan "eth0" ;; diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh index dc964a3117..d61e937cdc 100755 --- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh +++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh @@ -35,6 +35,10 @@ platform_do_upgrade() { marvell,armada8040-clearfog-gt-8k) legacy_sdcard_do_upgrade "$1" ;; + mikrotik,rb5009) + PART_NAME=firmware + default_do_upgrade "$1" + ;; *) default_do_upgrade "$1" ;; diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts new file mode 100644 index 0000000000..66c74451f0 --- /dev/null +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "armada-7040.dtsi" +#include +#include + +/ { + model = "MikroTik RB5009"; + compatible = "mikrotik,rb5009", "marvell,armada7040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + aliases { + led-boot = &led_user; + led-failsafe = &led_user; + led-running = &led_user; + led-upgrade = &led_user; + }; + + sfp_i2c: sfp-i2c { + compatible = "i2c-gpio"; + sda-gpios = <&cp0_gpio1 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&cp0_gpio1 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&cp0_gpio1 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_user: user { + label = "green:user"; + gpios = <&cp0_gpio2 26 GPIO_ACTIVE_LOW>; + }; + + sfp { + label = "green:sfp"; + gpios = <&cp0_gpio2 25 GPIO_ACTIVE_LOW>; + }; + + hdr1 { + label = "blue:hdr1"; + gpios = <&cp0_gpio1 4 GPIO_ACTIVE_LOW>; + }; + + hdr2 { + label = "blue:hdr2"; + gpios = <&cp0_gpio2 19 GPIO_ACTIVE_LOW>; + }; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ATF"; + reg = <0x0 0x95c04>; + read-only; + }; + partition@1 { + label = "backup_RouterBOOT"; + reg = <0x95c04 0x193FC>; + read-only; + }; + hard_config: partition@2 { + label = "hard_config"; + reg = <0xaf000 0x1000>; + read-only; + }; + partition@3 { + label = "RouterBOOT"; + reg = <0xb0000 0x10000>; + }; + partition@4 { + label = "soft_config"; + reg = <0xc0000 0x10000>; + }; + partition@5 { + label = "DTS"; + reg = <0xd0000 0x10000>; + read-only; + }; + partition@6 { + label = "free_space"; + reg = <0xe0000 0x20000>; + }; + partition@7 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x100000 0xf00000>; + }; + partition@8 { + label = "first_1M"; + reg = <0x0 0x100000>; + }; + }; + }; +}; + +&cp0_nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + nand-rb = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RouterBoard NAND Boot"; + reg = <0x0 0x800000>; + }; + + partition@800000 { + label = "RouterBoard NAND Main"; + reg = <0x800000 0x3f800000>; + }; + }; + }; +}; + +&cp0_gpio2 { + enable-usb-power { + gpio-hog; + gpios = <23 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "enable USB power"; + }; + + enable-leds-power { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "enable LED-s power"; + }; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +&cp0_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cp0_mdio { + status = "okay"; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + /* This port is connected to 88E6393X switch */ + status = "okay"; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <0>; +}; + +&cp0_mdio { + status = "okay"; + + switch@0 { + /* Actual device is MV88E6393X */ + compatible = "marvell,mv88e6190"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + //strict-cpu-mode = <1>; + //reset-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&cp0_eth0>; + }; + + port@1 { + reg = <1>; + label = "p8"; + phy-handle = <&switch0phy1>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <7>; + }; + + port@2 { + reg = <2>; + label = "p7"; + phy-handle = <&switch0phy2>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <6>; + }; + + port@3 { + reg = <3>; + label = "p6"; + phy-handle = <&switch0phy3>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <5>; + }; + + port@4 { + reg = <4>; + label = "p5"; + phy-handle = <&switch0phy4>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <4>; + }; + + port@5 { + reg = <5>; + label = "p4"; + phy-handle = <&switch0phy5>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <3>; + }; + + port@6 { + reg = <6>; + label = "p3"; + phy-handle = <&switch0phy6>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <2>; + }; + + port@7 { + reg = <7>; + label = "p2"; + phy-handle = <&switch0phy7>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + }; + + port@9 { + reg = <9>; + label = "p1"; + phy-mode = "sgmii"; + phy-handle = <&switch0phy9>; + managed = "in-band-status"; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <0>; + }; + + port@a { + reg = <10>; + label = "sfp"; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + sfp = <&sfp>; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <8>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy1: switch0phy1@1 { + reg = <0x1>; + }; + + switch0phy2: switch0phy2@2 { + reg = <0x2>; + }; + + switch0phy3: switch0phy3@3 { + reg = <0x3>; + }; + + switch0phy4: switch0phy4@4 { + reg = <0x4>; + }; + + switch0phy5: switch0phy5@5 { + reg = <0x5>; + }; + + switch0phy6: switch0phy6@6 { + reg = <0x6>; + }; + + switch0phy7: switch0phy7@7 { + reg = <0x7>; + }; + }; + + mdio1 { + compatible = "marvell,mv88e6xxx-mdio-external"; + #address-cells = <1>; + #size-cells = <0>; + + switch0phy9: switch0phy9@0 { + reg = <0>; + }; + }; + }; +}; + +&hard_config { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_hard: macaddr@10 { + reg = <0x10 0x6>; + }; +}; -- 2.42.1