From 774eeade044f65b1e0c3de189baff42ac683882d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Bl=C3=A4se?= Date: Tue, 26 Dec 2023 17:07:59 +0100 Subject: [PATCH] Add support for Mikrotik RB5009 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Device support is based on the patch set linked in the OpenWrt Wiki. [1][2] The aux-loader blob is not included, as it is only required for initial installation. Two additional kernel patches for mvpp2 are added to allow receive hashing to work properly in the DSA setup of the device. [1] https://openwrt.org/toh/mikrotik/rb5009ug_s_in#installation [2] https://paste.myconan.net/482114 Signed-off-by: Fabian Bläse --- bsp/mvebu-cortexa72.bsp | 6 + bsp/mvebu-cortexa72/.config | 48 + ...otik-rb_softconfig-work-crc-mismatch.patch | 53 + .../0202-mvebu-add-aux-loader2-support.patch | 70 + ...-mvebu-add-support-for-RB5009UG-S-IN.patch | 439 +++++ .../0204-mvebu-RB5009-start-to-use-UBI.patch | 85 + ...5009-remove-sfp-port-from-wan-bridge.patch | 29 + .../0207-mvebu-rb5009-add-SFP-GPIO-pins.patch | 32 + ...-QCA8081-label-for-2.5-GbE-port-in-D.patch | 39 + ...9-mvebu-cortexa72-add-missing-symbol.patch | 24 + ...enable-SBSA-Watchdog-Mikrotik-RB-Sys.patch | 35 + ...a72-performance-as-default-scheduler.patch | 30 + ...vebu-add-Amethyst-specific-SMI-setup.patch | 118 ++ ...el-5.15-backport-QCA8081-PHY-support.patch | 1626 +++++++++++++++++ ...009-add-QCA8081-PHY-support-for-5.15.patch | 29 + ...port-5.18-AT803x-fiber-support-patch.patch | 154 ++ ...at803x-null-pointer-fix-with-upstrea.patch | 70 + ...CA8081-2.5Gb-patch-with-upstream-one.patch | 172 ++ ...kernel-5.15-refresh-RB5009UG-patches.patch | 890 +++++++++ .../0299-mvpp2-enable-dsa-parser-entry.patch | 41 + .../openwrt/0299-mvpp2-vlan-after-dsa.patch | 30 + .../aarch64/network.mikrotik,rb5009 | 6 + .../files/etc/hotplug.d/net/40-net-rss | 6 + .../files/etc/uci-defaults/50-packet-steering | 5 + 24 files changed, 4037 insertions(+) create mode 100644 bsp/mvebu-cortexa72.bsp create mode 100644 bsp/mvebu-cortexa72/.config create mode 100644 build_patches/openwrt/0201-generic-fix-mikrotik-rb_softconfig-work-crc-mismatch.patch create mode 100644 build_patches/openwrt/0202-mvebu-add-aux-loader2-support.patch create mode 100644 build_patches/openwrt/0203-mvebu-mvebu-add-support-for-RB5009UG-S-IN.patch create mode 100644 build_patches/openwrt/0204-mvebu-RB5009-start-to-use-UBI.patch create mode 100644 build_patches/openwrt/0206-mvebu-RB5009-remove-sfp-port-from-wan-bridge.patch create mode 100644 build_patches/openwrt/0207-mvebu-rb5009-add-SFP-GPIO-pins.patch create mode 100644 build_patches/openwrt/0208-mvebu-rb5009-use-QCA8081-label-for-2.5-GbE-port-in-D.patch create mode 100644 build_patches/openwrt/0209-mvebu-cortexa72-add-missing-symbol.patch create mode 100644 build_patches/openwrt/0210-mvebu-cortexa72-enable-SBSA-Watchdog-Mikrotik-RB-Sys.patch create mode 100644 build_patches/openwrt/0211-mvebu-cortexa72-performance-as-default-scheduler.patch create mode 100644 build_patches/openwrt/0212-mvebu-add-Amethyst-specific-SMI-setup.patch create mode 100644 build_patches/openwrt/0213-kernel-5.15-backport-QCA8081-PHY-support.patch create mode 100644 build_patches/openwrt/0214-mvebu-rb5009-add-QCA8081-PHY-support-for-5.15.patch create mode 100644 build_patches/openwrt/0215-generic-backport-5.18-AT803x-fiber-support-patch.patch create mode 100644 build_patches/openwrt/0216-generic-replace-at803x-null-pointer-fix-with-upstrea.patch create mode 100644 build_patches/openwrt/0217-kernel-replace-QCA8081-2.5Gb-patch-with-upstream-one.patch create mode 100644 build_patches/openwrt/0218-kernel-5.15-refresh-RB5009UG-patches.patch create mode 100644 build_patches/openwrt/0299-mvpp2-enable-dsa-parser-entry.patch create mode 100644 build_patches/openwrt/0299-mvpp2-vlan-after-dsa.patch create mode 100644 src/packages/fff/fff-network/aarch64/network.mikrotik,rb5009 create mode 100644 src/packages/fff/fff-network/files/etc/hotplug.d/net/40-net-rss diff --git a/bsp/mvebu-cortexa72.bsp b/bsp/mvebu-cortexa72.bsp new file mode 100644 index 00000000..f10d399c --- /dev/null +++ b/bsp/mvebu-cortexa72.bsp @@ -0,0 +1,6 @@ +chipset=mvebu +subtarget=cortexa72 + +images=( + "openwrt-mvebu-cortexa72-mikrotik_rb5009-squashfs*" + ) diff --git a/bsp/mvebu-cortexa72/.config b/bsp/mvebu-cortexa72/.config new file mode 100644 index 00000000..be49ffb1 --- /dev/null +++ b/bsp/mvebu-cortexa72/.config @@ -0,0 +1,48 @@ +# Generated using "./buildscript config openwrt". +# Do no edit manually +# +CONFIG_TARGET_mvebu=y +CONFIG_TARGET_mvebu_cortexa72=y +CONFIG_TARGET_MULTI_PROFILE=y +CONFIG_TARGET_DEVICE_mvebu_cortexa72_DEVICE_mikrotik_rb5009=y +CONFIG_TARGET_DEVICE_PACKAGES_mvebu_cortexa72_DEVICE_mikrotik_rb5009="" +CONFIG_BUSYBOX_CUSTOM=y +CONFIG_TARGET_PER_DEVICE_ROOTFS=y +# CONFIG_BUSYBOX_CONFIG_BRCTL is not set +# CONFIG_BUSYBOX_CONFIG_CHGRP is not set +# CONFIG_BUSYBOX_CONFIG_CHOWN is not set +# CONFIG_BUSYBOX_CONFIG_CROND is not set +# CONFIG_BUSYBOX_CONFIG_CRONTAB is not set +# CONFIG_BUSYBOX_CONFIG_FEATURE_FAST_TOP is not set +# CONFIG_BUSYBOX_CONFIG_FEATURE_NTPD_SERVER is not set +# CONFIG_BUSYBOX_CONFIG_IFCONFIG is not set +# CONFIG_BUSYBOX_CONFIG_IP is not set +# CONFIG_BUSYBOX_CONFIG_MKSWAP is not set +# CONFIG_BUSYBOX_CONFIG_ROUTE is not set +# CONFIG_BUSYBOX_CONFIG_SWAPOFF is not set +# CONFIG_BUSYBOX_CONFIG_SWAPON is not set +CONFIG_CLEAN_IPKG=y +# CONFIG_DROPBEAR_CURVE25519 is not set +# CONFIG_FASTD_ENABLE_CIPHER_SALSA2012 is not set +# CONFIG_FASTD_ENABLE_MAC_GHASH is not set +# CONFIG_FASTD_ENABLE_MAC_UHASH is not set +# CONFIG_FASTD_ENABLE_METHOD_COMPOSED_GMAC is not set +# CONFIG_FASTD_ENABLE_METHOD_COMPOSED_UMAC is not set +# CONFIG_FASTD_ENABLE_METHOD_GENERIC_GMAC is not set +# CONFIG_FASTD_ENABLE_METHOD_GENERIC_UMAC is not set +# CONFIG_PACKAGE_ALFRED_VIS is not set +CONFIG_PACKAGE_fff-extra=y +CONFIG_PACKAGE_libuclient=m +CONFIG_PACKAGE_libwolfssl=m +CONFIG_PACKAGE_opkg=m +CONFIG_PACKAGE_uclient-fetch=m +CONFIG_PACKAGE_wpad-basic=y +CONFIG_PACKAGE_wpad-basic-wolfssl=m +CONFIG_STRIP_KERNEL_EXPORTS=y +# CONFIG_TARGET_ROOTFS_EXT4FS is not set +CONFIG_TARGET_SQUASHFS_BLOCK_SIZE=512 +# CONFIG_LIBCURL_FILE is not set +# CONFIG_LIBCURL_FTP is not set +# CONFIG_LIBCURL_PROXY is not set +# CONFIG_LIBCURL_UNIX_SOCKETS is not set +# CONFIG_HTOP_LMSENSORS is not set diff --git a/build_patches/openwrt/0201-generic-fix-mikrotik-rb_softconfig-work-crc-mismatch.patch b/build_patches/openwrt/0201-generic-fix-mikrotik-rb_softconfig-work-crc-mismatch.patch new file mode 100644 index 00000000..5ef6c051 --- /dev/null +++ b/build_patches/openwrt/0201-generic-fix-mikrotik-rb_softconfig-work-crc-mismatch.patch @@ -0,0 +1,53 @@ +From ab8d25d5ac1b307dacdc3e5e44e23248f4b9a018 Mon Sep 17 00:00:00 2001 +From: Serhii Serhieiev +Date: Wed, 9 Feb 2022 09:07:57 +0200 +Subject: [PATCH 01/18] generic: fix mikrotik/rb_softconfig work(crc mismatch) + with 64K block size + +Signed-off-by: Serhii Serhieiev +--- + .../files/drivers/platform/mikrotik/rb_softconfig.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/target/linux/generic/files/drivers/platform/mikrotik/rb_softconfig.c b/target/linux/generic/files/drivers/platform/mikrotik/rb_softconfig.c +index 5acff6aa91..2332089a46 100644 +--- a/target/linux/generic/files/drivers/platform/mikrotik/rb_softconfig.c ++++ b/target/linux/generic/files/drivers/platform/mikrotik/rb_softconfig.c +@@ -58,6 +58,7 @@ + + #define RB_SOFTCONFIG_VER "0.05" + #define RB_SC_PR_PFX "[rb_softconfig] " ++#define SOFT_CONF_FIXED_SIZE 0x1000 + + #define RB_SC_HAS_WRITE_SUPPORT true + #define RB_SC_WMODE S_IWUSR +@@ -636,7 +637,7 @@ static ssize_t sc_commit_store(struct kobject *kobj, struct kobj_attribute *attr + + write_lock(&sc_bufrwl); + if (!flush) // reread +- ret = mtd_read(mtd, 0, mtd->size, &bytes_rw, sc_buf); ++ ret = mtd_read(mtd, 0, sc_buflen, &bytes_rw, sc_buf); + else { // crc32 + commit + /* + * CRC32 is computed on the entire buffer, excluding the CRC +@@ -658,7 +659,7 @@ static ssize_t sc_commit_store(struct kobject *kobj, struct kobj_attribute *attr + ei.len = mtd->size; + ret = mtd_erase(mtd, &ei); + if (!ret) +- ret = mtd_write(mtd, 0, mtd->size, &bytes_rw, sc_buf); ++ ret = mtd_write(mtd, 0, sc_buflen, &bytes_rw, sc_buf); + + /* + * Handling mtd_write() failure here is a tricky situation. The +@@ -708,7 +709,7 @@ int rb_softconfig_init(struct kobject *rb_kobj, struct mtd_info *mtd) + if (ret) + return -ENODEV; + +- sc_buflen = mtd->size; ++ sc_buflen = mtd->size > SOFT_CONF_FIXED_SIZE ? SOFT_CONF_FIXED_SIZE : mtd->size; + sc_buf = kmalloc(sc_buflen, GFP_KERNEL); + if (!sc_buf) { + __put_mtd_device(mtd); +-- +2.42.1 + diff --git a/build_patches/openwrt/0202-mvebu-add-aux-loader2-support.patch b/build_patches/openwrt/0202-mvebu-add-aux-loader2-support.patch new file mode 100644 index 00000000..203483f2 --- /dev/null +++ b/build_patches/openwrt/0202-mvebu-add-aux-loader2-support.patch @@ -0,0 +1,70 @@ +From d1b6214aadbce601ebf54e8f673bbf427b4e33ec Mon Sep 17 00:00:00 2001 +From: Serhii Serhieiev +Date: Wed, 9 Feb 2022 09:32:30 +0200 +Subject: [PATCH 02/18] mvebu: add aux-loader2 support + +This auxiliary bootloader implements the ability to run the OpenWrt Linux kernel(FIT image) +from the RouterBOOT. The thing is that RouterBOOT is able to load ONLY program code in ELF format. +To bypass this restriction, the auxiliary bootloader extends the capabilities of the RouterBOOT - +by adding support for loading system from FIT images. + +Source code is available under GPLv2: https://github.com/adron-s/aux-loader2 + +Signed-off-by: Serhii Serhieiev +[fabian@blaese.de: Remove aux-loader blob, as it is only required for initial installation] +Signed-off-by: Fabian Bläse +--- + target/linux/mvebu/image/Makefile | 12 ++++++++++++ + target/linux/mvebu/image/cortexa72.mk | 19 +++++++++++++++++++ + 2 files changed, 25 insertions(+) + +diff --git a/target/linux/mvebu/image/Makefile b/target/linux/mvebu/image/Makefile +index 57129d2dcb..180b909cbd 100644 +--- a/target/linux/mvebu/image/Makefile ++++ b/target/linux/mvebu/image/Makefile +@@ -162,6 +162,12 @@ define Build/uDPU-firmware + -f $(KDIR_TMP)/$(DEVICE_IMG_PREFIX)-firmware.tgz -C $@-fw . + endef + ++define Device/FitImageLzma ++ KERNEL_SUFFIX := -fit-uImage.itb ++ KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb | pad-to 64k ++ KERNEL_NAME := Image ++endef ++ + define Device/Default + PROFILES := Default + DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1))) +diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk +index 7f344f1de2..fc4712a597 100644 +--- a/target/linux/mvebu/image/cortexa72.mk ++++ b/target/linux/mvebu/image/cortexa72.mk +@@ -52,6 +52,25 @@ define Device/marvell_macchiatobin-singleshot + endef + TARGET_DEVICES += marvell_macchiatobin-singleshot + ++define Device/mikrotik_rb5009 ++ DEVICE_DTS := armada-7040-rb5009 ++ DEVICE_DTS_DIR := $(DTS_DIR)/marvell ++ $(call Device/FitImageLzma) ++ DEVICE_VENDOR := MikroTik ++ DEVICE_MODEL := RB5009 ++ SOC := armada-7040 ++ KERNEL_LOADADDR := 0x22000000 ++ KERNEL_INITRAMFS = $$(KERNEL) ++ KERNEL_INITRAMFS_SUFFIX := -fit-uImage.elf ++ BLOCKSIZE := 64k ++ IMAGE_SIZE := 15360k ++ IMAGES := sysupgrade.bin ++ IMAGE/sysupgrade.bin := append-kernel | pad-to $$(BLOCKSIZE) | \ ++ append-rootfs | pad-rootfs | check-size | append-metadata ++ DEVICE_PACKAGES += kmod-i2c-gpio ++endef ++TARGET_DEVICES += mikrotik_rb5009 ++ + define Device/marvell_clearfog-gt-8k + $(call Device/Default-arm64) + DEVICE_VENDOR := SolidRun +-- +2.42.1 + diff --git a/build_patches/openwrt/0203-mvebu-mvebu-add-support-for-RB5009UG-S-IN.patch b/build_patches/openwrt/0203-mvebu-mvebu-add-support-for-RB5009UG-S-IN.patch new file mode 100644 index 00000000..65ea3239 --- /dev/null +++ b/build_patches/openwrt/0203-mvebu-mvebu-add-support-for-RB5009UG-S-IN.patch @@ -0,0 +1,439 @@ +From 4994d15a2708e3c2e5df3d91061a4899cb44a979 Mon Sep 17 00:00:00 2001 +From: Serhii Serhieiev +Date: Wed, 9 Feb 2022 09:45:47 +0200 +Subject: [PATCH 03/18] mvebu: mvebu: add support for RB5009UG+S+IN. + +This patch adds support for Mikrotik RB5009UG+S+IN. + +Specifications: + - SoC: Marvell Armada 7040 (88F7040) - 4 cores, ARMv8, 1.4GHz, 64bit + - RAM: 1024MB DDR4 + - Flash: 16MB SPI NOR flash, 1024MB NAND + - Ethernet: One Marvell 88E6393X - Amethyst: one 2.5G + seven 1G ports and one SFP+ + - LED: User, SFP, Hdr1, Hdr2 + - Buttons: Reset + - UART: 115200 8n1 + - USB: One USB3 port +Signed-off-by: Serhii Serhieiev +--- + .../base-files/etc/board.d/02_network | 3 + + .../base-files/lib/upgrade/platform.sh | 4 + + .../boot/dts/marvell/armada-7040-rb5009.dts | 377 ++++++++++++++++++ + 3 files changed, 384 insertions(+) + create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts + +diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network +index 6a5861084e..ccb89add24 100644 +--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network ++++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network +@@ -32,6 +32,9 @@ marvell,armada7040-db) + marvell,armada8040-clearfog-gt-8k) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 eth2" "eth0 eth1" + ;; ++mikrotik,rb5009) ++ ucidef_set_interfaces_lan_wan "p2 p3 p4 p5 p6 p7 p8" "sfp p1" ++ ;; + *) + ucidef_set_interface_lan "eth0" + ;; +diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh +index dc964a3117..d61e937cdc 100755 +--- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh ++++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh +@@ -35,6 +35,10 @@ platform_do_upgrade() { + marvell,armada8040-clearfog-gt-8k) + legacy_sdcard_do_upgrade "$1" + ;; ++ mikrotik,rb5009) ++ PART_NAME=firmware ++ default_do_upgrade "$1" ++ ;; + *) + default_do_upgrade "$1" + ;; +diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +new file mode 100644 +index 0000000000..66c74451f0 +--- /dev/null ++++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +@@ -0,0 +1,377 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "armada-7040.dtsi" ++#include ++#include ++ ++/ { ++ model = "MikroTik RB5009"; ++ compatible = "mikrotik,rb5009", "marvell,armada7040", ++ "marvell,armada-ap806-quad", "marvell,armada-ap806"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ aliases { ++ led-boot = &led_user; ++ led-failsafe = &led_user; ++ led-running = &led_user; ++ led-upgrade = &led_user; ++ }; ++ ++ sfp_i2c: sfp-i2c { ++ compatible = "i2c-gpio"; ++ sda-gpios = <&cp0_gpio1 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; ++ scl-gpios = <&cp0_gpio1 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&cp0_gpio1 28 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_user: user { ++ label = "green:user"; ++ gpios = <&cp0_gpio2 26 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sfp { ++ label = "green:sfp"; ++ gpios = <&cp0_gpio2 25 GPIO_ACTIVE_LOW>; ++ }; ++ ++ hdr1 { ++ label = "blue:hdr1"; ++ gpios = <&cp0_gpio1 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ hdr2 { ++ label = "blue:hdr2"; ++ gpios = <&cp0_gpio2 19 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ sfp: sfp { ++ compatible = "sff,sfp"; ++ i2c-bus = <&sfp_i2c>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++ ++ pinctrl-0 = <&uart0_pins>; ++ pinctrl-names = "default"; ++}; ++ ++ ++&spi0 { ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <20000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "ATF"; ++ reg = <0x0 0x95c04>; ++ read-only; ++ }; ++ partition@1 { ++ label = "backup_RouterBOOT"; ++ reg = <0x95c04 0x193FC>; ++ read-only; ++ }; ++ hard_config: partition@2 { ++ label = "hard_config"; ++ reg = <0xaf000 0x1000>; ++ read-only; ++ }; ++ partition@3 { ++ label = "RouterBOOT"; ++ reg = <0xb0000 0x10000>; ++ }; ++ partition@4 { ++ label = "soft_config"; ++ reg = <0xc0000 0x10000>; ++ }; ++ partition@5 { ++ label = "DTS"; ++ reg = <0xd0000 0x10000>; ++ read-only; ++ }; ++ partition@6 { ++ label = "free_space"; ++ reg = <0xe0000 0x20000>; ++ }; ++ partition@7 { ++ compatible = "denx,fit"; ++ label = "firmware"; ++ reg = <0x100000 0xf00000>; ++ }; ++ partition@8 { ++ label = "first_1M"; ++ reg = <0x0 0x100000>; ++ }; ++ }; ++ }; ++}; ++ ++&cp0_nand_controller { ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ nand-rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "RouterBoard NAND Boot"; ++ reg = <0x0 0x800000>; ++ }; ++ ++ partition@800000 { ++ label = "RouterBoard NAND Main"; ++ reg = <0x800000 0x3f800000>; ++ }; ++ }; ++ }; ++}; ++ ++&cp0_gpio2 { ++ enable-usb-power { ++ gpio-hog; ++ gpios = <23 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "enable USB power"; ++ }; ++ ++ enable-leds-power { ++ gpio-hog; ++ gpios = <27 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "enable LED-s power"; ++ }; ++}; ++ ++&cp0_usb3_1 { ++ status = "okay"; ++}; ++ ++&cp0_i2c0 { ++ status = "okay"; ++ clock-frequency = <100000>; ++}; ++ ++&cp0_mdio { ++ status = "okay"; ++}; ++ ++&cp0_ethernet { ++ status = "okay"; ++}; ++ ++&cp0_eth0 { ++ /* This port is connected to 88E6393X switch */ ++ status = "okay"; ++ phy-mode = "10gbase-r"; ++ managed = "in-band-status"; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <0>; ++}; ++ ++&cp0_mdio { ++ status = "okay"; ++ ++ switch@0 { ++ /* Actual device is MV88E6393X */ ++ compatible = "marvell,mv88e6190"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ //strict-cpu-mode = <1>; ++ //reset-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "cpu"; ++ ethernet = <&cp0_eth0>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "p8"; ++ phy-handle = <&switch0phy1>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <7>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "p7"; ++ phy-handle = <&switch0phy2>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <6>; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "p6"; ++ phy-handle = <&switch0phy3>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <5>; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ label = "p5"; ++ phy-handle = <&switch0phy4>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <4>; ++ }; ++ ++ port@5 { ++ reg = <5>; ++ label = "p4"; ++ phy-handle = <&switch0phy5>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <3>; ++ }; ++ ++ port@6 { ++ reg = <6>; ++ label = "p3"; ++ phy-handle = <&switch0phy6>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <2>; ++ }; ++ ++ port@7 { ++ reg = <7>; ++ label = "p2"; ++ phy-handle = <&switch0phy7>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <1>; ++ }; ++ ++ port@9 { ++ reg = <9>; ++ label = "p1"; ++ phy-mode = "sgmii"; ++ phy-handle = <&switch0phy9>; ++ managed = "in-band-status"; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <0>; ++ }; ++ ++ port@a { ++ reg = <10>; ++ label = "sfp"; ++ phy-mode = "10gbase-r"; ++ managed = "in-band-status"; ++ sfp = <&sfp>; ++ nvmem-cells = <&macaddr_hard>; ++ nvmem-cell-names = "mac-address"; ++ mac-address-increment = <8>; ++ }; ++ }; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ switch0phy1: switch0phy1@1 { ++ reg = <0x1>; ++ }; ++ ++ switch0phy2: switch0phy2@2 { ++ reg = <0x2>; ++ }; ++ ++ switch0phy3: switch0phy3@3 { ++ reg = <0x3>; ++ }; ++ ++ switch0phy4: switch0phy4@4 { ++ reg = <0x4>; ++ }; ++ ++ switch0phy5: switch0phy5@5 { ++ reg = <0x5>; ++ }; ++ ++ switch0phy6: switch0phy6@6 { ++ reg = <0x6>; ++ }; ++ ++ switch0phy7: switch0phy7@7 { ++ reg = <0x7>; ++ }; ++ }; ++ ++ mdio1 { ++ compatible = "marvell,mv88e6xxx-mdio-external"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ switch0phy9: switch0phy9@0 { ++ reg = <0>; ++ }; ++ }; ++ }; ++}; ++ ++&hard_config { ++ compatible = "nvmem-cells"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ macaddr_hard: macaddr@10 { ++ reg = <0x10 0x6>; ++ }; ++}; +-- +2.42.1 + diff --git a/build_patches/openwrt/0204-mvebu-RB5009-start-to-use-UBI.patch b/build_patches/openwrt/0204-mvebu-RB5009-start-to-use-UBI.patch new file mode 100644 index 00000000..731f4be5 --- /dev/null +++ b/build_patches/openwrt/0204-mvebu-RB5009-start-to-use-UBI.patch @@ -0,0 +1,85 @@ +From ddf04b2773e5316e2b645ee669d172e8a61b2d00 Mon Sep 17 00:00:00 2001 +From: Serhii Serhieiev +Date: Mon, 14 Feb 2022 06:50:56 +0200 +Subject: [PATCH 04/18] mvebu: RB5009: start to use UBI + +Now UBI on a NAND flash drive is used as rootfs. +The kernel is still located on a NOR flash drive in the form of a FIT image. + +Signed-off-by: Serhii Serhieiev +--- + .../cortexa72/base-files/lib/upgrade/platform.sh | 3 +-- + .../arm64/boot/dts/marvell/armada-7040-rb5009.dts | 12 +++--------- + target/linux/mvebu/image/cortexa72.mk | 6 +----- + 3 files changed, 5 insertions(+), 16 deletions(-) + +diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh +index d61e937cdc..55bdfb7264 100755 +--- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh ++++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh +@@ -36,8 +36,7 @@ platform_do_upgrade() { + legacy_sdcard_do_upgrade "$1" + ;; + mikrotik,rb5009) +- PART_NAME=firmware +- default_do_upgrade "$1" ++ nand_do_upgrade "$1" + ;; + *) + default_do_upgrade "$1" +diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +index 66c74451f0..5535f8ad89 100644 +--- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts ++++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +@@ -129,8 +129,7 @@ + reg = <0xe0000 0x20000>; + }; + partition@7 { +- compatible = "denx,fit"; +- label = "firmware"; ++ label = "kernel"; + reg = <0x100000 0xf00000>; + }; + partition@8 { +@@ -158,13 +157,8 @@ + #size-cells = <1>; + + partition@0 { +- label = "RouterBoard NAND Boot"; +- reg = <0x0 0x800000>; +- }; +- +- partition@800000 { +- label = "RouterBoard NAND Main"; +- reg = <0x800000 0x3f800000>; ++ label = "ubi"; ++ reg = <0x0 0x40000000>; + }; + }; + }; +diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk +index fc4712a597..9f872d3afc 100644 +--- a/target/linux/mvebu/image/cortexa72.mk ++++ b/target/linux/mvebu/image/cortexa72.mk +@@ -56,17 +56,13 @@ define Device/mikrotik_rb5009 + DEVICE_DTS := armada-7040-rb5009 + DEVICE_DTS_DIR := $(DTS_DIR)/marvell + $(call Device/FitImageLzma) ++ $(Device/NAND-128K) + DEVICE_VENDOR := MikroTik + DEVICE_MODEL := RB5009 + SOC := armada-7040 + KERNEL_LOADADDR := 0x22000000 + KERNEL_INITRAMFS = $$(KERNEL) + KERNEL_INITRAMFS_SUFFIX := -fit-uImage.elf +- BLOCKSIZE := 64k +- IMAGE_SIZE := 15360k +- IMAGES := sysupgrade.bin +- IMAGE/sysupgrade.bin := append-kernel | pad-to $$(BLOCKSIZE) | \ +- append-rootfs | pad-rootfs | check-size | append-metadata + DEVICE_PACKAGES += kmod-i2c-gpio + endef + TARGET_DEVICES += mikrotik_rb5009 +-- +2.42.1 + diff --git a/build_patches/openwrt/0206-mvebu-RB5009-remove-sfp-port-from-wan-bridge.patch b/build_patches/openwrt/0206-mvebu-RB5009-remove-sfp-port-from-wan-bridge.patch new file mode 100644 index 00000000..646e0c77 --- /dev/null +++ b/build_patches/openwrt/0206-mvebu-RB5009-remove-sfp-port-from-wan-bridge.patch @@ -0,0 +1,29 @@ +From de0624d0317cd14d6eba6b239457de6f2596d1e7 Mon Sep 17 00:00:00 2001 +From: Serhii Serhieiev +Date: Tue, 15 Feb 2022 07:35:09 +0200 +Subject: [PATCH 06/18] mvebu: RB5009: remove sfp port from wan bridge + +The presence of two bridges leads to a conflict between vlans +and Wan ports become inoperative. + +Signed-off-by: Serhii Serhieiev +--- + target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network +index ccb89add24..e1703029be 100644 +--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network ++++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network +@@ -33,7 +33,7 @@ marvell,armada8040-clearfog-gt-8k) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 eth2" "eth0 eth1" + ;; + mikrotik,rb5009) +- ucidef_set_interfaces_lan_wan "p2 p3 p4 p5 p6 p7 p8" "sfp p1" ++ ucidef_set_interfaces_lan_wan "p2 p3 p4 p5 p6 p7 p8 sfp" "p1" + ;; + *) + ucidef_set_interface_lan "eth0" +-- +2.42.1 + diff --git a/build_patches/openwrt/0207-mvebu-rb5009-add-SFP-GPIO-pins.patch b/build_patches/openwrt/0207-mvebu-rb5009-add-SFP-GPIO-pins.patch new file mode 100644 index 00000000..1bdbdf20 --- /dev/null +++ b/build_patches/openwrt/0207-mvebu-rb5009-add-SFP-GPIO-pins.patch @@ -0,0 +1,32 @@ +From daf670f8f34df3169d64f1d9e45453c3b0f61185 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 14 Mar 2022 18:55:25 +0100 +Subject: [PATCH 07/18] mvebu: rb5009: add SFP GPIO pins + +After finally being able to trace them out using a breakout lets add the +required SFP GPIO pins. + +Signed-off-by: Robert Marko +--- + .../files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +index 5535f8ad89..0babac6f08 100644 +--- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts ++++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +@@ -70,6 +70,11 @@ + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; ++ mod-def0-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>; ++ los-gpios = <&cp0_gpio1 2 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&cp0_gpio1 6 GPIO_ACTIVE_HIGH>; ++ tx-disable-gpios = <&cp0_gpio1 5 GPIO_ACTIVE_HIGH>; ++ rate-select0-gpios = <&cp0_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; + +-- +2.42.1 + diff --git a/build_patches/openwrt/0208-mvebu-rb5009-use-QCA8081-label-for-2.5-GbE-port-in-D.patch b/build_patches/openwrt/0208-mvebu-rb5009-use-QCA8081-label-for-2.5-GbE-port-in-D.patch new file mode 100644 index 00000000..fdb90d41 --- /dev/null +++ b/build_patches/openwrt/0208-mvebu-rb5009-use-QCA8081-label-for-2.5-GbE-port-in-D.patch @@ -0,0 +1,39 @@ +From 16969a4451e09d1bd0b7aff2208d514a6bcbf011 Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Tue, 20 Sep 2022 23:05:43 +0200 +Subject: [PATCH 08/18] mvebu: rb5009: use QCA8081 label for 2.5 GbE port in + DTS + +The SFP+ interface is clearly labeled as such in the DTS, +unlike the 2,5 GbE QCA8081. Label it to distinguish it from +the GbE ports as well. Taken from robimarko's tree at +https://github.com/robimarko/openwrt/tree/rb5009-5.15. +--- + .../files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +index 0babac6f08..0c9742d2d8 100644 +--- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts ++++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts +@@ -301,7 +301,7 @@ + reg = <9>; + label = "p1"; + phy-mode = "sgmii"; +- phy-handle = <&switch0phy9>; ++ phy-handle = <&qca8081>; + managed = "in-band-status"; + nvmem-cells = <&macaddr_hard>; + nvmem-cell-names = "mac-address"; +@@ -358,7 +358,7 @@ + #address-cells = <1>; + #size-cells = <0>; + +- switch0phy9: switch0phy9@0 { ++ qca8081: qca8081@0 { + reg = <0>; + }; + }; +-- +2.42.1 + diff --git a/build_patches/openwrt/0209-mvebu-cortexa72-add-missing-symbol.patch b/build_patches/openwrt/0209-mvebu-cortexa72-add-missing-symbol.patch new file mode 100644 index 00000000..8ee17344 --- /dev/null +++ b/build_patches/openwrt/0209-mvebu-cortexa72-add-missing-symbol.patch @@ -0,0 +1,24 @@ +From a4964c4d4d8367d3dbf225efaa4488af76c4e97a Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Wed, 30 Nov 2022 19:23:29 +0100 +Subject: [PATCH 09/18] mvebu: cortexa72: add missing symbol + +--- + target/linux/mvebu/cortexa72/config-5.15 | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15 +index 978208f1cb..27a413c624 100644 +--- a/target/linux/mvebu/cortexa72/config-5.15 ++++ b/target/linux/mvebu/cortexa72/config-5.15 +@@ -93,6 +93,7 @@ CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y + CONFIG_SWIOTLB=y + CONFIG_SYSCTL_EXCEPTION_TRACE=y + CONFIG_THREAD_INFO_IN_TASK=y ++# CONFIG_UCLAMP_TASK is not set + CONFIG_UNMAP_KERNEL_AT_EL0=y + CONFIG_VMAP_STACK=y + CONFIG_ZONE_DMA32=y +-- +2.42.1 + diff --git a/build_patches/openwrt/0210-mvebu-cortexa72-enable-SBSA-Watchdog-Mikrotik-RB-Sys.patch b/build_patches/openwrt/0210-mvebu-cortexa72-enable-SBSA-Watchdog-Mikrotik-RB-Sys.patch new file mode 100644 index 00000000..e53661f2 --- /dev/null +++ b/build_patches/openwrt/0210-mvebu-cortexa72-enable-SBSA-Watchdog-Mikrotik-RB-Sys.patch @@ -0,0 +1,35 @@ +From 3363cd5d3afd161f3a6d1aa94889c36c42073216 Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Sun, 18 Sep 2022 15:46:26 +0200 +Subject: [PATCH 10/18] mvebu: cortexa72: enable SBSA Watchdog, Mikrotik RB + Sysfs and MTD_SPLIT_FIT_FW + +--- + target/linux/mvebu/cortexa72/config-5.15 | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15 +index 27a413c624..0f19de730e 100644 +--- a/target/linux/mvebu/cortexa72/config-5.15 ++++ b/target/linux/mvebu/cortexa72/config-5.15 +@@ -35,6 +35,7 @@ CONFIG_ARM_GIC_V3_ITS=y + CONFIG_ARM_GIC_V3_ITS_PCI=y + # CONFIG_ARM_PL172_MPMC is not set + CONFIG_ARM_PSCI_FW=y ++CONFIG_ARM_SBSA_WATCHDOG=y + CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y + CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y + CONFIG_CPU_LITTLE_ENDIAN=y +@@ -54,6 +55,9 @@ CONFIG_MFD_IEI_WT61P803_PUZZLE=y + CONFIG_MFD_SYSCON=y + CONFIG_MMC_SDHCI_XENON=y + CONFIG_MODULES_USE_ELF_RELA=y ++CONFIG_MIKROTIK=y ++CONFIG_MIKROTIK_RB_SYSFS=y ++CONFIG_MTD_SPLIT_FIT_FW=y + CONFIG_MVEBU_GICP=y + CONFIG_MVEBU_ICU=y + CONFIG_MVEBU_ODMI=y +-- +2.42.1 + diff --git a/build_patches/openwrt/0211-mvebu-cortexa72-performance-as-default-scheduler.patch b/build_patches/openwrt/0211-mvebu-cortexa72-performance-as-default-scheduler.patch new file mode 100644 index 00000000..80099f79 --- /dev/null +++ b/build_patches/openwrt/0211-mvebu-cortexa72-performance-as-default-scheduler.patch @@ -0,0 +1,30 @@ +From 97711723fb3d695c87133b2ec6ab5a9b6dea352c Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Fri, 23 Sep 2022 23:54:15 +0200 +Subject: [PATCH 11/18] mvebu: cortexa72: performance as default scheduler + +It looks more and more like demand-based governors cause extra +jitter, so ditch 'schedutil' and switch to 'performance' + +Signed-off-by: Stijn Segers +--- + target/linux/mvebu/cortexa72/config-5.15 | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15 +index 0f19de730e..5d7b5594aa 100644 +--- a/target/linux/mvebu/cortexa72/config-5.15 ++++ b/target/linux/mvebu/cortexa72/config-5.15 +@@ -38,6 +38,9 @@ CONFIG_ARM_PSCI_FW=y + CONFIG_ARM_SBSA_WATCHDOG=y + CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y + CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y + CONFIG_CPU_LITTLE_ENDIAN=y + CONFIG_DMA_DIRECT_REMAP=y + CONFIG_FRAME_POINTER=y +-- +2.42.1 + diff --git a/build_patches/openwrt/0212-mvebu-add-Amethyst-specific-SMI-setup.patch b/build_patches/openwrt/0212-mvebu-add-Amethyst-specific-SMI-setup.patch new file mode 100644 index 00000000..a0da2191 --- /dev/null +++ b/build_patches/openwrt/0212-mvebu-add-Amethyst-specific-SMI-setup.patch @@ -0,0 +1,118 @@ +From facbe16f6981dccaf682980a2cb18790d6eae0d2 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 30 Jan 2022 13:03:13 +0100 +Subject: [PATCH 12/18] mvebu: add Amethyst specific SMI setup + +Amethyst switches require different external SMI GPIO setup then other +switches, so provide it since RB5009 uses the external SMI bus. + +Signed-off-by: Robert Marko +--- + ...x-add-Amethyst-specific-SMI-GPIO-fun.patch | 95 +++++++++++++++++++ + 1 file changed, 95 insertions(+) + create mode 100644 target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch + +diff --git a/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch b/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch +new file mode 100644 +index 0000000000..248b8b9d6c +--- /dev/null ++++ b/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch +@@ -0,0 +1,95 @@ ++From 40aa82107e7b1e7f20cbf6e644005c0c606f9f79 Mon Sep 17 00:00:00 2001 ++From: Robert Marko ++Date: Fri, 14 Jan 2022 15:17:37 +0100 ++Subject: [PATCH] net: dsa: mv88e6xxx: add Amethyst specific SMI GPIO function ++ ++The existing mv88e6xxx_g2_scratch_gpio_set_smi() cannot be used on the ++88E6393X as it requires certain P0_MODE, it also checks the CPU mode ++as it impacts the bit setting value. ++ ++This is all irrelevant for Amethyst (MV88E6191X/6193X/6393X) as only ++the default value of the SMI_PHY Config bit is set to CPU_MGD bootstrap ++pin value but it can be changed without restrictions so that GPIO pins ++9 and 10 are used as SMI pins. ++ ++So, introduce Amethyst specific function and call that if the Amethyst ++family wants to setup the external PHY. ++ ++Signed-off-by: Robert Marko ++--- ++ drivers/net/dsa/mv88e6xxx/chip.c | 5 +++- ++ drivers/net/dsa/mv88e6xxx/global2.h | 2 ++ ++ drivers/net/dsa/mv88e6xxx/global2_scratch.c | 31 +++++++++++++++++++++ ++ 3 files changed, 37 insertions(+), 1 deletion(-) ++ ++diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c ++index 43d126628610..b3803101d612 100644 ++--- a/drivers/net/dsa/mv88e6xxx/chip.c +++++ b/drivers/net/dsa/mv88e6xxx/chip.c ++@@ -3409,7 +3409,10 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, ++ ++ if (external) { ++ mv88e6xxx_reg_lock(chip); ++- err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); +++ if (chip->info->family == MV88E6XXX_FAMILY_6393) +++ err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); +++ else +++ err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); ++ mv88e6xxx_reg_unlock(chip); ++ ++ if (err) ++diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h ++index f3e27573a386..e0649f21f28e 100644 ++--- a/drivers/net/dsa/mv88e6xxx/global2.h +++++ b/drivers/net/dsa/mv88e6xxx/global2.h ++@@ -370,6 +370,8 @@ extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; ++ ++ int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, ++ bool external); +++int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, +++ bool external); ++ int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin); ++ int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats); ++ ++diff --git a/drivers/net/dsa/mv88e6xxx/global2_scratch.c b/drivers/net/dsa/mv88e6xxx/global2_scratch.c ++index eda710062933..dc3f4645fa52 100644 ++--- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c +++++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c ++@@ -289,3 +289,34 @@ int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, ++ ++ return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val); ++ } +++ +++/** +++ * mv88e6393x_g2_scratch_gpio_set_smi - set gpio muxing for external smi +++ * @chip: chip private data +++ * @external: set mux for external smi, or free for gpio usage +++ * +++ * MV88E6191X/6193X/6393X GPIO pins 9 and 10 can be configured as an +++ * external SMI interface or as regular GPIO-s. +++ * +++ * They however have a different register layout then the existing +++ * function. +++ */ +++ +++int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, +++ bool external) +++{ +++ int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG; +++ int err; +++ u8 val; +++ +++ err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val); +++ if (err) +++ return err; +++ +++ if (external) +++ val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI; +++ else +++ val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI; +++ +++ return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val); +++} ++-- ++2.34.1 ++ +-- +2.42.1 + diff --git a/build_patches/openwrt/0213-kernel-5.15-backport-QCA8081-PHY-support.patch b/build_patches/openwrt/0213-kernel-5.15-backport-QCA8081-PHY-support.patch new file mode 100644 index 00000000..282eb182 --- /dev/null +++ b/build_patches/openwrt/0213-kernel-5.15-backport-QCA8081-PHY-support.patch @@ -0,0 +1,1626 @@ +From ab9ea153c32fdf68240d2ad6d20523b3fd15d88d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 30 Jan 2022 13:00:09 +0100 +Subject: [PATCH 13/18] kernel: 5.15: backport QCA8081 PHY support + +Backport support for the Qualcomm QCA8081 PHY as well as one pending fix. + +Signed-off-by: Robert Marko +--- + ...eplace-AT803X_DEVICE_ADDR-with-MDIO_.patch | 50 ++++ + ...-v5.16-net-phy-at803x-use-phy_modify.patch | 41 +++ + ...t-phy-at803x-improve-the-WOL-feature.patch | 110 ++++++++ + ...-at803x-use-GENMASK-for-speed-status.patch | 45 +++ + ...6-net-phy-at803x-add-QCA9561-support.patch | 84 ++++++ + ...-phy-add-qca8081-ethernet-phy-driver.patch | 70 +++++ + ...5.16-net-phy-add-qca8081-read_status.patch | 176 ++++++++++++ + ....16-net-phy-add-qca8081-get_features.patch | 46 +++ + ...5.16-net-phy-add-qca8081-config_aneg.patch | 62 ++++ + ...tants-for-fast-retrain-related-regis.patch | 67 +++++ + ...-net-phy-add-genphy_c45_fast_retrain.patch | 75 +++++ + ...5.16-net-phy-add-qca8081-config_init.patch | 152 ++++++++++ + ...081-soft_reset-and-enable-master-sla.patch | 107 +++++++ + ...ca8081-master-slave-seed-value-if-li.patch | 51 ++++ + ...5.16-net-phy-add-qca8081-cdt-feature.patch | 264 ++++++++++++++++++ + ...a8081-with-speeds-lower-than-2.5Gb-s.patch | 84 ++++++ + 16 files changed, 1484 insertions(+) + create mode 100644 target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch + create mode 100644 target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch + create mode 100644 target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch + create mode 100644 target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch + create mode 100644 target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch + create mode 100644 target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch + create mode 100644 target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch + create mode 100644 target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch + create mode 100644 target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch + create mode 100644 target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch + create mode 100644 target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch + create mode 100644 target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch + create mode 100644 target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch + create mode 100644 target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch + create mode 100644 target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch + create mode 100644 target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch + +diff --git a/target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch b/target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch +new file mode 100644 +index 0000000000..2b0b24e62c +--- /dev/null ++++ b/target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch +@@ -0,0 +1,50 @@ ++From 157bb1293c232adb1e6f78db57e7f4f8aa853124 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:25 +0800 ++Subject: [PATCH 765/778] net: phy: at803x: replace AT803X_DEVICE_ADDR with ++ MDIO_MMD_PCS ++ ++Replace AT803X_DEVICE_ADDR with MDIO_MMD_PCS defined in mdio.h. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Reviewed-by: Russell King (Oracle) ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 6 +++--- ++ 1 file changed, 3 insertions(+), 3 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 69da011e82c8..d0f41cdaec75 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -70,7 +70,6 @@ ++ #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) ++ #define AT803X_LED_CONTROL 0x18 ++ ++-#define AT803X_DEVICE_ADDR 0x03 ++ #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C ++ #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B ++ #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A ++@@ -338,7 +337,8 @@ static int at803x_set_wol(struct phy_device *phydev, ++ const u8 *mac; ++ int ret; ++ u32 value; ++- unsigned int i, offsets[] = { +++ unsigned int i; +++ const unsigned int offsets[] = { ++ AT803X_LOC_MAC_ADDR_32_47_OFFSET, ++ AT803X_LOC_MAC_ADDR_16_31_OFFSET, ++ AT803X_LOC_MAC_ADDR_0_15_OFFSET, ++@@ -354,7 +354,7 @@ static int at803x_set_wol(struct phy_device *phydev, ++ return -EINVAL; ++ ++ for (i = 0; i < 3; i++) ++- phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], +++ phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], ++ mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); ++ ++ value = phy_read(phydev, AT803X_INTR_ENABLE); ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch b/target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch +new file mode 100644 +index 0000000000..fbd7de0519 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch +@@ -0,0 +1,41 @@ ++From e75ced0692768f577ef69a6896bd146a71816205 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:26 +0800 ++Subject: [PATCH 766/778] net: phy: at803x: use phy_modify() ++ ++Convert at803x_set_wol to use phy_modify. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Reviewed-by: Russell King (Oracle) ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 8 ++------ ++ 1 file changed, 2 insertions(+), 6 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index d0f41cdaec75..cf25cd428ffa 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -357,16 +357,12 @@ static int at803x_set_wol(struct phy_device *phydev, ++ phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], ++ mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); ++ ++- value = phy_read(phydev, AT803X_INTR_ENABLE); ++- value |= AT803X_INTR_ENABLE_WOL; ++- ret = phy_write(phydev, AT803X_INTR_ENABLE, value); +++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); ++ if (ret) ++ return ret; ++ value = phy_read(phydev, AT803X_INTR_STATUS); ++ } else { ++- value = phy_read(phydev, AT803X_INTR_ENABLE); ++- value &= (~AT803X_INTR_ENABLE_WOL); ++- ret = phy_write(phydev, AT803X_INTR_ENABLE, value); +++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); ++ if (ret) ++ return ret; ++ value = phy_read(phydev, AT803X_INTR_STATUS); ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch b/target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch +new file mode 100644 +index 0000000000..1109e0a81e +--- /dev/null ++++ b/target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch +@@ -0,0 +1,110 @@ ++From e452594dba41f6ed48c36b919ad7a1ff809af0f6 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:27 +0800 ++Subject: [PATCH 767/778] net: phy: at803x: improve the WOL feature ++ ++The wol feature is controlled by the MMD3.8012 bit5, ++need to set this bit when the wol function is enabled. ++ ++The reg18 bit0 is for enabling WOL interrupt, when wol ++occurs, the wol interrupt status reg19 bit0 is set to 1. ++ ++Call phy_trigger_machine if there are any other interrupt ++pending in the function set_wol. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 45 +++++++++++++++++++++++++++++++++------- ++ 1 file changed, 38 insertions(+), 7 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index cf25cd428ffa..1363f12ba659 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -70,6 +70,8 @@ ++ #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) ++ #define AT803X_LED_CONTROL 0x18 ++ +++#define AT803X_PHY_MMD3_WOL_CTRL 0x8012 +++#define AT803X_WOL_EN BIT(5) ++ #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C ++ #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B ++ #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A ++@@ -335,8 +337,7 @@ static int at803x_set_wol(struct phy_device *phydev, ++ { ++ struct net_device *ndev = phydev->attached_dev; ++ const u8 *mac; ++- int ret; ++- u32 value; +++ int ret, irq_enabled; ++ unsigned int i; ++ const unsigned int offsets[] = { ++ AT803X_LOC_MAC_ADDR_32_47_OFFSET, ++@@ -357,18 +358,45 @@ static int at803x_set_wol(struct phy_device *phydev, ++ phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], ++ mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); ++ +++ /* Enable WOL function */ +++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, +++ 0, AT803X_WOL_EN); +++ if (ret) +++ return ret; +++ /* Enable WOL interrupt */ ++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); ++ if (ret) ++ return ret; ++- value = phy_read(phydev, AT803X_INTR_STATUS); ++ } else { +++ /* Disable WoL function */ +++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, +++ AT803X_WOL_EN, 0); +++ if (ret) +++ return ret; +++ /* Disable WOL interrupt */ ++ ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); ++ if (ret) ++ return ret; ++- value = phy_read(phydev, AT803X_INTR_STATUS); ++ } ++ ++- return ret; +++ /* Clear WOL status */ +++ ret = phy_read(phydev, AT803X_INTR_STATUS); +++ if (ret < 0) +++ return ret; +++ +++ /* Check if there are other interrupts except for WOL triggered when PHY is +++ * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can +++ * be passed up to the interrupt PIN. +++ */ +++ irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); +++ if (irq_enabled < 0) +++ return irq_enabled; +++ +++ irq_enabled &= ~AT803X_INTR_ENABLE_WOL; +++ if (ret & irq_enabled && !phy_polling_mode(phydev)) +++ phy_trigger_machine(phydev); +++ +++ return 0; ++ } ++ ++ static void at803x_get_wol(struct phy_device *phydev, ++@@ -379,8 +407,11 @@ static void at803x_get_wol(struct phy_device *phydev, ++ wol->supported = WAKE_MAGIC; ++ wol->wolopts = 0; ++ ++- value = phy_read(phydev, AT803X_INTR_ENABLE); ++- if (value & AT803X_INTR_ENABLE_WOL) +++ value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); +++ if (value < 0) +++ return; +++ +++ if (value & AT803X_WOL_EN) ++ wol->wolopts |= WAKE_MAGIC; ++ } ++ ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch b/target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch +new file mode 100644 +index 0000000000..534878a266 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch +@@ -0,0 +1,45 @@ ++From 3a6119df06444516c2b06e52df29561cc7820578 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:28 +0800 ++Subject: [PATCH 768/778] net: phy: at803x: use GENMASK() for speed status ++ ++Use GENMASK() for the current speed value. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 10 +++++----- ++ 1 file changed, 5 insertions(+), 5 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 1363f12ba659..3465f2bb6356 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -33,10 +33,10 @@ ++ #define AT803X_SFC_DISABLE_JABBER BIT(0) ++ ++ #define AT803X_SPECIFIC_STATUS 0x11 ++-#define AT803X_SS_SPEED_MASK (3 << 14) ++-#define AT803X_SS_SPEED_1000 (2 << 14) ++-#define AT803X_SS_SPEED_100 (1 << 14) ++-#define AT803X_SS_SPEED_10 (0 << 14) +++#define AT803X_SS_SPEED_MASK GENMASK(15, 14) +++#define AT803X_SS_SPEED_1000 2 +++#define AT803X_SS_SPEED_100 1 +++#define AT803X_SS_SPEED_10 0 ++ #define AT803X_SS_DUPLEX BIT(13) ++ #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) ++ #define AT803X_SS_MDIX BIT(6) ++@@ -994,7 +994,7 @@ static int at803x_read_status(struct phy_device *phydev) ++ if (sfc < 0) ++ return sfc; ++ ++- switch (ss & AT803X_SS_SPEED_MASK) { +++ switch (FIELD_GET(AT803X_SS_SPEED_MASK, ss)) { ++ case AT803X_SS_SPEED_10: ++ phydev->speed = SPEED_10; ++ break; ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch b/target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch +new file mode 100644 +index 0000000000..48fbac610a +--- /dev/null ++++ b/target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch +@@ -0,0 +1,84 @@ ++From fada2ce09308bc79e27876b8a89c7de38265f730 Mon Sep 17 00:00:00 2001 ++From: David Bauer ++Date: Wed, 6 Oct 2021 00:54:01 +0200 ++Subject: [PATCH] net: phy: at803x: add QCA9561 support ++ ++Add support for the embedded fast-ethernet PHY found on the QCA9561 ++WiSoC platform. It supports the usual Atheros PHY featureset including ++the cable tester. ++ ++Tested on a Xiaomi MiRouter 4Q (QCA9561) ++ ++Reviewed-by: Andrew Lunn ++Signed-off-by: David Bauer ++Link: https://lore.kernel.org/r/20211005225401.10653-1-mail@david-bauer.net ++Signed-off-by: Jakub Kicinski ++--- ++ drivers/net/phy/at803x.c | 23 +++++++++++++++++++++-- ++ 1 file changed, 21 insertions(+), 2 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 3feee4d59030..ae7e1f1c59f0 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -153,6 +153,7 @@ ++ #define QCA8327_A_PHY_ID 0x004dd033 ++ #define QCA8327_B_PHY_ID 0x004dd034 ++ #define QCA8337_PHY_ID 0x004dd036 +++#define QCA9561_PHY_ID 0x004dd042 ++ #define QCA8K_PHY_ID_MASK 0xffffffff ++ ++ #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) ++@@ -1237,7 +1238,8 @@ static int at803x_cable_test_get_status(struct phy_device *phydev, ++ int pair, ret; ++ ++ if (phydev->phy_id == ATH9331_PHY_ID || ++- phydev->phy_id == ATH8032_PHY_ID) +++ phydev->phy_id == ATH8032_PHY_ID || +++ phydev->phy_id == QCA9561_PHY_ID) ++ pair_mask = 0x3; ++ else ++ pair_mask = 0xf; ++@@ -1277,7 +1279,8 @@ static int at803x_cable_test_start(struct phy_device *phydev) ++ phy_write(phydev, MII_BMCR, BMCR_ANENABLE); ++ phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); ++ if (phydev->phy_id != ATH9331_PHY_ID && ++- phydev->phy_id != ATH8032_PHY_ID) +++ phydev->phy_id != ATH8032_PHY_ID && +++ phydev->phy_id != QCA9561_PHY_ID) ++ phy_write(phydev, MII_CTRL1000, 0); ++ ++ /* we do all the (time consuming) work later */ ++@@ -1408,6 +1411,21 @@ static struct phy_driver at803x_driver[] = { ++ .read_status = at803x_read_status, ++ .soft_reset = genphy_soft_reset, ++ .config_aneg = at803x_config_aneg, +++}, { +++ /* Qualcomm Atheros QCA9561 */ +++ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), +++ .name = "Qualcomm Atheros QCA9561 built-in PHY", +++ .suspend = at803x_suspend, +++ .resume = at803x_resume, +++ .flags = PHY_POLL_CABLE_TEST, +++ /* PHY_BASIC_FEATURES */ +++ .config_intr = &at803x_config_intr, +++ .handle_interrupt = at803x_handle_interrupt, +++ .cable_test_start = at803x_cable_test_start, +++ .cable_test_get_status = at803x_cable_test_get_status, +++ .read_status = at803x_read_status, +++ .soft_reset = genphy_soft_reset, +++ .config_aneg = at803x_config_aneg, ++ }, { ++ /* QCA8337 */ ++ .phy_id = QCA8337_PHY_ID, ++@@ -1466,6 +1484,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { ++ { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, +++ { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, ++ { } ++ }; ++ ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch b/target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch +new file mode 100644 +index 0000000000..1aec1eae60 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch +@@ -0,0 +1,70 @@ ++From b135eb71f8b23ebfa5a1970dbdfa7834853f38b6 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:29 +0800 ++Subject: [PATCH 769/778] net: phy: add qca8081 ethernet phy driver ++ ++qca8081 is a single port ethernet phy chip that supports ++10/100/1000/2500 Mbps mode. ++ ++Add the basic phy driver features, and reuse the at803x ++phy driver functions. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 17 ++++++++++++++++- ++ 1 file changed, 16 insertions(+), 1 deletion(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 3465f2bb6356..aae27fe3e1e1 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -158,6 +158,8 @@ ++ #define ATH8035_PHY_ID 0x004dd072 ++ #define AT8030_PHY_ID_MASK 0xffffffef ++ +++#define QCA8081_PHY_ID 0x004dd101 +++ ++ #define QCA8327_A_PHY_ID 0x004dd033 ++ #define QCA8327_B_PHY_ID 0x004dd034 ++ #define QCA8337_PHY_ID 0x004dd036 ++@@ -173,7 +175,7 @@ ++ #define AT803X_KEEP_PLL_ENABLED BIT(0) ++ #define AT803X_DISABLE_SMARTEEE BIT(1) ++ ++-MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); +++MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); ++ MODULE_AUTHOR("Matus Ujhelyi"); ++ MODULE_LICENSE("GPL"); ++ ++@@ -1591,6 +1593,18 @@ static struct phy_driver at803x_driver[] = { ++ .get_stats = at803x_get_stats, ++ .suspend = qca83xx_suspend, ++ .resume = qca83xx_resume, +++}, { +++ /* Qualcomm QCA8081 */ +++ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), +++ .name = "Qualcomm QCA8081", +++ .config_intr = at803x_config_intr, +++ .handle_interrupt = at803x_handle_interrupt, +++ .get_tunable = at803x_get_tunable, +++ .set_tunable = at803x_set_tunable, +++ .set_wol = at803x_set_wol, +++ .get_wol = at803x_get_wol, +++ .suspend = genphy_suspend, +++ .resume = genphy_resume, ++ }, }; ++ ++ module_phy_driver(at803x_driver); ++@@ -1605,6 +1619,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { ++ { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, ++ { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, +++ { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, ++ { } ++ }; ++ ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch b/target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch +new file mode 100644 +index 0000000000..3e7572b034 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch +@@ -0,0 +1,176 @@ ++From c5d98553d5b7f44d79e0b90a3d6c3256c22df939 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:30 +0800 ++Subject: [PATCH 770/778] net: phy: add qca8081 read_status ++ ++1. Separate the function at803x_read_specific_status from ++the at803x_read_status, since it can be reused by the ++read_status of qca8081 phy driver excepting adding the ++2500M speed. ++ ++2. Add the qca8081 read_status function qca808x_read_status. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 95 ++++++++++++++++++++++++++++++---------- ++ 1 file changed, 73 insertions(+), 22 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index aae27fe3e1e1..cecf78e6c643 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -41,6 +41,9 @@ ++ #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) ++ #define AT803X_SS_MDIX BIT(6) ++ +++#define QCA808X_SS_SPEED_MASK GENMASK(9, 7) +++#define QCA808X_SS_SPEED_2500 4 +++ ++ #define AT803X_INTR_ENABLE 0x12 ++ #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) ++ #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) ++@@ -959,27 +962,9 @@ static void at803x_link_change_notify(struct phy_device *phydev) ++ } ++ } ++ ++-static int at803x_read_status(struct phy_device *phydev) +++static int at803x_read_specific_status(struct phy_device *phydev) ++ { ++- int ss, err, old_link = phydev->link; ++- ++- /* Update the link, but return if there was an error */ ++- err = genphy_update_link(phydev); ++- if (err) ++- return err; ++- ++- /* why bother the PHY if nothing can have changed */ ++- if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) ++- return 0; ++- ++- phydev->speed = SPEED_UNKNOWN; ++- phydev->duplex = DUPLEX_UNKNOWN; ++- phydev->pause = 0; ++- phydev->asym_pause = 0; ++- ++- err = genphy_read_lpa(phydev); ++- if (err < 0) ++- return err; +++ int ss; ++ ++ /* Read the AT8035 PHY-Specific Status register, which indicates the ++ * speed and duplex that the PHY is actually using, irrespective of ++@@ -990,13 +975,19 @@ static int at803x_read_status(struct phy_device *phydev) ++ return ss; ++ ++ if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { ++- int sfc; +++ int sfc, speed; ++ ++ sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); ++ if (sfc < 0) ++ return sfc; ++ ++- switch (FIELD_GET(AT803X_SS_SPEED_MASK, ss)) { +++ /* qca8081 takes the different bits for speed value from at803x */ +++ if (phydev->drv->phy_id == QCA8081_PHY_ID) +++ speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); +++ else +++ speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); +++ +++ switch (speed) { ++ case AT803X_SS_SPEED_10: ++ phydev->speed = SPEED_10; ++ break; ++@@ -1006,6 +997,9 @@ static int at803x_read_status(struct phy_device *phydev) ++ case AT803X_SS_SPEED_1000: ++ phydev->speed = SPEED_1000; ++ break; +++ case QCA808X_SS_SPEED_2500: +++ phydev->speed = SPEED_2500; +++ break; ++ } ++ if (ss & AT803X_SS_DUPLEX) ++ phydev->duplex = DUPLEX_FULL; ++@@ -1030,6 +1024,35 @@ static int at803x_read_status(struct phy_device *phydev) ++ } ++ } ++ +++ return 0; +++} +++ +++static int at803x_read_status(struct phy_device *phydev) +++{ +++ int err, old_link = phydev->link; +++ +++ /* Update the link, but return if there was an error */ +++ err = genphy_update_link(phydev); +++ if (err) +++ return err; +++ +++ /* why bother the PHY if nothing can have changed */ +++ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) +++ return 0; +++ +++ phydev->speed = SPEED_UNKNOWN; +++ phydev->duplex = DUPLEX_UNKNOWN; +++ phydev->pause = 0; +++ phydev->asym_pause = 0; +++ +++ err = genphy_read_lpa(phydev); +++ if (err < 0) +++ return err; +++ +++ err = at803x_read_specific_status(phydev); +++ if (err < 0) +++ return err; +++ ++ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) ++ phy_resolve_aneg_pause(phydev); ++ ++@@ -1434,6 +1457,33 @@ static int qca83xx_suspend(struct phy_device *phydev) ++ return 0; ++ } ++ +++static int qca808x_read_status(struct phy_device *phydev) +++{ +++ int ret; +++ +++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); +++ if (ret < 0) +++ return ret; +++ +++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, +++ ret & MDIO_AN_10GBT_STAT_LP2_5G); +++ +++ ret = genphy_read_status(phydev); +++ if (ret) +++ return ret; +++ +++ ret = at803x_read_specific_status(phydev); +++ if (ret < 0) +++ return ret; +++ +++ if (phydev->link && phydev->speed == SPEED_2500) +++ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +++ else +++ phydev->interface = PHY_INTERFACE_MODE_SMII; +++ +++ return 0; +++} +++ ++ static struct phy_driver at803x_driver[] = { ++ { ++ /* Qualcomm Atheros AR8035 */ ++@@ -1605,6 +1655,7 @@ static struct phy_driver at803x_driver[] = { ++ .get_wol = at803x_get_wol, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, +++ .read_status = qca808x_read_status, ++ }, }; ++ ++ module_phy_driver(at803x_driver); ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch b/target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch +new file mode 100644 +index 0000000000..7cc6a79e7b +--- /dev/null ++++ b/target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch +@@ -0,0 +1,46 @@ ++From 0850643b203fea4106aa063f235f708f6c18b809 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:31 +0800 ++Subject: [PATCH 771/778] net: phy: add qca8081 get_features ++ ++Reuse the at803x phy driver get_features excepting ++adding 2500M capability. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 10 ++++++++++ ++ 1 file changed, 10 insertions(+) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index cecf78e6c643..c4b7ac03cd35 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -744,6 +744,15 @@ static int at803x_get_features(struct phy_device *phydev) ++ if (err) ++ return err; ++ +++ if (phydev->drv->phy_id == QCA8081_PHY_ID) { +++ err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); +++ if (err < 0) +++ return err; +++ +++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, +++ err & MDIO_PMA_NG_EXTABLE_2_5GBT); +++ } +++ ++ if (phydev->drv->phy_id != ATH8031_PHY_ID) ++ return 0; ++ ++@@ -1653,6 +1662,7 @@ static struct phy_driver at803x_driver[] = { ++ .set_tunable = at803x_set_tunable, ++ .set_wol = at803x_set_wol, ++ .get_wol = at803x_get_wol, +++ .get_features = at803x_get_features, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_status = qca808x_read_status, ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch b/target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch +new file mode 100644 +index 0000000000..2b9b2edbf8 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch +@@ -0,0 +1,62 @@ ++From eedbbcef4c38b9987afd5307cb4db43012aca6dc Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:32 +0800 ++Subject: [PATCH 772/778] net: phy: add qca8081 config_aneg ++ ++Reuse at803x phy driver config_aneg excepting ++adding 2500M auto-negotiation. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 26 +++++++++++++++++++++++++- ++ 1 file changed, 25 insertions(+), 1 deletion(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index c4b7ac03cd35..70c1025e8e5d 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -1109,7 +1109,30 @@ static int at803x_config_aneg(struct phy_device *phydev) ++ return ret; ++ } ++ ++- return genphy_config_aneg(phydev); +++ /* Do not restart auto-negotiation by setting ret to 0 defautly, +++ * when calling __genphy_config_aneg later. +++ */ +++ ret = 0; +++ +++ if (phydev->drv->phy_id == QCA8081_PHY_ID) { +++ int phy_ctrl = 0; +++ +++ /* The reg MII_BMCR also needs to be configured for force mode, the +++ * genphy_config_aneg is also needed. +++ */ +++ if (phydev->autoneg == AUTONEG_DISABLE) +++ genphy_c45_pma_setup_forced(phydev); +++ +++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) +++ phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; +++ +++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, +++ MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); +++ if (ret < 0) +++ return ret; +++ } +++ +++ return __genphy_config_aneg(phydev, ret); ++ } ++ ++ static int at803x_get_downshift(struct phy_device *phydev, u8 *d) ++@@ -1663,6 +1686,7 @@ static struct phy_driver at803x_driver[] = { ++ .set_wol = at803x_set_wol, ++ .get_wol = at803x_get_wol, ++ .get_features = at803x_get_features, +++ .config_aneg = at803x_config_aneg, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_status = qca808x_read_status, ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch b/target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch +new file mode 100644 +index 0000000000..31c08efc85 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch +@@ -0,0 +1,67 @@ ++From b49201b26348c478e7efe820d3b68bc87041d66e Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:33 +0800 ++Subject: [PATCH 773/778] net: phy: add constants for fast retrain related ++ register ++ ++Add the constants for 2.5G fast retrain capability ++in 10G AN control register, fast retrain status and ++control register and THP bypass register into mdio.h. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ include/uapi/linux/mdio.h | 9 +++++++++ ++ 1 file changed, 9 insertions(+) ++ ++diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h ++index bdf77dffa5a4..c54e6eae5366 100644 ++--- a/include/uapi/linux/mdio.h +++++ b/include/uapi/linux/mdio.h ++@@ -53,12 +53,14 @@ ++ #define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */ ++ #define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */ ++ #define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */ +++#define MDIO_AN_CTRL2 64 /* AN THP bypass request control */ ++ ++ /* Media-dependent registers. */ ++ #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ ++ #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ ++ #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. ++ * Lanes B-D are numbered 134-136. */ +++#define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */ ++ #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ ++ #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ ++ #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ ++@@ -239,6 +241,9 @@ ++ #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ ++ #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ ++ +++/* PMA 10GBASE-R Fast Retrain status and control register. */ +++#define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 /* Fast retrain enable */ +++ ++ /* PCS 10GBASE-R/-T status register 1. */ ++ #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ ++ ++@@ -247,6 +252,7 @@ ++ #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 ++ ++ /* AN 10GBASE-T control register. */ +++#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 /* Advertise 2.5GBASE-T fast retrain */ ++ #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */ ++ #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */ ++ #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ ++@@ -289,6 +295,9 @@ ++ #define MDIO_EEE_2_5GT 0x0001 /* 2.5GT EEE cap */ ++ #define MDIO_EEE_5GT 0x0002 /* 5GT EEE cap */ ++ +++/* AN MultiGBASE-T AN control 2 */ +++#define MDIO_AN_THP_BP2_5GT 0x0008 /* 2.5GT THP bypass request */ +++ ++ /* 2.5G/5G Extended abilities register. */ ++ #define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */ ++ #define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */ ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch b/target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch +new file mode 100644 +index 0000000000..0cf37833f6 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch +@@ -0,0 +1,75 @@ ++From 95a73ac1f54b2ad307c525e48757da22bb3e81e7 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:34 +0800 ++Subject: [PATCH 774/778] net: phy: add genphy_c45_fast_retrain ++ ++Add generic fast retrain auto-negotiation function for C45 PHYs. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/phy-c45.c | 34 ++++++++++++++++++++++++++++++++++ ++ include/linux/phy.h | 1 + ++ 2 files changed, 35 insertions(+) ++ ++diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c ++index c617dbcad6ea..b01180e1f578 100644 ++--- a/drivers/net/phy/phy-c45.c +++++ b/drivers/net/phy/phy-c45.c ++@@ -611,6 +611,40 @@ int genphy_c45_loopback(struct phy_device *phydev, bool enable) ++ } ++ EXPORT_SYMBOL_GPL(genphy_c45_loopback); ++ +++/** +++ * genphy_c45_fast_retrain - configure fast retrain registers +++ * @phydev: target phy_device struct +++ * +++ * Description: If fast-retrain is enabled, we configure PHY as +++ * advertising fast retrain capable and THP Bypass Request, then +++ * enable fast retrain. If it is not enabled, we configure fast +++ * retrain disabled. +++ */ +++int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) +++{ +++ int ret; +++ +++ if (!enable) +++ return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, +++ MDIO_PMA_10GBR_FSRT_ENABLE); +++ +++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { +++ ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, +++ MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); +++ if (ret) +++ return ret; +++ +++ ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, +++ MDIO_AN_THP_BP2_5GT); +++ if (ret) +++ return ret; +++ } +++ +++ return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, +++ MDIO_PMA_10GBR_FSRT_ENABLE); +++} +++EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); +++ ++ struct phy_driver genphy_c45_driver = { ++ .phy_id = 0xffffffff, ++ .phy_id_mask = 0xffffffff, ++diff --git a/include/linux/phy.h b/include/linux/phy.h ++index 736e1d1a47c4..04e90423fa88 100644 ++--- a/include/linux/phy.h +++++ b/include/linux/phy.h ++@@ -1584,6 +1584,7 @@ int genphy_c45_config_aneg(struct phy_device *phydev); ++ int genphy_c45_loopback(struct phy_device *phydev, bool enable); ++ int genphy_c45_pma_resume(struct phy_device *phydev); ++ int genphy_c45_pma_suspend(struct phy_device *phydev); +++int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable); ++ ++ /* Generic C45 PHY driver */ ++ extern struct phy_driver genphy_c45_driver; ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch b/target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch +new file mode 100644 +index 0000000000..9c27de67b3 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch +@@ -0,0 +1,152 @@ ++From 6b81737634ba49859b6c042f1315f479cecb9b06 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:35 +0800 ++Subject: [PATCH 775/778] net: phy: add qca8081 config_init ++ ++Add the qca8081 phy driver config_init function, which includes: ++1. Enable fast restrain. ++2. Add 802.3az configurations. ++3. Initialize ADC threshold as 100mv. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 107 +++++++++++++++++++++++++++++++++++++++ ++ 1 file changed, 107 insertions(+) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 70c1025e8e5d..da710523b7c4 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -178,6 +178,51 @@ ++ #define AT803X_KEEP_PLL_ENABLED BIT(0) ++ #define AT803X_DISABLE_SMARTEEE BIT(1) ++ +++/* ADC threshold */ +++#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 +++#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) +++#define QCA808X_ADC_THRESHOLD_80MV 0 +++#define QCA808X_ADC_THRESHOLD_100MV 0xf0 +++#define QCA808X_ADC_THRESHOLD_200MV 0x0f +++#define QCA808X_ADC_THRESHOLD_300MV 0xff +++ +++/* CLD control */ +++#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 +++#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) +++#define QCA808X_8023AZ_AFE_EN 0x90 +++ +++/* AZ control */ +++#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 +++#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 +++ +++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 +++#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 +++ +++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E +++#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 +++ +++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E +++#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 +++ +++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 +++#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 +++ +++#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c +++#define QCA808X_TOP_OPTION1_DATA 0x0 +++ +++#define QCA808X_PHY_MMD3_DEBUG_1 0xa100 +++#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 +++#define QCA808X_PHY_MMD3_DEBUG_2 0xa101 +++#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad +++#define QCA808X_PHY_MMD3_DEBUG_3 0xa103 +++#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 +++#define QCA808X_PHY_MMD3_DEBUG_4 0xa105 +++#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 +++#define QCA808X_PHY_MMD3_DEBUG_5 0xa106 +++#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 +++#define QCA808X_PHY_MMD3_DEBUG_6 0xa011 +++#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 +++ ++ MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); ++ MODULE_AUTHOR("Matus Ujhelyi"); ++ MODULE_LICENSE("GPL"); ++@@ -1489,6 +1534,67 @@ static int qca83xx_suspend(struct phy_device *phydev) ++ return 0; ++ } ++ +++static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) +++{ +++ int ret; +++ +++ /* Enable fast retrain */ +++ ret = genphy_c45_fast_retrain(phydev, true); +++ if (ret) +++ return ret; +++ +++ phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, +++ QCA808X_TOP_OPTION1_DATA); +++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, +++ QCA808X_MSE_THRESHOLD_20DB_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, +++ QCA808X_MSE_THRESHOLD_17DB_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, +++ QCA808X_MSE_THRESHOLD_27DB_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, +++ QCA808X_MSE_THRESHOLD_28DB_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, +++ QCA808X_MMD3_DEBUG_1_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, +++ QCA808X_MMD3_DEBUG_4_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, +++ QCA808X_MMD3_DEBUG_5_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, +++ QCA808X_MMD3_DEBUG_3_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, +++ QCA808X_MMD3_DEBUG_6_VALUE); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, +++ QCA808X_MMD3_DEBUG_2_VALUE); +++ +++ return 0; +++} +++ +++static int qca808x_config_init(struct phy_device *phydev) +++{ +++ int ret; +++ +++ /* Active adc&vga on 802.3az for the link 1000M and 100M */ +++ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, +++ QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); +++ if (ret) +++ return ret; +++ +++ /* Adjust the threshold on 802.3az for the link 1000M */ +++ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, +++ QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); +++ if (ret) +++ return ret; +++ +++ /* Config the fast retrain for the link 2500M */ +++ ret = qca808x_phy_fast_retrain_config(phydev); +++ if (ret) +++ return ret; +++ +++ /* Configure adc threshold as 100mv for the link 10M */ +++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, +++ QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); +++} +++ ++ static int qca808x_read_status(struct phy_device *phydev) ++ { ++ int ret; ++@@ -1690,6 +1796,7 @@ static struct phy_driver at803x_driver[] = { ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_status = qca808x_read_status, +++ .config_init = qca808x_config_init, ++ }, }; ++ ++ module_phy_driver(at803x_driver); ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch b/target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch +new file mode 100644 +index 0000000000..bf34b4bdfb +--- /dev/null ++++ b/target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch +@@ -0,0 +1,107 @@ ++From 939ca53160bd3eb1044447099981f2de15347b24 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:36 +0800 ++Subject: [PATCH 776/778] net: phy: add qca8081 soft_reset and enable ++ master/slave seed ++ ++qca8081 phy is a single port phy, configure ++phy the lower seed value to make it linked as slave ++mode easier. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 48 ++++++++++++++++++++++++++++++++++++++++ ++ 1 file changed, 48 insertions(+) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index da710523b7c4..1418db4f2091 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -223,6 +223,12 @@ ++ #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 ++ #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 ++ +++/* master/slave seed config */ +++#define QCA808X_PHY_DEBUG_LOCAL_SEED 9 +++#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) +++#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) +++#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 +++ ++ MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); ++ MODULE_AUTHOR("Matus Ujhelyi"); ++ MODULE_LICENSE("GPL"); ++@@ -1569,6 +1575,26 @@ static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) ++ return 0; ++ } ++ +++static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) +++{ +++ u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE); +++ +++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, +++ QCA808X_MASTER_SLAVE_SEED_CFG, +++ FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); +++} +++ +++static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) +++{ +++ u16 seed_enable = 0; +++ +++ if (enable) +++ seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; +++ +++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, +++ QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); +++} +++ ++ static int qca808x_config_init(struct phy_device *phydev) ++ { ++ int ret; ++@@ -1590,6 +1616,16 @@ static int qca808x_config_init(struct phy_device *phydev) ++ if (ret) ++ return ret; ++ +++ /* Configure lower ramdom seed to make phy linked as slave mode */ +++ ret = qca808x_phy_ms_random_seed_set(phydev); +++ if (ret) +++ return ret; +++ +++ /* Enable seed */ +++ ret = qca808x_phy_ms_seed_enable(phydev, true); +++ if (ret) +++ return ret; +++ ++ /* Configure adc threshold as 100mv for the link 10M */ ++ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, ++ QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); ++@@ -1622,6 +1658,17 @@ static int qca808x_read_status(struct phy_device *phydev) ++ return 0; ++ } ++ +++static int qca808x_soft_reset(struct phy_device *phydev) +++{ +++ int ret; +++ +++ ret = genphy_soft_reset(phydev); +++ if (ret < 0) +++ return ret; +++ +++ return qca808x_phy_ms_seed_enable(phydev, true); +++} +++ ++ static struct phy_driver at803x_driver[] = { ++ { ++ /* Qualcomm Atheros AR8035 */ ++@@ -1797,6 +1844,7 @@ static struct phy_driver at803x_driver[] = { ++ .resume = genphy_resume, ++ .read_status = qca808x_read_status, ++ .config_init = qca808x_config_init, +++ .soft_reset = qca808x_soft_reset, ++ }, }; ++ ++ module_phy_driver(at803x_driver); ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch b/target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch +new file mode 100644 +index 0000000000..1f614e99a4 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch +@@ -0,0 +1,51 @@ ++From 2413dabe7f4a55ccf5876daeec8f7be5b651f1ab Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:37 +0800 ++Subject: [PATCH 777/778] net: phy: adjust qca8081 master/slave seed value if ++ link down ++ ++1. The master/slave seed needs to be updated when the link can't ++be created. ++ ++2. The case where two qca8081 PHYs are connected each other and ++master/slave seed is generated as the same value also needs ++to be considered, so adding this code change into read_status ++instead of link_change_notify. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 16 ++++++++++++++++ ++ 1 file changed, 16 insertions(+) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 1418db4f2091..00733badcda5 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -1655,6 +1655,22 @@ static int qca808x_read_status(struct phy_device *phydev) ++ else ++ phydev->interface = PHY_INTERFACE_MODE_SMII; ++ +++ /* generate seed as a lower random value to make PHY linked as SLAVE easily, +++ * except for master/slave configuration fault detected. +++ * the reason for not putting this code into the function link_change_notify is +++ * the corner case where the link partner is also the qca8081 PHY and the seed +++ * value is configured as the same value, the link can't be up and no link change +++ * occurs. +++ */ +++ if (!phydev->link) { +++ if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { +++ qca808x_phy_ms_seed_enable(phydev, false); +++ } else { +++ qca808x_phy_ms_random_seed_set(phydev); +++ qca808x_phy_ms_seed_enable(phydev, true); +++ } +++ } +++ ++ return 0; ++ } ++ ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch b/target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch +new file mode 100644 +index 0000000000..d49fb2f566 +--- /dev/null ++++ b/target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch +@@ -0,0 +1,264 @@ ++From c8f6335ebcb32c29abbde0e6849b48be04c0fe13 Mon Sep 17 00:00:00 2001 ++From: Luo Jie ++Date: Sun, 24 Oct 2021 16:27:38 +0800 ++Subject: [PATCH 778/778] net: phy: add qca8081 cdt feature ++ ++To perform CDT of qca8081 phy: ++1. disable hibernation. ++2. force phy working in MDI mode. ++3. force phy working in 1000BASE-T mode. ++4. configure the related thresholds. ++ ++Signed-off-by: Luo Jie ++Reviewed-by: Andrew Lunn ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 194 ++++++++++++++++++++++++++++++++++++++- ++ 1 file changed, 191 insertions(+), 3 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 00733badcda5..f1cbe1f6ddec 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -229,6 +229,32 @@ ++ #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) ++ #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 ++ +++/* Hibernation yields lower power consumpiton in contrast with normal operation mode. +++ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. +++ */ +++#define QCA808X_DBG_AN_TEST 0xb +++#define QCA808X_HIBERNATION_EN BIT(15) +++ +++#define QCA808X_CDT_ENABLE_TEST BIT(15) +++#define QCA808X_CDT_INTER_CHECK_DIS BIT(13) +++#define QCA808X_CDT_LENGTH_UNIT BIT(10) +++ +++#define QCA808X_MMD3_CDT_STATUS 0x8064 +++#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 +++#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 +++#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 +++#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 +++#define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) +++ +++#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) +++#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) +++#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) +++#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) +++#define QCA808X_CDT_STATUS_STAT_FAIL 0 +++#define QCA808X_CDT_STATUS_STAT_NORMAL 1 +++#define QCA808X_CDT_STATUS_STAT_OPEN 2 +++#define QCA808X_CDT_STATUS_STAT_SHORT 3 +++ ++ MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); ++ MODULE_AUTHOR("Matus Ujhelyi"); ++ MODULE_LICENSE("GPL"); ++@@ -1319,8 +1345,14 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) ++ { ++ u16 cdt; ++ ++- cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | ++- AT803X_CDT_ENABLE_TEST; +++ /* qca8081 takes the different bit 15 to enable CDT test */ +++ if (phydev->drv->phy_id == QCA8081_PHY_ID) +++ cdt = QCA808X_CDT_ENABLE_TEST | +++ QCA808X_CDT_LENGTH_UNIT | +++ QCA808X_CDT_INTER_CHECK_DIS; +++ else +++ cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | +++ AT803X_CDT_ENABLE_TEST; ++ ++ return phy_write(phydev, AT803X_CDT, cdt); ++ } ++@@ -1328,10 +1360,16 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) ++ static int at803x_cdt_wait_for_completion(struct phy_device *phydev) ++ { ++ int val, ret; +++ u16 cdt_en; +++ +++ if (phydev->drv->phy_id == QCA8081_PHY_ID) +++ cdt_en = QCA808X_CDT_ENABLE_TEST; +++ else +++ cdt_en = AT803X_CDT_ENABLE_TEST; ++ ++ /* One test run takes about 25ms */ ++ ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, ++- !(val & AT803X_CDT_ENABLE_TEST), +++ !(val & cdt_en), ++ 30000, 100000, true); ++ ++ return ret < 0 ? ret : 0; ++@@ -1685,6 +1723,153 @@ static int qca808x_soft_reset(struct phy_device *phydev) ++ return qca808x_phy_ms_seed_enable(phydev, true); ++ } ++ +++static bool qca808x_cdt_fault_length_valid(int cdt_code) +++{ +++ switch (cdt_code) { +++ case QCA808X_CDT_STATUS_STAT_SHORT: +++ case QCA808X_CDT_STATUS_STAT_OPEN: +++ return true; +++ default: +++ return false; +++ } +++} +++ +++static int qca808x_cable_test_result_trans(int cdt_code) +++{ +++ switch (cdt_code) { +++ case QCA808X_CDT_STATUS_STAT_NORMAL: +++ return ETHTOOL_A_CABLE_RESULT_CODE_OK; +++ case QCA808X_CDT_STATUS_STAT_SHORT: +++ return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; +++ case QCA808X_CDT_STATUS_STAT_OPEN: +++ return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; +++ case QCA808X_CDT_STATUS_STAT_FAIL: +++ default: +++ return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; +++ } +++} +++ +++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) +++{ +++ int val; +++ u32 cdt_length_reg = 0; +++ +++ switch (pair) { +++ case ETHTOOL_A_CABLE_PAIR_A: +++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; +++ break; +++ case ETHTOOL_A_CABLE_PAIR_B: +++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; +++ break; +++ case ETHTOOL_A_CABLE_PAIR_C: +++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; +++ break; +++ case ETHTOOL_A_CABLE_PAIR_D: +++ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; +++ break; +++ default: +++ return -EINVAL; +++ } +++ +++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); +++ if (val < 0) +++ return val; +++ +++ return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; +++} +++ +++static int qca808x_cable_test_start(struct phy_device *phydev) +++{ +++ int ret; +++ +++ /* perform CDT with the following configs: +++ * 1. disable hibernation. +++ * 2. force PHY working in MDI mode. +++ * 3. for PHY working in 1000BaseT. +++ * 4. configure the threshold. +++ */ +++ +++ ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); +++ if (ret < 0) +++ return ret; +++ +++ ret = at803x_config_mdix(phydev, ETH_TP_MDI); +++ if (ret < 0) +++ return ret; +++ +++ /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ +++ phydev->duplex = DUPLEX_FULL; +++ phydev->speed = SPEED_1000; +++ ret = genphy_c45_pma_setup_forced(phydev); +++ if (ret < 0) +++ return ret; +++ +++ ret = genphy_setup_forced(phydev); +++ if (ret < 0) +++ return ret; +++ +++ /* configure the thresholds for open, short, pair ok test */ +++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); +++ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); +++ +++ return 0; +++} +++ +++static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) +++{ +++ int ret, val; +++ int pair_a, pair_b, pair_c, pair_d; +++ +++ *finished = false; +++ +++ ret = at803x_cdt_start(phydev, 0); +++ if (ret) +++ return ret; +++ +++ ret = at803x_cdt_wait_for_completion(phydev); +++ if (ret) +++ return ret; +++ +++ val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); +++ if (val < 0) +++ return val; +++ +++ pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); +++ pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); +++ pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); +++ pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); +++ +++ ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, +++ qca808x_cable_test_result_trans(pair_a)); +++ ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, +++ qca808x_cable_test_result_trans(pair_b)); +++ ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, +++ qca808x_cable_test_result_trans(pair_c)); +++ ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, +++ qca808x_cable_test_result_trans(pair_d)); +++ +++ if (qca808x_cdt_fault_length_valid(pair_a)) +++ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, +++ qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); +++ if (qca808x_cdt_fault_length_valid(pair_b)) +++ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, +++ qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); +++ if (qca808x_cdt_fault_length_valid(pair_c)) +++ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, +++ qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); +++ if (qca808x_cdt_fault_length_valid(pair_d)) +++ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, +++ qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); +++ +++ *finished = true; +++ +++ return 0; +++} +++ ++ static struct phy_driver at803x_driver[] = { ++ { ++ /* Qualcomm Atheros AR8035 */ ++@@ -1848,6 +2033,7 @@ static struct phy_driver at803x_driver[] = { ++ /* Qualcomm QCA8081 */ ++ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), ++ .name = "Qualcomm QCA8081", +++ .flags = PHY_POLL_CABLE_TEST, ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .get_tunable = at803x_get_tunable, ++@@ -1861,6 +2047,8 @@ static struct phy_driver at803x_driver[] = { ++ .read_status = qca808x_read_status, ++ .config_init = qca808x_config_init, ++ .soft_reset = qca808x_soft_reset, +++ .cable_test_start = qca808x_cable_test_start, +++ .cable_test_get_status = qca808x_cable_test_get_status, ++ }, }; ++ ++ module_phy_driver(at803x_driver); ++-- ++2.34.1 ++ +diff --git a/target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch b/target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch +new file mode 100644 +index 0000000000..2bec96d306 +--- /dev/null ++++ b/target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch +@@ -0,0 +1,84 @@ ++From patchwork Sun Jan 30 10:25:28 2022 ++Content-Type: text/plain; charset="utf-8" ++MIME-Version: 1.0 ++Content-Transfer-Encoding: 7bit ++X-Patchwork-Submitter: Jonathan McDowell ++X-Patchwork-Id: 12729797 ++X-Patchwork-Delegate: kuba@kernel.org ++Return-Path: ++X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ++ aws-us-west-2-korg-lkml-1.web.codeaurora.org ++Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) ++ by smtp.lore.kernel.org (Postfix) with ESMTP id 1DD5EC433EF ++ for ; Sun, 30 Jan 2022 10:55:25 +0000 (UTC) ++Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand ++ id S240477AbiA3KzX (ORCPT ); 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++ bh=zynwQsXAChbzANQqprwMGE7qGv9t50Oo07QICLYU9a0=; b=Z ++ K8tRPtlmUhokQQlgSXpHDLec4xjYjkTQl6oFZ1GPCWgQy2YyrGnhNmtUr8GG4q3NR0jhiKh9A2y61 ++ pfq1eOPalgLqQ47fxD6JmCK8r/Sb6cXRKYN3OZ8NiEC9yhT8uxEqYe1tTUJL6RVfepb6+yFT5sp2Y ++ Osx4iy/QAibB+/8I6lhU5Tb35eztlYgE+/Mky3gIAhyM5kvHjcj4/S6i6Sw2UW27P3tuvH0JetOT6 ++ OFx58fSC5azHX6pNGqx+Na+tHVtfBMkIiOpdumXyswfZDNqGvg6eXTMPsSZUJ269N1dkqPLBB7Mwz ++ jtBcyMpAaEbN7MJWuh2h0DMYmTymlFFrg==; ++Received: from noodles by the.earth.li with local (Exim 4.94.2) ++ (envelope-from ) ++ id 1nE7Oi-00A0XI-KA; Sun, 30 Jan 2022 10:25:28 +0000 ++Date: Sun, 30 Jan 2022 10:25:28 +0000 ++From: Jonathan McDowell ++To: Andrew Lunn , ++ Heiner Kallweit , ++ Russell King , ++ David Miller , ++ Jakub Kicinski , Luo Jie ++Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, ++ Robert Marko ++Subject: [PATCH net] net: phy: Fix qca8081 with speeds lower than 2.5Gb/s ++Message-ID: ++MIME-Version: 1.0 ++Content-Disposition: inline ++Precedence: bulk ++List-ID: ++X-Mailing-List: netdev@vger.kernel.org ++X-Patchwork-Delegate: kuba@kernel.org ++ ++A typo in qca808x_read_status means we try to set SMII mode on the port ++rather than SGMII when the link speed is not 2.5Gb/s. This results in no ++traffic due to the mismatch in configuration between the phy and the ++mac. ++ ++Fixes: 79c7bc0521545 ("net: phy: add qca8081 read_status") ++Signed-off-by: Jonathan McDowell ++--- ++ drivers/net/phy/at803x.c | 2 +- ++ 1 file changed, 1 insertion(+), 1 deletion(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 5b6c0d120e09..7077e3a92d31 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -1691,7 +1691,7 @@ static int qca808x_read_status(struct phy_device *phydev) ++ if (phydev->link && phydev->speed == SPEED_2500) ++ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++ else ++- phydev->interface = PHY_INTERFACE_MODE_SMII; +++ phydev->interface = PHY_INTERFACE_MODE_SGMII; ++ ++ /* generate seed as a lower random value to make PHY linked as SLAVE easily, ++ * except for master/slave configuration fault detected. +-- +2.42.1 + diff --git a/build_patches/openwrt/0214-mvebu-rb5009-add-QCA8081-PHY-support-for-5.15.patch b/build_patches/openwrt/0214-mvebu-rb5009-add-QCA8081-PHY-support-for-5.15.patch new file mode 100644 index 00000000..89b93178 --- /dev/null +++ b/build_patches/openwrt/0214-mvebu-rb5009-add-QCA8081-PHY-support-for-5.15.patch @@ -0,0 +1,29 @@ +From 211bc4d66dd5b1c17ad85ed1a51bf202aa8c62b5 Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Sun, 18 Sep 2022 17:07:22 +0200 +Subject: [PATCH 14/18] mvebu: rb5009: add QCA8081 PHY support for 5.15 + +The required DT nodes area already in adrons's RB5009 DTS, so we +only need to enable the relevant kernel symbol in 5.15. + +Robimarko's tree use the 'qca8081' label whereas adrons's uses +the more generic 'switch0phy9' one. +--- + target/linux/mvebu/cortexa72/config-5.15 | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15 +index 5d7b5594aa..29d9ee3556 100644 +--- a/target/linux/mvebu/cortexa72/config-5.15 ++++ b/target/linux/mvebu/cortexa72/config-5.15 +@@ -36,6 +36,7 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y + # CONFIG_ARM_PL172_MPMC is not set + CONFIG_ARM_PSCI_FW=y + CONFIG_ARM_SBSA_WATCHDOG=y ++CONFIG_AT803X_PHY=y + CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y + CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y + # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +-- +2.42.1 + diff --git a/build_patches/openwrt/0215-generic-backport-5.18-AT803x-fiber-support-patch.patch b/build_patches/openwrt/0215-generic-backport-5.18-AT803x-fiber-support-patch.patch new file mode 100644 index 00000000..d79e72ce --- /dev/null +++ b/build_patches/openwrt/0215-generic-backport-5.18-AT803x-fiber-support-patch.patch @@ -0,0 +1,154 @@ +From e1abb1ddb7177391d9e02be985e5950d3dd233e0 Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Sat, 26 Aug 2023 12:08:34 +0200 +Subject: [PATCH 15/18] generic: backport 5.18 AT803x fiber support patch + +Commit e1242fc3390 backported some 5.18 AT803x patches, which were +modified to apply to 5.15. With the QCA8081 patches part of the 5.16 +merge window, those 5.18 AT803x patches need to be the actual upstream +ones; otherwise RB5009UG just hangs at boot time. + +Signed-off-by: Stijn Segers +--- + ...-01-net-phy-at803x-add-fiber-support.patch | 37 ++++++++++--------- + 1 file changed, 20 insertions(+), 17 deletions(-) + +diff --git a/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch b/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch +index 7cb21ed00d..989dc06ca6 100644 +--- a/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch ++++ b/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch +@@ -20,9 +20,11 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 76 +++++++++++++++++++++++++++++++++++----- + 1 file changed, 67 insertions(+), 9 deletions(-) + ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 052b2eb9f101f..3f3d4c164df40 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -48,6 +48,8 @@ ++@@ -51,6 +51,8 @@ + #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) + #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) + #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) +@@ -31,10 +33,11 @@ Signed-off-by: David S. Miller + #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) + #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) + #define AT803X_INTR_ENABLE_WOL BIT(0) +-@@ -82,6 +84,17 @@ ++@@ -85,7 +87,17 @@ ++ #define AT803X_DEBUG_DATA 0x1E + + #define AT803X_MODE_CFG_MASK 0x0F +- #define AT803X_MODE_CFG_SGMII 0x01 ++-#define AT803X_MODE_CFG_SGMII 0x01 + +#define AT803X_MODE_CFG_BASET_RGMII 0x00 + +#define AT803X_MODE_CFG_BASET_SGMII 0x01 + +#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 +@@ -49,7 +52,7 @@ Signed-off-by: David S. Miller + + #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ + #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 +-@@ -199,6 +212,8 @@ struct at803x_priv { ++@@ -283,6 +295,8 @@ struct at803x_priv { + u16 clk_25m_mask; + u8 smarteee_lpi_tw_1g; + u8 smarteee_lpi_tw_100m; +@@ -58,7 +61,7 @@ Signed-off-by: David S. Miller + struct regulator_dev *vddio_rdev; + struct regulator_dev *vddh_rdev; + struct regulator *vddio; +-@@ -674,7 +689,33 @@ static int at803x_probe(struct phy_devic ++@@ -784,7 +798,33 @@ static int at803x_probe(struct phy_device *phydev) + return ret; + } + +@@ -92,7 +95,7 @@ Signed-off-by: David S. Miller + } + + static void at803x_remove(struct phy_device *phydev) +-@@ -687,6 +728,7 @@ static void at803x_remove(struct phy_dev ++@@ -797,6 +837,7 @@ static void at803x_remove(struct phy_device *phydev) + + static int at803x_get_features(struct phy_device *phydev) + { +@@ -100,7 +103,7 @@ Signed-off-by: David S. Miller + int err; + + err = genphy_read_abilities(phydev); +-@@ -704,12 +746,13 @@ static int at803x_get_features(struct ph ++@@ -823,12 +864,13 @@ static int at803x_get_features(struct phy_device *phydev) + * As a result of that, ESTATUS_1000_XFULL is set + * to 1 even when operating in copper TP mode. + * +@@ -119,7 +122,7 @@ Signed-off-by: David S. Miller + return 0; + } + +-@@ -773,15 +816,18 @@ static int at8031_pll_config(struct phy_ ++@@ -892,15 +934,18 @@ static int at8031_pll_config(struct phy_device *phydev) + + static int at803x_config_init(struct phy_device *phydev) + { +@@ -141,7 +144,7 @@ Signed-off-by: David S. Miller + phy_unlock_mdio_bus(phydev); + if (ret) + return ret; +-@@ -840,6 +886,7 @@ static int at803x_ack_interrupt(struct p ++@@ -959,6 +1004,7 @@ static int at803x_ack_interrupt(struct phy_device *phydev) + + static int at803x_config_intr(struct phy_device *phydev) + { +@@ -149,7 +152,7 @@ Signed-off-by: David S. Miller + int err; + int value; + +-@@ -856,6 +903,10 @@ static int at803x_config_intr(struct phy ++@@ -975,6 +1021,10 @@ static int at803x_config_intr(struct phy_device *phydev) + value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; + value |= AT803X_INTR_ENABLE_LINK_FAIL; + value |= AT803X_INTR_ENABLE_LINK_SUCCESS; +@@ -160,12 +163,12 @@ Signed-off-by: David S. Miller + + err = phy_write(phydev, AT803X_INTR_ENABLE, value); + } else { +-@@ -923,8 +974,12 @@ static void at803x_link_change_notify(st ++@@ -1107,8 +1157,12 @@ static int at803x_read_specific_status(struct phy_device *phydev) + + static int at803x_read_status(struct phy_device *phydev) + { + + struct at803x_priv *priv = phydev->priv; +- int ss, err, old_link = phydev->link; ++ int err, old_link = phydev->link; + + + if (priv->is_1000basex) + + return genphy_c37_read_status(phydev); +@@ -173,7 +176,7 @@ Signed-off-by: David S. Miller + /* Update the link, but return if there was an error */ + err = genphy_update_link(phydev); + if (err) +-@@ -1023,6 +1078,7 @@ static int at803x_config_mdix(struct phy ++@@ -1162,6 +1216,7 @@ static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) + + static int at803x_config_aneg(struct phy_device *phydev) + { +@@ -181,13 +184,13 @@ Signed-off-by: David S. Miller + int ret; + + ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); +-@@ -1039,6 +1095,9 @@ static int at803x_config_aneg(struct phy ++@@ -1178,6 +1233,9 @@ static int at803x_config_aneg(struct phy_device *phydev) + return ret; + } + + + if (priv->is_1000basex) + + return genphy_c37_config_aneg(phydev); + + +- return genphy_config_aneg(phydev); +- } +- ++ /* Do not restart auto-negotiation by setting ret to 0 defautly, ++ * when calling __genphy_config_aneg later. ++ */ +-- +2.42.1 + diff --git a/build_patches/openwrt/0216-generic-replace-at803x-null-pointer-fix-with-upstrea.patch b/build_patches/openwrt/0216-generic-replace-at803x-null-pointer-fix-with-upstrea.patch new file mode 100644 index 00000000..e13b30f0 --- /dev/null +++ b/build_patches/openwrt/0216-generic-replace-at803x-null-pointer-fix-with-upstrea.patch @@ -0,0 +1,70 @@ +From fa76a94d8c10d66f0204500e3cb86969b6ba4bd7 Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Sat, 26 Aug 2023 12:13:58 +0200 +Subject: [PATCH 16/18] generic: replace at803x null pointer fix with upstream + one + +Signed-off-by: Stijn Segers +--- + ...LL-pointer-dereference-on-AR9331-PHY.patch | 27 +++++++++++++++++-- + 1 file changed, 25 insertions(+), 2 deletions(-) + +diff --git a/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch b/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch +index 53d6325c49..0ac5fda4a0 100644 +--- a/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch ++++ b/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch +@@ -1,8 +1,10 @@ +-From 9926de7315be3d606cc011a305ad9adb9e8e14c9 Mon Sep 17 00:00:00 2001 ++From 66fa352215e8455ba2e5f33793535795bd3e36ca Mon Sep 17 00:00:00 2001 + From: Oleksij Rempel + Date: Sat, 18 Jun 2022 14:23:33 +0200 + Subject: [PATCH] net: phy: at803x: fix NULL pointer dereference on AR9331 PHY + ++[ Upstream commit 9926de7315be3d606cc011a305ad9adb9e8e14c9 ] ++ + Latest kernel will explode on the PHY interrupt config, since it depends + now on allocated priv. So, run probe to allocate priv to fix it. + +@@ -39,13 +41,16 @@ Fixes: 3265f4218878 ("net: phy: at803x: add fiber support") + Signed-off-by: Oleksij Rempel + Reviewed-by: Andrew Lunn + Signed-off-by: David S. Miller ++Signed-off-by: Sasha Levin + --- + drivers/net/phy/at803x.c | 6 ++++++ + 1 file changed, 6 insertions(+) + ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 6a467e7817a6a..59fe356942b51 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -1592,6 +1592,8 @@ static struct phy_driver at803x_driver[] ++@@ -2072,6 +2072,8 @@ static struct phy_driver at803x_driver[] = { + /* ATHEROS AR9331 */ + PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), + .name = "Qualcomm Atheros AR9331 built-in PHY", +@@ -54,3 +59,21 @@ Signed-off-by: David S. Miller + .suspend = at803x_suspend, + .resume = at803x_resume, + .flags = PHY_POLL_CABLE_TEST, ++@@ -2087,6 +2089,8 @@ static struct phy_driver at803x_driver[] = { ++ /* Qualcomm Atheros QCA9561 */ ++ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), ++ .name = "Qualcomm Atheros QCA9561 built-in PHY", +++ .probe = at803x_probe, +++ .remove = at803x_remove, ++ .suspend = at803x_suspend, ++ .resume = at803x_resume, ++ .flags = PHY_POLL_CABLE_TEST, ++@@ -2151,6 +2155,8 @@ static struct phy_driver at803x_driver[] = { ++ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), ++ .name = "Qualcomm QCA8081", ++ .flags = PHY_POLL_CABLE_TEST, +++ .probe = at803x_probe, +++ .remove = at803x_remove, ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .get_tunable = at803x_get_tunable, +-- +2.42.1 + diff --git a/build_patches/openwrt/0217-kernel-replace-QCA8081-2.5Gb-patch-with-upstream-one.patch b/build_patches/openwrt/0217-kernel-replace-QCA8081-2.5Gb-patch-with-upstream-one.patch new file mode 100644 index 00000000..b5e805d3 --- /dev/null +++ b/build_patches/openwrt/0217-kernel-replace-QCA8081-2.5Gb-patch-with-upstream-one.patch @@ -0,0 +1,172 @@ +From 3202c7d6107b5c09d1995a23e8fb0625922789b3 Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Sat, 29 Apr 2023 16:35:49 +0200 +Subject: [PATCH 17/18] kernel: replace QCA8081 2.5Gb patch with upstream one + +The v2 of this patch was merged into 5.17. Drop the old patch +and replace it with v2. +--- + ...a8081-with-speeds-lower-than-2.5Gb-s.patch | 59 +++++++++++++ + ...a8081-with-speeds-lower-than-2.5Gb-s.patch | 84 ------------------- + 2 files changed, 59 insertions(+), 84 deletions(-) + create mode 100644 target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch + delete mode 100644 target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch + +diff --git a/target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch b/target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch +new file mode 100644 +index 0000000000..1d8e7997fd +--- /dev/null ++++ b/target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch +@@ -0,0 +1,59 @@ ++From 881cc731df6af99a21622e9be25a23b81adcd10b Mon Sep 17 00:00:00 2001 ++From: Jonathan McDowell ++Date: Mon, 31 Jan 2022 13:56:41 +0000 ++Subject: [PATCH] net: phy: Fix qca8081 with speeds lower than 2.5Gb/s ++ ++A typo in qca808x_read_status means we try to set SMII mode on the port ++rather than SGMII when the link speed is not 2.5Gb/s. This results in no ++traffic due to the mismatch in configuration between the phy and the ++mac. ++ ++v2: ++ Only change interface mode when the link is up ++ ++Fixes: 79c7bc0521545 ("net: phy: add qca8081 read_status") ++Cc: stable@vger.kernel.org ++Signed-off-by: Jonathan McDowell ++Reviewed-by: Russell King (Oracle) ++Signed-off-by: David S. Miller ++--- ++ drivers/net/phy/at803x.c | 26 +++++++++++++------------- ++ 1 file changed, 13 insertions(+), 13 deletions(-) ++ ++diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c ++index 5b6c0d120e09e2..29aa811af430f0 100644 ++--- a/drivers/net/phy/at803x.c +++++ b/drivers/net/phy/at803x.c ++@@ -1688,19 +1688,19 @@ static int qca808x_read_status(struct phy_device *phydev) ++ if (ret < 0) ++ return ret; ++ ++- if (phydev->link && phydev->speed == SPEED_2500) ++- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++- else ++- phydev->interface = PHY_INTERFACE_MODE_SMII; ++- ++- /* generate seed as a lower random value to make PHY linked as SLAVE easily, ++- * except for master/slave configuration fault detected. ++- * the reason for not putting this code into the function link_change_notify is ++- * the corner case where the link partner is also the qca8081 PHY and the seed ++- * value is configured as the same value, the link can't be up and no link change ++- * occurs. ++- */ ++- if (!phydev->link) { +++ if (phydev->link) { +++ if (phydev->speed == SPEED_2500) +++ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +++ else +++ phydev->interface = PHY_INTERFACE_MODE_SGMII; +++ } else { +++ /* generate seed as a lower random value to make PHY linked as SLAVE easily, +++ * except for master/slave configuration fault detected. +++ * the reason for not putting this code into the function link_change_notify is +++ * the corner case where the link partner is also the qca8081 PHY and the seed +++ * value is configured as the same value, the link can't be up and no link change +++ * occurs. +++ */ ++ if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { ++ qca808x_phy_ms_seed_enable(phydev, false); ++ } else { +diff --git a/target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch b/target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch +deleted file mode 100644 +index 2bec96d306..0000000000 +--- a/target/linux/generic/pending-5.15/790-net-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch ++++ /dev/null +@@ -1,84 +0,0 @@ +-From patchwork Sun Jan 30 10:25:28 2022 +-Content-Type: text/plain; charset="utf-8" +-MIME-Version: 1.0 +-Content-Transfer-Encoding: 7bit +-X-Patchwork-Submitter: Jonathan McDowell +-X-Patchwork-Id: 12729797 +-X-Patchwork-Delegate: kuba@kernel.org +-Return-Path: +-X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on +- aws-us-west-2-korg-lkml-1.web.codeaurora.org +-Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) +- by smtp.lore.kernel.org (Postfix) with ESMTP id 1DD5EC433EF +- for ; Sun, 30 Jan 2022 10:55:25 +0000 (UTC) +-Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand +- id S240477AbiA3KzX (ORCPT ); +- Sun, 30 Jan 2022 05:55:23 -0500 +-Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36812 "EHLO +- lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org +- with ESMTP id S239076AbiA3KzV (ORCPT +- ); Sun, 30 Jan 2022 05:55:21 -0500 +-X-Greylist: delayed 1780 seconds by postgrey-1.37 at +- lindbergh.monkeyblade.net; Sun, 30 Jan 2022 02:55:21 PST +-Received: from the.earth.li (the.earth.li +- [IPv6:2a00:1098:86:4d:c0ff:ee:15:900d]) +- by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EAD9C061714; +- Sun, 30 Jan 2022 02:55:21 -0800 (PST) +-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=earth.li; +- s=the; +- h=Content-Type:MIME-Version:Message-ID:Subject:Cc:To:From:Date:Sender: +- Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date +- :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: +- References:List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post: +- List-Owner:List-Archive; +- bh=zynwQsXAChbzANQqprwMGE7qGv9t50Oo07QICLYU9a0=; b=Z +- K8tRPtlmUhokQQlgSXpHDLec4xjYjkTQl6oFZ1GPCWgQy2YyrGnhNmtUr8GG4q3NR0jhiKh9A2y61 +- pfq1eOPalgLqQ47fxD6JmCK8r/Sb6cXRKYN3OZ8NiEC9yhT8uxEqYe1tTUJL6RVfepb6+yFT5sp2Y +- Osx4iy/QAibB+/8I6lhU5Tb35eztlYgE+/Mky3gIAhyM5kvHjcj4/S6i6Sw2UW27P3tuvH0JetOT6 +- OFx58fSC5azHX6pNGqx+Na+tHVtfBMkIiOpdumXyswfZDNqGvg6eXTMPsSZUJ269N1dkqPLBB7Mwz +- jtBcyMpAaEbN7MJWuh2h0DMYmTymlFFrg==; +-Received: from noodles by the.earth.li with local (Exim 4.94.2) +- (envelope-from ) +- id 1nE7Oi-00A0XI-KA; Sun, 30 Jan 2022 10:25:28 +0000 +-Date: Sun, 30 Jan 2022 10:25:28 +0000 +-From: Jonathan McDowell +-To: Andrew Lunn , +- Heiner Kallweit , +- Russell King , +- David Miller , +- Jakub Kicinski , Luo Jie +-Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, +- Robert Marko +-Subject: [PATCH net] net: phy: Fix qca8081 with speeds lower than 2.5Gb/s +-Message-ID: +-MIME-Version: 1.0 +-Content-Disposition: inline +-Precedence: bulk +-List-ID: +-X-Mailing-List: netdev@vger.kernel.org +-X-Patchwork-Delegate: kuba@kernel.org +- +-A typo in qca808x_read_status means we try to set SMII mode on the port +-rather than SGMII when the link speed is not 2.5Gb/s. This results in no +-traffic due to the mismatch in configuration between the phy and the +-mac. +- +-Fixes: 79c7bc0521545 ("net: phy: add qca8081 read_status") +-Signed-off-by: Jonathan McDowell +---- +- drivers/net/phy/at803x.c | 2 +- +- 1 file changed, 1 insertion(+), 1 deletion(-) +- +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 5b6c0d120e09..7077e3a92d31 100644 +---- a/drivers/net/phy/at803x.c +-+++ b/drivers/net/phy/at803x.c +-@@ -1691,7 +1691,7 @@ static int qca808x_read_status(struct phy_device *phydev) +- if (phydev->link && phydev->speed == SPEED_2500) +- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- else +-- phydev->interface = PHY_INTERFACE_MODE_SMII; +-+ phydev->interface = PHY_INTERFACE_MODE_SGMII; +- +- /* generate seed as a lower random value to make PHY linked as SLAVE easily, +- * except for master/slave configuration fault detected. +-- +2.42.1 + diff --git a/build_patches/openwrt/0218-kernel-5.15-refresh-RB5009UG-patches.patch b/build_patches/openwrt/0218-kernel-5.15-refresh-RB5009UG-patches.patch new file mode 100644 index 00000000..0108883d --- /dev/null +++ b/build_patches/openwrt/0218-kernel-5.15-refresh-RB5009UG-patches.patch @@ -0,0 +1,890 @@ +From 68fc4f780968f0f76bc6eebda329b525542ccd5e Mon Sep 17 00:00:00 2001 +From: Stijn Segers +Date: Sat, 26 Aug 2023 12:35:10 +0200 +Subject: [PATCH 18/18] kernel: 5.15: refresh RB5009UG patches + +Signed-off-by: Stijn Segers +--- + ...eplace-AT803X_DEVICE_ADDR-with-MDIO_.patch | 9 ++------ + ...-v5.16-net-phy-at803x-use-phy_modify.patch | 7 +------ + ...t-phy-at803x-improve-the-WOL-feature.patch | 11 +++------- + ...-at803x-use-GENMASK-for-speed-status.patch | 7 +------ + ...6-net-phy-at803x-add-QCA9561-support.patch | 21 +++++++------------ + ...-phy-add-qca8081-ethernet-phy-driver.patch | 9 ++------ + ...5.16-net-phy-add-qca8081-read_status.patch | 17 ++++++--------- + ....16-net-phy-add-qca8081-get_features.patch | 9 ++------ + ...5.16-net-phy-add-qca8081-config_aneg.patch | 9 ++------ + ...tants-for-fast-retrain-related-regis.patch | 5 ----- + ...-net-phy-add-genphy_c45_fast_retrain.patch | 11 ++-------- + ...5.16-net-phy-add-qca8081-config_init.patch | 9 ++------ + ...081-soft_reset-and-enable-master-sla.patch | 13 ++++-------- + ...ca8081-master-slave-seed-value-if-li.patch | 7 +------ + ...5.16-net-phy-add-qca8081-cdt-feature.patch | 15 +++++-------- + ...a8081-with-speeds-lower-than-2.5Gb-s.patch | 4 +--- + ...-01-net-phy-at803x-add-fiber-support.patch | 20 ++++++++---------- + ...y-at803x-support-downstream-SFP-cage.patch | 4 ++-- + ...LL-pointer-dereference-on-AR9331-PHY.patch | 8 +++---- + ...ix-error-return-code-in-at803x_probe.patch | 2 +- + ...x-add-Amethyst-specific-SMI-GPIO-fun.patch | 15 +++---------- + 21 files changed, 60 insertions(+), 152 deletions(-) + +diff --git a/target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch b/target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch +index 2b0b24e62c..5678f064bd 100644 +--- a/target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch ++++ b/target/linux/generic/backport-5.15/765-v5.16-net-phy-at803x-replace-AT803X_DEVICE_ADDR-with-MDIO_.patch +@@ -14,8 +14,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 69da011e82c8..d0f41cdaec75 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -70,7 +70,6 @@ +@@ -26,7 +24,7 @@ index 69da011e82c8..d0f41cdaec75 100644 + #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C + #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B + #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A +-@@ -338,7 +337,8 @@ static int at803x_set_wol(struct phy_device *phydev, ++@@ -337,7 +336,8 @@ static int at803x_set_wol(struct phy_dev + const u8 *mac; + int ret; + u32 value; +@@ -36,7 +34,7 @@ index 69da011e82c8..d0f41cdaec75 100644 + AT803X_LOC_MAC_ADDR_32_47_OFFSET, + AT803X_LOC_MAC_ADDR_16_31_OFFSET, + AT803X_LOC_MAC_ADDR_0_15_OFFSET, +-@@ -354,7 +354,7 @@ static int at803x_set_wol(struct phy_device *phydev, ++@@ -353,7 +353,7 @@ static int at803x_set_wol(struct phy_dev + return -EINVAL; + + for (i = 0; i < 3; i++) +@@ -45,6 +43,3 @@ index 69da011e82c8..d0f41cdaec75 100644 + mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); + + value = phy_read(phydev, AT803X_INTR_ENABLE); +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch b/target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch +index fbd7de0519..be1befa69d 100644 +--- a/target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch ++++ b/target/linux/generic/backport-5.15/766-v5.16-net-phy-at803x-use-phy_modify.patch +@@ -13,11 +13,9 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index d0f41cdaec75..cf25cd428ffa 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -357,16 +357,12 @@ static int at803x_set_wol(struct phy_device *phydev, ++@@ -356,16 +356,12 @@ static int at803x_set_wol(struct phy_dev + phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], + mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); + +@@ -36,6 +34,3 @@ index d0f41cdaec75..cf25cd428ffa 100644 + if (ret) + return ret; + value = phy_read(phydev, AT803X_INTR_STATUS); +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch b/target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch +index 1109e0a81e..e6edf2ce21 100644 +--- a/target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch ++++ b/target/linux/generic/backport-5.15/767-v5.16-net-phy-at803x-improve-the-WOL-feature.patch +@@ -19,8 +19,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 45 +++++++++++++++++++++++++++++++++------- + 1 file changed, 38 insertions(+), 7 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index cf25cd428ffa..1363f12ba659 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -70,6 +70,8 @@ +@@ -32,7 +30,7 @@ index cf25cd428ffa..1363f12ba659 100644 + #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C + #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B + #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A +-@@ -335,8 +337,7 @@ static int at803x_set_wol(struct phy_device *phydev, ++@@ -334,8 +336,7 @@ static int at803x_set_wol(struct phy_dev + { + struct net_device *ndev = phydev->attached_dev; + const u8 *mac; +@@ -42,7 +40,7 @@ index cf25cd428ffa..1363f12ba659 100644 + unsigned int i; + const unsigned int offsets[] = { + AT803X_LOC_MAC_ADDR_32_47_OFFSET, +-@@ -357,18 +358,45 @@ static int at803x_set_wol(struct phy_device *phydev, ++@@ -356,18 +357,45 @@ static int at803x_set_wol(struct phy_dev + phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], + mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); + +@@ -91,7 +89,7 @@ index cf25cd428ffa..1363f12ba659 100644 + } + + static void at803x_get_wol(struct phy_device *phydev, +-@@ -379,8 +407,11 @@ static void at803x_get_wol(struct phy_device *phydev, ++@@ -378,8 +406,11 @@ static void at803x_get_wol(struct phy_de + wol->supported = WAKE_MAGIC; + wol->wolopts = 0; + +@@ -105,6 +103,3 @@ index cf25cd428ffa..1363f12ba659 100644 + wol->wolopts |= WAKE_MAGIC; + } + +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch b/target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch +index 534878a266..f8420c8d1f 100644 +--- a/target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch ++++ b/target/linux/generic/backport-5.15/768-v5.16-net-phy-at803x-use-GENMASK-for-speed-status.patch +@@ -12,8 +12,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 1363f12ba659..3465f2bb6356 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -33,10 +33,10 @@ +@@ -31,7 +29,7 @@ index 1363f12ba659..3465f2bb6356 100644 + #define AT803X_SS_DUPLEX BIT(13) + #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) + #define AT803X_SS_MDIX BIT(6) +-@@ -994,7 +994,7 @@ static int at803x_read_status(struct phy_device *phydev) ++@@ -985,7 +985,7 @@ static int at803x_read_status(struct phy + if (sfc < 0) + return sfc; + +@@ -40,6 +38,3 @@ index 1363f12ba659..3465f2bb6356 100644 + case AT803X_SS_SPEED_10: + phydev->speed = SPEED_10; + break; +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch b/target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch +index 48fbac610a..68e7eae7bb 100644 +--- a/target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch ++++ b/target/linux/generic/backport-5.15/769-0-v5.16-net-phy-at803x-add-QCA9561-support.patch +@@ -17,11 +17,9 @@ Signed-off-by: Jakub Kicinski + drivers/net/phy/at803x.c | 23 +++++++++++++++++++++-- + 1 file changed, 21 insertions(+), 2 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 3feee4d59030..ae7e1f1c59f0 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -153,6 +153,7 @@ ++@@ -161,6 +161,7 @@ + #define QCA8327_A_PHY_ID 0x004dd033 + #define QCA8327_B_PHY_ID 0x004dd034 + #define QCA8337_PHY_ID 0x004dd036 +@@ -29,7 +27,7 @@ index 3feee4d59030..ae7e1f1c59f0 100644 + #define QCA8K_PHY_ID_MASK 0xffffffff + + #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) +-@@ -1237,7 +1238,8 @@ static int at803x_cable_test_get_status(struct phy_device *phydev, ++@@ -1263,7 +1264,8 @@ static int at803x_cable_test_get_status( + int pair, ret; + + if (phydev->phy_id == ATH9331_PHY_ID || +@@ -39,7 +37,7 @@ index 3feee4d59030..ae7e1f1c59f0 100644 + pair_mask = 0x3; + else + pair_mask = 0xf; +-@@ -1277,7 +1279,8 @@ static int at803x_cable_test_start(struct phy_device *phydev) ++@@ -1303,7 +1305,8 @@ static int at803x_cable_test_start(struc + phy_write(phydev, MII_BMCR, BMCR_ANENABLE); + phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); + if (phydev->phy_id != ATH9331_PHY_ID && +@@ -49,11 +47,10 @@ index 3feee4d59030..ae7e1f1c59f0 100644 + phy_write(phydev, MII_CTRL1000, 0); + + /* we do all the (time consuming) work later */ +-@@ -1408,6 +1411,21 @@ static struct phy_driver at803x_driver[] = { +- .read_status = at803x_read_status, ++@@ -1516,6 +1519,21 @@ static struct phy_driver at803x_driver[] + .soft_reset = genphy_soft_reset, + .config_aneg = at803x_config_aneg, +-+}, { ++ }, { + + /* Qualcomm Atheros QCA9561 */ + + PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), + + .name = "Qualcomm Atheros QCA9561 built-in PHY", +@@ -68,10 +65,11 @@ index 3feee4d59030..ae7e1f1c59f0 100644 + + .read_status = at803x_read_status, + + .soft_reset = genphy_soft_reset, + + .config_aneg = at803x_config_aneg, +- }, { +++}, { + /* QCA8337 */ + .phy_id = QCA8337_PHY_ID, +-@@ -1466,6 +1484,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { ++ .phy_id_mask = QCA8K_PHY_ID_MASK, ++@@ -1576,6 +1594,7 @@ static struct mdio_device_id __maybe_unu + { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, +@@ -79,6 +77,3 @@ index 3feee4d59030..ae7e1f1c59f0 100644 + { } + }; + +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch b/target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch +index 1aec1eae60..0b09503898 100644 +--- a/target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch ++++ b/target/linux/generic/backport-5.15/769-v5.16-net-phy-add-qca8081-ethernet-phy-driver.patch +@@ -16,8 +16,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 3465f2bb6356..aae27fe3e1e1 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -158,6 +158,8 @@ +@@ -38,7 +36,7 @@ index 3465f2bb6356..aae27fe3e1e1 100644 + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); + +-@@ -1591,6 +1593,18 @@ static struct phy_driver at803x_driver[] = { ++@@ -1581,6 +1583,18 @@ static struct phy_driver at803x_driver[] + .get_stats = at803x_get_stats, + .suspend = qca83xx_suspend, + .resume = qca83xx_resume, +@@ -57,7 +55,7 @@ index 3465f2bb6356..aae27fe3e1e1 100644 + }, }; + + module_phy_driver(at803x_driver); +-@@ -1605,6 +1619,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { ++@@ -1595,6 +1609,7 @@ static struct mdio_device_id __maybe_unu + { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, +@@ -65,6 +63,3 @@ index 3465f2bb6356..aae27fe3e1e1 100644 + { } + }; + +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch b/target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch +index 3e7572b034..bbaf30eeb8 100644 +--- a/target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch ++++ b/target/linux/generic/backport-5.15/770-v5.16-net-phy-add-qca8081-read_status.patch +@@ -17,8 +17,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 95 ++++++++++++++++++++++++++++++---------- + 1 file changed, 73 insertions(+), 22 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index aae27fe3e1e1..cecf78e6c643 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -41,6 +41,9 @@ +@@ -31,7 +29,7 @@ index aae27fe3e1e1..cecf78e6c643 100644 + #define AT803X_INTR_ENABLE 0x12 + #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) + #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) +-@@ -959,27 +962,9 @@ static void at803x_link_change_notify(struct phy_device *phydev) ++@@ -951,27 +954,9 @@ static void at803x_link_change_notify(st + } + } + +@@ -61,7 +59,7 @@ index aae27fe3e1e1..cecf78e6c643 100644 + + /* Read the AT8035 PHY-Specific Status register, which indicates the + * speed and duplex that the PHY is actually using, irrespective of +-@@ -990,13 +975,19 @@ static int at803x_read_status(struct phy_device *phydev) ++@@ -982,13 +967,19 @@ static int at803x_read_status(struct phy + return ss; + + if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { +@@ -83,7 +81,7 @@ index aae27fe3e1e1..cecf78e6c643 100644 + case AT803X_SS_SPEED_10: + phydev->speed = SPEED_10; + break; +-@@ -1006,6 +997,9 @@ static int at803x_read_status(struct phy_device *phydev) ++@@ -998,6 +989,9 @@ static int at803x_read_status(struct phy + case AT803X_SS_SPEED_1000: + phydev->speed = SPEED_1000; + break; +@@ -93,7 +91,7 @@ index aae27fe3e1e1..cecf78e6c643 100644 + } + if (ss & AT803X_SS_DUPLEX) + phydev->duplex = DUPLEX_FULL; +-@@ -1030,6 +1024,35 @@ static int at803x_read_status(struct phy_device *phydev) ++@@ -1022,6 +1016,35 @@ static int at803x_read_status(struct phy + } + } + +@@ -129,7 +127,7 @@ index aae27fe3e1e1..cecf78e6c643 100644 + if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) + phy_resolve_aneg_pause(phydev); + +-@@ -1434,6 +1457,33 @@ static int qca83xx_suspend(struct phy_device *phydev) ++@@ -1426,6 +1449,33 @@ static int qca83xx_suspend(struct phy_de + return 0; + } + +@@ -163,7 +161,7 @@ index aae27fe3e1e1..cecf78e6c643 100644 + static struct phy_driver at803x_driver[] = { + { + /* Qualcomm Atheros AR8035 */ +-@@ -1605,6 +1655,7 @@ static struct phy_driver at803x_driver[] = { ++@@ -1595,6 +1645,7 @@ static struct phy_driver at803x_driver[] + .get_wol = at803x_get_wol, + .suspend = genphy_suspend, + .resume = genphy_resume, +@@ -171,6 +169,3 @@ index aae27fe3e1e1..cecf78e6c643 100644 + }, }; + + module_phy_driver(at803x_driver); +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch b/target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch +index 7cc6a79e7b..1408a2a403 100644 +--- a/target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch ++++ b/target/linux/generic/backport-5.15/771-v5.16-net-phy-add-qca8081-get_features.patch +@@ -13,11 +13,9 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index cecf78e6c643..c4b7ac03cd35 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -744,6 +744,15 @@ static int at803x_get_features(struct phy_device *phydev) ++@@ -726,6 +726,15 @@ static int at803x_get_features(struct ph + if (err) + return err; + +@@ -33,7 +31,7 @@ index cecf78e6c643..c4b7ac03cd35 100644 + if (phydev->drv->phy_id != ATH8031_PHY_ID) + return 0; + +-@@ -1653,6 +1662,7 @@ static struct phy_driver at803x_driver[] = { ++@@ -1643,6 +1652,7 @@ static struct phy_driver at803x_driver[] + .set_tunable = at803x_set_tunable, + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, +@@ -41,6 +39,3 @@ index cecf78e6c643..c4b7ac03cd35 100644 + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch b/target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch +index 2b9b2edbf8..ebf524bcf4 100644 +--- a/target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch ++++ b/target/linux/generic/backport-5.15/772-v5.16-net-phy-add-qca8081-config_aneg.patch +@@ -13,11 +13,9 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 26 +++++++++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index c4b7ac03cd35..70c1025e8e5d 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -1109,7 +1109,30 @@ static int at803x_config_aneg(struct phy_device *phydev) ++@@ -1101,7 +1101,30 @@ static int at803x_config_aneg(struct phy + return ret; + } + +@@ -49,7 +47,7 @@ index c4b7ac03cd35..70c1025e8e5d 100644 + } + + static int at803x_get_downshift(struct phy_device *phydev, u8 *d) +-@@ -1663,6 +1686,7 @@ static struct phy_driver at803x_driver[] = { ++@@ -1653,6 +1676,7 @@ static struct phy_driver at803x_driver[] + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, + .get_features = at803x_get_features, +@@ -57,6 +55,3 @@ index c4b7ac03cd35..70c1025e8e5d 100644 + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch b/target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch +index 31c08efc85..bddbdb9f87 100644 +--- a/target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch ++++ b/target/linux/generic/backport-5.15/773-v5-16-net-phy-add-constants-for-fast-retrain-related-regis.patch +@@ -15,8 +15,6 @@ Signed-off-by: David S. Miller + include/uapi/linux/mdio.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +-diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h +-index bdf77dffa5a4..c54e6eae5366 100644 + --- a/include/uapi/linux/mdio.h + +++ b/include/uapi/linux/mdio.h + @@ -53,12 +53,14 @@ +@@ -62,6 +60,3 @@ index bdf77dffa5a4..c54e6eae5366 100644 + /* 2.5G/5G Extended abilities register. */ + #define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */ + #define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */ +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch b/target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch +index 0cf37833f6..8aca8c1925 100644 +--- a/target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch ++++ b/target/linux/generic/backport-5.15/774-v5.16-net-phy-add-genphy_c45_fast_retrain.patch +@@ -13,11 +13,9 @@ Signed-off-by: David S. Miller + include/linux/phy.h | 1 + + 2 files changed, 35 insertions(+) + +-diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c +-index c617dbcad6ea..b01180e1f578 100644 + --- a/drivers/net/phy/phy-c45.c + +++ b/drivers/net/phy/phy-c45.c +-@@ -611,6 +611,40 @@ int genphy_c45_loopback(struct phy_device *phydev, bool enable) ++@@ -611,6 +611,40 @@ int genphy_c45_loopback(struct phy_devic + } + EXPORT_SYMBOL_GPL(genphy_c45_loopback); + +@@ -58,11 +56,9 @@ index c617dbcad6ea..b01180e1f578 100644 + struct phy_driver genphy_c45_driver = { + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, +-diff --git a/include/linux/phy.h b/include/linux/phy.h +-index 736e1d1a47c4..04e90423fa88 100644 + --- a/include/linux/phy.h + +++ b/include/linux/phy.h +-@@ -1584,6 +1584,7 @@ int genphy_c45_config_aneg(struct phy_device *phydev); ++@@ -1624,6 +1624,7 @@ int genphy_c45_config_aneg(struct phy_de + int genphy_c45_loopback(struct phy_device *phydev, bool enable); + int genphy_c45_pma_resume(struct phy_device *phydev); + int genphy_c45_pma_suspend(struct phy_device *phydev); +@@ -70,6 +66,3 @@ index 736e1d1a47c4..04e90423fa88 100644 + + /* Generic C45 PHY driver */ + extern struct phy_driver genphy_c45_driver; +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch b/target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch +index 9c27de67b3..6d2aae0d97 100644 +--- a/target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch ++++ b/target/linux/generic/backport-5.15/775-v5.16-net-phy-add-qca8081-config_init.patch +@@ -15,8 +15,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 107 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 107 insertions(+) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 70c1025e8e5d..da710523b7c4 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -178,6 +178,51 @@ +@@ -71,7 +69,7 @@ index 70c1025e8e5d..da710523b7c4 100644 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); +-@@ -1489,6 +1534,67 @@ static int qca83xx_suspend(struct phy_device *phydev) ++@@ -1481,6 +1526,67 @@ static int qca83xx_suspend(struct phy_de + return 0; + } + +@@ -139,7 +137,7 @@ index 70c1025e8e5d..da710523b7c4 100644 + static int qca808x_read_status(struct phy_device *phydev) + { + int ret; +-@@ -1690,6 +1796,7 @@ static struct phy_driver at803x_driver[] = { ++@@ -1680,6 +1786,7 @@ static struct phy_driver at803x_driver[] + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, +@@ -147,6 +145,3 @@ index 70c1025e8e5d..da710523b7c4 100644 + }, }; + + module_phy_driver(at803x_driver); +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch b/target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch +index bf34b4bdfb..6ddbad3a06 100644 +--- a/target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch ++++ b/target/linux/generic/backport-5.15/776-v5.16-net-phy-add-qca8081-soft_reset-and-enable-master-sla.patch +@@ -15,8 +15,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 48 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 48 insertions(+) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index da710523b7c4..1418db4f2091 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -223,6 +223,12 @@ +@@ -32,7 +30,7 @@ index da710523b7c4..1418db4f2091 100644 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); +-@@ -1569,6 +1575,26 @@ static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) ++@@ -1561,6 +1567,26 @@ static int qca808x_phy_fast_retrain_conf + return 0; + } + +@@ -59,7 +57,7 @@ index da710523b7c4..1418db4f2091 100644 + static int qca808x_config_init(struct phy_device *phydev) + { + int ret; +-@@ -1590,6 +1616,16 @@ static int qca808x_config_init(struct phy_device *phydev) ++@@ -1582,6 +1608,16 @@ static int qca808x_config_init(struct ph + if (ret) + return ret; + +@@ -76,7 +74,7 @@ index da710523b7c4..1418db4f2091 100644 + /* Configure adc threshold as 100mv for the link 10M */ + return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, + QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); +-@@ -1622,6 +1658,17 @@ static int qca808x_read_status(struct phy_device *phydev) ++@@ -1614,6 +1650,17 @@ static int qca808x_read_status(struct ph + return 0; + } + +@@ -94,7 +92,7 @@ index da710523b7c4..1418db4f2091 100644 + static struct phy_driver at803x_driver[] = { + { + /* Qualcomm Atheros AR8035 */ +-@@ -1797,6 +1844,7 @@ static struct phy_driver at803x_driver[] = { ++@@ -1787,6 +1834,7 @@ static struct phy_driver at803x_driver[] + .resume = genphy_resume, + .read_status = qca808x_read_status, + .config_init = qca808x_config_init, +@@ -102,6 +100,3 @@ index da710523b7c4..1418db4f2091 100644 + }, }; + + module_phy_driver(at803x_driver); +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch b/target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch +index 1f614e99a4..c0ed0d770a 100644 +--- a/target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch ++++ b/target/linux/generic/backport-5.15/777-v5.16-net-phy-adjust-qca8081-master-slave-seed-value-if-li.patch +@@ -19,11 +19,9 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 1418db4f2091..00733badcda5 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -1655,6 +1655,22 @@ static int qca808x_read_status(struct phy_device *phydev) ++@@ -1647,6 +1647,22 @@ static int qca808x_read_status(struct ph + else + phydev->interface = PHY_INTERFACE_MODE_SMII; + +@@ -46,6 +44,3 @@ index 1418db4f2091..00733badcda5 100644 + return 0; + } + +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch b/target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch +index d49fb2f566..ecdc902dfd 100644 +--- a/target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch ++++ b/target/linux/generic/backport-5.15/778-v5.16-net-phy-add-qca8081-cdt-feature.patch +@@ -16,8 +16,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 194 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 191 insertions(+), 3 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 00733badcda5..f1cbe1f6ddec 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -229,6 +229,32 @@ +@@ -53,7 +51,7 @@ index 00733badcda5..f1cbe1f6ddec 100644 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi"); + MODULE_LICENSE("GPL"); +-@@ -1319,8 +1345,14 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) ++@@ -1311,8 +1337,14 @@ static int at803x_cdt_start(struct phy_d + { + u16 cdt; + +@@ -70,7 +68,7 @@ index 00733badcda5..f1cbe1f6ddec 100644 + + return phy_write(phydev, AT803X_CDT, cdt); + } +-@@ -1328,10 +1360,16 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) ++@@ -1320,10 +1352,16 @@ static int at803x_cdt_start(struct phy_d + static int at803x_cdt_wait_for_completion(struct phy_device *phydev) + { + int val, ret; +@@ -88,7 +86,7 @@ index 00733badcda5..f1cbe1f6ddec 100644 + 30000, 100000, true); + + return ret < 0 ? ret : 0; +-@@ -1685,6 +1723,153 @@ static int qca808x_soft_reset(struct phy_device *phydev) ++@@ -1677,6 +1715,153 @@ static int qca808x_soft_reset(struct phy + return qca808x_phy_ms_seed_enable(phydev, true); + } + +@@ -242,7 +240,7 @@ index 00733badcda5..f1cbe1f6ddec 100644 + static struct phy_driver at803x_driver[] = { + { + /* Qualcomm Atheros AR8035 */ +-@@ -1848,6 +2033,7 @@ static struct phy_driver at803x_driver[] = { ++@@ -1838,6 +2023,7 @@ static struct phy_driver at803x_driver[] + /* Qualcomm QCA8081 */ + PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), + .name = "Qualcomm QCA8081", +@@ -250,7 +248,7 @@ index 00733badcda5..f1cbe1f6ddec 100644 + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .get_tunable = at803x_get_tunable, +-@@ -1861,6 +2047,8 @@ static struct phy_driver at803x_driver[] = { ++@@ -1851,6 +2037,8 @@ static struct phy_driver at803x_driver[] + .read_status = qca808x_read_status, + .config_init = qca808x_config_init, + .soft_reset = qca808x_soft_reset, +@@ -259,6 +257,3 @@ index 00733badcda5..f1cbe1f6ddec 100644 + }, }; + + module_phy_driver(at803x_driver); +--- +-2.34.1 +- +diff --git a/target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch b/target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch +index 1d8e7997fd..566be8f958 100644 +--- a/target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch ++++ b/target/linux/generic/backport-5.15/778-v5.17-net-phy-Fix-qca8081-with-speeds-lower-than-2.5Gb-s.patch +@@ -20,11 +20,9 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 26 +++++++++++++------------- + 1 file changed, 13 insertions(+), 13 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 5b6c0d120e09e2..29aa811af430f0 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -1688,19 +1688,19 @@ static int qca808x_read_status(struct phy_device *phydev) ++@@ -1680,19 +1680,19 @@ static int qca808x_read_status(struct ph + if (ret < 0) + return ret; + +diff --git a/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch b/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch +index 989dc06ca6..46bbfa0cae 100644 +--- a/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch ++++ b/target/linux/generic/backport-5.15/778-v5.18-01-net-phy-at803x-add-fiber-support.patch +@@ -20,8 +20,6 @@ Signed-off-by: David S. Miller + drivers/net/phy/at803x.c | 76 +++++++++++++++++++++++++++++++++++----- + 1 file changed, 67 insertions(+), 9 deletions(-) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 052b2eb9f101f..3f3d4c164df40 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c + @@ -51,6 +51,8 @@ +@@ -61,7 +59,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + struct regulator_dev *vddio_rdev; + struct regulator_dev *vddh_rdev; + struct regulator *vddio; +-@@ -784,7 +798,33 @@ static int at803x_probe(struct phy_device *phydev) ++@@ -784,7 +798,33 @@ static int at803x_probe(struct phy_devic + return ret; + } + +@@ -95,7 +93,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + } + + static void at803x_remove(struct phy_device *phydev) +-@@ -797,6 +837,7 @@ static void at803x_remove(struct phy_device *phydev) ++@@ -797,6 +837,7 @@ static void at803x_remove(struct phy_dev + + static int at803x_get_features(struct phy_device *phydev) + { +@@ -103,7 +101,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + int err; + + err = genphy_read_abilities(phydev); +-@@ -823,12 +864,13 @@ static int at803x_get_features(struct phy_device *phydev) ++@@ -823,12 +864,13 @@ static int at803x_get_features(struct ph + * As a result of that, ESTATUS_1000_XFULL is set + * to 1 even when operating in copper TP mode. + * +@@ -122,7 +120,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + return 0; + } + +-@@ -892,15 +934,18 @@ static int at8031_pll_config(struct phy_device *phydev) ++@@ -892,15 +934,18 @@ static int at8031_pll_config(struct phy_ + + static int at803x_config_init(struct phy_device *phydev) + { +@@ -144,7 +142,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + phy_unlock_mdio_bus(phydev); + if (ret) + return ret; +-@@ -959,6 +1004,7 @@ static int at803x_ack_interrupt(struct phy_device *phydev) ++@@ -959,6 +1004,7 @@ static int at803x_ack_interrupt(struct p + + static int at803x_config_intr(struct phy_device *phydev) + { +@@ -152,7 +150,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + int err; + int value; + +-@@ -975,6 +1021,10 @@ static int at803x_config_intr(struct phy_device *phydev) ++@@ -975,6 +1021,10 @@ static int at803x_config_intr(struct phy + value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; + value |= AT803X_INTR_ENABLE_LINK_FAIL; + value |= AT803X_INTR_ENABLE_LINK_SUCCESS; +@@ -163,7 +161,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + + err = phy_write(phydev, AT803X_INTR_ENABLE, value); + } else { +-@@ -1107,8 +1157,12 @@ static int at803x_read_specific_status(struct phy_device *phydev) ++@@ -1107,8 +1157,12 @@ static int at803x_read_specific_status(s + + static int at803x_read_status(struct phy_device *phydev) + { +@@ -176,7 +174,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + /* Update the link, but return if there was an error */ + err = genphy_update_link(phydev); + if (err) +-@@ -1162,6 +1216,7 @@ static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) ++@@ -1162,6 +1216,7 @@ static int at803x_config_mdix(struct phy + + static int at803x_config_aneg(struct phy_device *phydev) + { +@@ -184,7 +182,7 @@ index 052b2eb9f101f..3f3d4c164df40 100644 + int ret; + + ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); +-@@ -1178,6 +1233,9 @@ static int at803x_config_aneg(struct phy_device *phydev) ++@@ -1178,6 +1233,9 @@ static int at803x_config_aneg(struct phy + return ret; + } + +diff --git a/target/linux/generic/backport-5.15/778-v5.18-02-net-phy-at803x-support-downstream-SFP-cage.patch b/target/linux/generic/backport-5.15/778-v5.18-02-net-phy-at803x-support-downstream-SFP-cage.patch +index 8393cb32e8..3205cd5b5c 100644 +--- a/target/linux/generic/backport-5.15/778-v5.18-02-net-phy-at803x-support-downstream-SFP-cage.patch ++++ b/target/linux/generic/backport-5.15/778-v5.18-02-net-phy-at803x-support-downstream-SFP-cage.patch +@@ -25,7 +25,7 @@ Signed-off-by: David S. Miller + #include + + #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 +-@@ -555,6 +557,55 @@ static int at8031_register_regulators(st ++@@ -664,6 +666,55 @@ static int at8031_register_regulators(st + return 0; + } + +@@ -81,7 +81,7 @@ Signed-off-by: David S. Miller + static int at803x_parse_dt(struct phy_device *phydev) + { + struct device_node *node = phydev->mdio.dev.of_node; +-@@ -662,6 +713,11 @@ static int at803x_parse_dt(struct phy_de ++@@ -771,6 +822,11 @@ static int at803x_parse_dt(struct phy_de + phydev_err(phydev, "failed to get VDDIO regulator\n"); + return PTR_ERR(priv->vddio); + } +diff --git a/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch b/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch +index 0ac5fda4a0..5829b05d2c 100644 +--- a/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch ++++ b/target/linux/generic/backport-5.15/778-v5.18-03-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch +@@ -46,11 +46,9 @@ Signed-off-by: Sasha Levin + drivers/net/phy/at803x.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +-diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c +-index 6a467e7817a6a..59fe356942b51 100644 + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -2072,6 +2072,8 @@ static struct phy_driver at803x_driver[] = { ++@@ -2059,6 +2059,8 @@ static struct phy_driver at803x_driver[] + /* ATHEROS AR9331 */ + PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), + .name = "Qualcomm Atheros AR9331 built-in PHY", +@@ -59,7 +57,7 @@ index 6a467e7817a6a..59fe356942b51 100644 + .suspend = at803x_suspend, + .resume = at803x_resume, + .flags = PHY_POLL_CABLE_TEST, +-@@ -2087,6 +2089,8 @@ static struct phy_driver at803x_driver[] = { ++@@ -2074,6 +2076,8 @@ static struct phy_driver at803x_driver[] + /* Qualcomm Atheros QCA9561 */ + PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), + .name = "Qualcomm Atheros QCA9561 built-in PHY", +@@ -68,7 +66,7 @@ index 6a467e7817a6a..59fe356942b51 100644 + .suspend = at803x_suspend, + .resume = at803x_resume, + .flags = PHY_POLL_CABLE_TEST, +-@@ -2151,6 +2155,8 @@ static struct phy_driver at803x_driver[] = { ++@@ -2138,6 +2142,8 @@ static struct phy_driver at803x_driver[] + PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), + .name = "Qualcomm QCA8081", + .flags = PHY_POLL_CABLE_TEST, +diff --git a/target/linux/generic/backport-5.15/778-v5.18-04-net-phy-at803x-fix-error-return-code-in-at803x_probe.patch b/target/linux/generic/backport-5.15/778-v5.18-04-net-phy-at803x-fix-error-return-code-in-at803x_probe.patch +index cdae5b4ca4..f3aaff34ae 100644 +--- a/target/linux/generic/backport-5.15/778-v5.18-04-net-phy-at803x-fix-error-return-code-in-at803x_probe.patch ++++ b/target/linux/generic/backport-5.15/778-v5.18-04-net-phy-at803x-fix-error-return-code-in-at803x_probe.patch +@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski + + --- a/drivers/net/phy/at803x.c + +++ b/drivers/net/phy/at803x.c +-@@ -749,8 +749,10 @@ static int at803x_probe(struct phy_devic ++@@ -858,8 +858,10 @@ static int at803x_probe(struct phy_devic + int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); + int mode_cfg; + +diff --git a/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch b/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch +index 248b8b9d6c..e5c605c40f 100644 +--- a/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch ++++ b/target/linux/mvebu/patches-5.15/706-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch +@@ -22,11 +22,9 @@ Signed-off-by: Robert Marko + drivers/net/dsa/mv88e6xxx/global2_scratch.c | 31 +++++++++++++++++++++ + 3 files changed, 37 insertions(+), 1 deletion(-) + +-diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c +-index 43d126628610..b3803101d612 100644 + --- a/drivers/net/dsa/mv88e6xxx/chip.c + +++ b/drivers/net/dsa/mv88e6xxx/chip.c +-@@ -3409,7 +3409,10 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, ++@@ -3424,7 +3424,10 @@ static int mv88e6xxx_mdio_register(struc + + if (external) { + mv88e6xxx_reg_lock(chip); +@@ -38,11 +36,9 @@ index 43d126628610..b3803101d612 100644 + mv88e6xxx_reg_unlock(chip); + + if (err) +-diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h +-index f3e27573a386..e0649f21f28e 100644 + --- a/drivers/net/dsa/mv88e6xxx/global2.h + +++ b/drivers/net/dsa/mv88e6xxx/global2.h +-@@ -370,6 +370,8 @@ extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; ++@@ -371,6 +371,8 @@ extern const struct mv88e6xxx_gpio_ops m + + int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, + bool external); +@@ -51,11 +47,9 @@ index f3e27573a386..e0649f21f28e 100644 + int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin); + int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats); + +-diff --git a/drivers/net/dsa/mv88e6xxx/global2_scratch.c b/drivers/net/dsa/mv88e6xxx/global2_scratch.c +-index eda710062933..dc3f4645fa52 100644 + --- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c + +++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c +-@@ -289,3 +289,34 @@ int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, ++@@ -289,3 +289,34 @@ int mv88e6xxx_g2_scratch_gpio_set_smi(st + + return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val); + } +@@ -90,6 +84,3 @@ index eda710062933..dc3f4645fa52 100644 + + + + return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val); + +} +--- +-2.34.1 +- +-- +2.42.1 + diff --git a/build_patches/openwrt/0299-mvpp2-enable-dsa-parser-entry.patch b/build_patches/openwrt/0299-mvpp2-enable-dsa-parser-entry.patch new file mode 100644 index 00000000..2eb7ce4c --- /dev/null +++ b/build_patches/openwrt/0299-mvpp2-enable-dsa-parser-entry.patch @@ -0,0 +1,41 @@ +From 4540ecce14d98e8c06a9bff6307bfaaf4074f99e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Fabian=20Bl=C3=A4se?= +Date: Sat, 18 Nov 2023 23:30:43 +0100 +Subject: [PATCH] mvpp2: enable dsa parser entry + +--- + .../999-mvpp2-enable-dsa-parser-entry.patch | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + create mode 100644 target/linux/mvebu/patches-5.15/999-mvpp2-enable-dsa-parser-entry.patch + +diff --git a/target/linux/mvebu/patches-5.15/999-mvpp2-enable-dsa-parser-entry.patch b/target/linux/mvebu/patches-5.15/999-mvpp2-enable-dsa-parser-entry.patch +new file mode 100644 +index 0000000000..fe5c2657d9 +--- /dev/null ++++ b/target/linux/mvebu/patches-5.15/999-mvpp2-enable-dsa-parser-entry.patch +@@ -0,0 +1,22 @@ ++--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ++@@ -4757,7 +4757,7 @@ static int mvpp2_open(struct net_device ++ netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); ++ return err; ++ } ++- err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); +++ err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_DSA); ++ if (err) { ++ netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); ++ return err; ++--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c +++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c ++@@ -1260,7 +1260,7 @@ static void mvpp2_prs_dsa_init(struct mv ++ ++ /* Shift 0 bytes */ ++ mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); ++- mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); +++ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); ++ ++ /* Clear all sram ai bits for next iteration */ ++ mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); +-- +2.42.1 + diff --git a/build_patches/openwrt/0299-mvpp2-vlan-after-dsa.patch b/build_patches/openwrt/0299-mvpp2-vlan-after-dsa.patch new file mode 100644 index 00000000..5281ceb1 --- /dev/null +++ b/build_patches/openwrt/0299-mvpp2-vlan-after-dsa.patch @@ -0,0 +1,30 @@ +From fddf68b6c559df4e7b8561ea57d6e27bc4b0a8db Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Fabian=20Bl=C3=A4se?= +Date: Mon, 20 Nov 2023 21:28:16 +0100 +Subject: [PATCH] mvpp2: vlan after dsa + +--- + .../linux/mvebu/patches-5.15/999-vlan-after-dsa.patch | 11 +++++++++++ + 1 file changed, 11 insertions(+) + create mode 100644 target/linux/mvebu/patches-5.15/999-vlan-after-dsa.patch + +diff --git a/target/linux/mvebu/patches-5.15/999-vlan-after-dsa.patch b/target/linux/mvebu/patches-5.15/999-vlan-after-dsa.patch +new file mode 100644 +index 0000000000..d6f241ca08 +--- /dev/null ++++ b/target/linux/mvebu/patches-5.15/999-vlan-after-dsa.patch +@@ -0,0 +1,11 @@ ++--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c +++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c ++@@ -576,7 +576,7 @@ static void mvpp2_prs_dsa_tag_set(struct ++ /* Set result info bits to 'no vlans' */ ++ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, ++ MVPP2_PRS_RI_VLAN_MASK); ++- mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); +++ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); ++ } ++ ++ /* Mask all ports */ +-- +2.42.1 + diff --git a/src/packages/fff/fff-network/aarch64/network.mikrotik,rb5009 b/src/packages/fff/fff-network/aarch64/network.mikrotik,rb5009 new file mode 100644 index 00000000..1c6df4e6 --- /dev/null +++ b/src/packages/fff/fff-network/aarch64/network.mikrotik,rb5009 @@ -0,0 +1,6 @@ +WANDEV=switch0 +SWITCHDEV=switch0 +CLIENT_PORTS="p2 p3 p4 p5 p6 p7 p8 sfp" +WAN_PORTS="p1" +DSA=1 +ROUTERMAC=$(cat /sys/class/net/p1/address) diff --git a/src/packages/fff/fff-network/files/etc/hotplug.d/net/40-net-rss b/src/packages/fff/fff-network/files/etc/hotplug.d/net/40-net-rss new file mode 100644 index 00000000..5feebaa5 --- /dev/null +++ b/src/packages/fff/fff-network/files/etc/hotplug.d/net/40-net-rss @@ -0,0 +1,6 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-3.0 + +if [ $(uci get board.model.name) = "mikrotik,rb5009" ]; then + ethtool -K eth0 receive-hashing on +fi diff --git a/src/packages/fff/fff-network/files/etc/uci-defaults/50-packet-steering b/src/packages/fff/fff-network/files/etc/uci-defaults/50-packet-steering index 1427573d..515a642b 100644 --- a/src/packages/fff/fff-network/files/etc/uci-defaults/50-packet-steering +++ b/src/packages/fff/fff-network/files/etc/uci-defaults/50-packet-steering @@ -1,6 +1,11 @@ #!/bin/sh # SPDX-License-Identifier: GPL-3.0-or-later +# Skip devices which are capable of RSS +if [ $(uci get board.model.name) = "mikrotik,rb5009" ]; then + exit 0 +fi + # Enable RPS uci batch <<-__EOF__ set network.globals=globals