forked from freifunk-franken/firmware
ar71xx: backport ath9k-fixes from AA r36664
This commit is contained in:
parent
fc5ff59dcd
commit
9c5eb6797b
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@ -0,0 +1,31 @@
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac
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},
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};
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-static void __init ar913x_wmac_setup(void)
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+static int ar913x_wmac_reset(void)
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{
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/* reset the WMAC */
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ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
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@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi
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ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
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mdelay(10);
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+ return 0;
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+}
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+
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+static void __init ar913x_wmac_setup(void)
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+{
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+ ar913x_wmac_reset();
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+
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ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
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ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
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ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
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ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
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+
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+ ath79_wmac_data.external_reset = ar913x_wmac_reset;
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}
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@ -0,0 +1,81 @@
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -15,6 +15,7 @@
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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+#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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@@ -22,6 +23,7 @@
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "dev-wmac.h"
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+static u8 ath79_wmac_mac[ETH_ALEN];
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static struct ath9k_platform_data ath79_wmac_data;
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static struct resource ath79_wmac_resources[] = {
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@@ -143,7 +145,7 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = true;
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}
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-void __init ath79_register_wmac(u8 *cal_data)
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+void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
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{
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if (soc_is_ar913x())
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ar913x_wmac_setup();
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@@ -160,5 +162,10 @@ void __init ath79_register_wmac(u8 *cal_
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memcpy(ath79_wmac_data.eeprom_data, cal_data,
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sizeof(ath79_wmac_data.eeprom_data));
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+ if (mac_addr) {
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+ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
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+ ath79_wmac_data.macaddr = ath79_wmac_mac;
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+ }
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+
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platform_device_register(&ath79_wmac_device);
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}
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--- a/arch/mips/ath79/dev-wmac.h
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+++ b/arch/mips/ath79/dev-wmac.h
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@@ -12,6 +12,6 @@
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#ifndef _ATH79_DEV_WMAC_H
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#define _ATH79_DEV_WMAC_H
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-void ath79_register_wmac(u8 *cal_data);
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+void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
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#endif /* _ATH79_DEV_WMAC_H */
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--- a/arch/mips/ath79/mach-ap81.c
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+++ b/arch/mips/ath79/mach-ap81.c
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@@ -98,7 +98,7 @@ static void __init ap81_setup(void)
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ap81_gpio_keys);
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ath79_register_spi(&ap81_spi_data, ap81_spi_info,
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ARRAY_SIZE(ap81_spi_info));
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- ath79_register_wmac(cal_data);
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+ ath79_register_wmac(cal_data, NULL);
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ath79_register_usb();
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}
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--- a/arch/mips/ath79/mach-db120.c
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+++ b/arch/mips/ath79/mach-db120.c
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@@ -134,7 +134,7 @@ static void __init db120_setup(void)
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ath79_register_spi(&db120_spi_data, db120_spi_info,
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ARRAY_SIZE(db120_spi_info));
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ath79_register_usb();
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- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
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+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
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db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
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}
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--- a/arch/mips/ath79/mach-ap121.c
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+++ b/arch/mips/ath79/mach-ap121.c
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@@ -91,7 +91,7 @@ static void __init ap121_setup(void)
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ath79_register_spi(&ap121_spi_data, ap121_spi_info,
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ARRAY_SIZE(ap121_spi_info));
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ath79_register_usb();
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- ath79_register_wmac(cal_data);
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+ ath79_register_wmac(cal_data, NULL);
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}
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MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
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@ -0,0 +1,47 @@
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--- a/arch/mips/ath79/common.h
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+++ b/arch/mips/ath79/common.h
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@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
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void ath79_gpio_function_enable(u32 mask);
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void ath79_gpio_function_disable(u32 mask);
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void ath79_gpio_function_setup(u32 set, u32 clear);
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+void ath79_gpio_output_select(unsigned gpio, u8 val);
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void ath79_gpio_init(void);
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#endif /* __ATH79_COMMON_H */
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -198,6 +198,34 @@ void ath79_gpio_function_setup(u32 set,
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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+void __init ath79_gpio_output_select(unsigned gpio, u8 val)
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+{
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long flags;
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+ unsigned int reg;
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+ u32 t, s;
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+
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+ BUG_ON(!soc_is_ar934x());
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+
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+ if (gpio >= AR934X_GPIO_COUNT)
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+ return;
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+
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+ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
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+ s = 8 * (gpio % 4);
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+
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+ spin_lock_irqsave(&ath79_gpio_lock, flags);
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+
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+ t = __raw_readl(base + reg);
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+ t &= ~(0xff << s);
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+ t |= val << s;
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+ __raw_writel(t, base + reg);
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+
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+ /* flush write */
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+ (void) __raw_readl(base + reg);
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+
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+}
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+
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void __init ath79_gpio_init(void)
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{
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int err;
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@ -0,0 +1,61 @@
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--- a/arch/mips/ath79/early_printk.c
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+++ b/arch/mips/ath79/early_printk.c
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@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned
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/* nothing to do */
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}
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+static void prom_enable_uart(u32 id)
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+{
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+ void __iomem *gpio_base;
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+ u32 uart_en;
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+ u32 t;
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+
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+ switch (id) {
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+ case REV_ID_MAJOR_AR71XX:
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+ uart_en = AR71XX_GPIO_FUNC_UART_EN;
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+ break;
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+
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+ case REV_ID_MAJOR_AR7240:
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+ case REV_ID_MAJOR_AR7241:
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+ case REV_ID_MAJOR_AR7242:
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+ uart_en = AR724X_GPIO_FUNC_UART_EN;
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+ break;
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+
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+ case REV_ID_MAJOR_AR913X:
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+ uart_en = AR913X_GPIO_FUNC_UART_EN;
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+ break;
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+
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+ case REV_ID_MAJOR_AR9330:
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+ case REV_ID_MAJOR_AR9331:
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+ uart_en = AR933X_GPIO_FUNC_UART_EN;
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+ break;
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+
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+ case REV_ID_MAJOR_AR9341:
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+ case REV_ID_MAJOR_AR9342:
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+ case REV_ID_MAJOR_AR9344:
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+ /* TODO */
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+ default:
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+ return;
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+ }
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+
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+ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
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+ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
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+ t |= uart_en;
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+ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
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+}
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+
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static void prom_putchar_init(void)
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{
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void __iomem *base;
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@@ -85,8 +125,10 @@ static void prom_putchar_init(void)
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default:
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_prom_putchar = prom_putchar_dummy;
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- break;
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+ return;
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}
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+
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+ prom_enable_uart(id);
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}
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void prom_putchar(unsigned char ch)
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@ -0,0 +1,153 @@
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--- a/arch/mips/ath79/mach-pb44.c
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+++ b/arch/mips/ath79/mach-pb44.c
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@@ -8,23 +8,48 @@
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* by the Free Software Foundation.
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*/
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+#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c-gpio.h>
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#include <linux/i2c/pcf857x.h>
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+#include <linux/i2c/pcf857x.h>
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+#include <linux/spi/flash.h>
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+#include <linux/spi/vsc7385.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+#include <asm/mach-ath79/ath79.h>
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+
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+#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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+#include "machtypes.h"
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#include "pci.h"
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#define PB44_GPIO_I2C_SCL 0
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#define PB44_GPIO_I2C_SDA 1
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+#define PB44_PCF8757_VSC7395_CS 0
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+#define PB44_PCF8757_STEREO_CS 1
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+#define PB44_PCF8757_SLIC_CS0 2
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+#define PB44_PCF8757_SLIC_TEST 3
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+#define PB44_PCF8757_SLIC_INT0 4
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+#define PB44_PCF8757_SLIC_INT1 5
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+#define PB44_PCF8757_SW_RESET 6
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+#define PB44_PCF8757_SW_JUMP 8
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+#define PB44_PCF8757_LED_JUMP1 9
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+#define PB44_PCF8757_LED_JUMP2 10
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+#define PB44_PCF8757_TP24 11
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+#define PB44_PCF8757_TP25 12
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+#define PB44_PCF8757_TP26 13
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+#define PB44_PCF8757_TP27 14
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+#define PB44_PCF8757_TP28 15
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+
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#define PB44_GPIO_EXP_BASE 16
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+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
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#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
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#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
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#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
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@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
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.cs_line = 0,
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};
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+static struct ath79_spi_controller_data pb44_spi1_data = {
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+ .cs_type = ATH79_SPI_CS_TYPE_GPIO,
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+ .cs_line = PB44_GPIO_VSC7395_CS,
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+};
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+
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+static void pb44_vsc7395_reset(void)
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+{
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+ ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
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+ udelay(10);
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+ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
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+ mdelay(50);
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+}
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+
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+static struct vsc7385_platform_data pb44_vsc7395_data = {
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+ .reset = pb44_vsc7395_reset,
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+ .ucode_name = "vsc7395_ucode_pb44.bin",
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+ .mac_cfg = {
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+ .tx_ipg = 6,
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+ .bit2 = 1,
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+ .clk_sel = 0,
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+ },
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+};
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+
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+static const char *pb44_part_probes[] = {
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+ "RedBoot",
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+ NULL,
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+};
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+
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+static struct flash_platform_data pb44_flash_data = {
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+ .part_probes = pb44_part_probes,
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+};
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+
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static struct spi_board_info pb44_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p64",
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+ .platform_data = &pb44_flash_data,
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.controller_data = &pb44_spi0_data,
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},
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+ {
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+ .bus_num = 0,
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+ .chip_select = 1,
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+ .max_speed_hz = 25000000,
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+ .modalias = "spi-vsc7385",
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+ .platform_data = &pb44_vsc7395_data,
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+ .controller_data = &pb44_spi1_data,
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+ }
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};
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static struct ath79_spi_platform_data pb44_spi_data = {
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.bus_num = 0,
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- .num_chipselect = 1,
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+ .num_chipselect = 2,
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};
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+#define PB44_WAN_PHYMASK BIT(0)
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+#define PB44_LAN_PHYMASK 0
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+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
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+
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static void __init pb44_init(void)
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{
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i2c_register_board_info(0, pb44_i2c_board_info,
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@@ -122,6 +192,22 @@ static void __init pb44_init(void)
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ARRAY_SIZE(pb44_spi_info));
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ath79_register_usb();
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ath79_register_pci();
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+
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+ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
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+
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+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
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+
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+ ath79_register_eth(0);
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+
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+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
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+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth1_data.speed = SPEED_1000;
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+ ath79_eth1_data.duplex = DUPLEX_FULL;
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+ ath79_eth1_pll_data.pll_1000 = 0x110000;
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+
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+ ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -58,6 +58,7 @@ config ATH79_MACH_DB120
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config ATH79_MACH_PB44
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bool "Atheros PB44 reference board"
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select SOC_AR71XX
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+ select ATH79_DEV_ETH
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_SPI
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@ -0,0 +1,166 @@
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -148,6 +148,137 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = true;
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}
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+static bool __init
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+ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
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+{
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+ int timeout = 1000;
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+ u32 val;
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+
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+ __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
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+ while (timeout--) {
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+ val = __raw_readl(base + AR9300_OTP_STATUS);
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+ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ if (!timeout)
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+ return false;
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+
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+ *data = __raw_readl(base + AR9300_OTP_READ_DATA);
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+ return true;
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+}
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+
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+static bool __init
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+ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
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+{
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+ u32 data;
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+ int i;
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+
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+ for (i = 0; i < len; i++) {
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+ int offset = 8 * ((addr - i) % 4);
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+
|
||||
+ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
|
||||
+ return false;
|
||||
+
|
||||
+ dest[i] = (data >> offset) & 0xff;
|
||||
+ }
|
||||
+
|
||||
+ return true;
|
||||
+}
|
||||
+
|
||||
+static bool __init
|
||||
+ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
|
||||
+ int dest_start, int dest_len)
|
||||
+{
|
||||
+ int dest_bytes = 0;
|
||||
+ int offset = 0;
|
||||
+ int end = addr - len;
|
||||
+ u8 hdr[2];
|
||||
+
|
||||
+ while (addr > end) {
|
||||
+ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
|
||||
+ return false;
|
||||
+
|
||||
+ addr -= 2;
|
||||
+ offset += hdr[0];
|
||||
+
|
||||
+ if (offset <= dest_start + dest_len &&
|
||||
+ offset + len >= dest_start) {
|
||||
+ int data_offset = 0;
|
||||
+ int dest_offset = 0;
|
||||
+ int copy_len;
|
||||
+
|
||||
+ if (offset < dest_start)
|
||||
+ data_offset = dest_start - offset;
|
||||
+ else
|
||||
+ dest_offset = offset - dest_start;
|
||||
+
|
||||
+ copy_len = len - data_offset;
|
||||
+ if (copy_len > dest_len - dest_offset)
|
||||
+ copy_len = dest_len - dest_offset;
|
||||
+
|
||||
+ ar93xx_wmac_otp_read(base, addr - data_offset,
|
||||
+ dest + dest_offset,
|
||||
+ copy_len);
|
||||
+
|
||||
+ dest_bytes += copy_len;
|
||||
+ }
|
||||
+ addr -= hdr[1];
|
||||
+ }
|
||||
+ return !!dest_bytes;
|
||||
+}
|
||||
+
|
||||
+bool __init ar93xx_wmac_read_mac_address(u8 *dest)
|
||||
+{
|
||||
+ void __iomem *base;
|
||||
+ bool ret = false;
|
||||
+ int addr = 0x1ff;
|
||||
+ unsigned int len;
|
||||
+ u32 hdr_u32;
|
||||
+ u8 *hdr = (u8 *) &hdr_u32;
|
||||
+ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
|
||||
+ int mac_start = 2, mac_end = 8;
|
||||
+
|
||||
+ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
|
||||
+ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
|
||||
+ while (addr > sizeof(hdr)) {
|
||||
+ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
|
||||
+ break;
|
||||
+
|
||||
+ if (hdr_u32 == 0 || hdr_u32 == ~0)
|
||||
+ break;
|
||||
+
|
||||
+ len = (hdr[1] << 4) | (hdr[2] >> 4);
|
||||
+ addr -= 4;
|
||||
+
|
||||
+ switch (hdr[0] >> 5) {
|
||||
+ case 0:
|
||||
+ if (len < mac_end)
|
||||
+ break;
|
||||
+
|
||||
+ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
|
||||
+ ret = true;
|
||||
+ break;
|
||||
+ case 3:
|
||||
+ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
|
||||
+ mac_start, 6);
|
||||
+ break;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ addr -= len + 2;
|
||||
+ }
|
||||
+
|
||||
+ iounmap(base);
|
||||
+ if (ret)
|
||||
+ memcpy(dest, mac, 6);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
|
||||
{
|
||||
if (soc_is_ar913x())
|
||||
--- a/arch/mips/ath79/dev-wmac.h
|
||||
+++ b/arch/mips/ath79/dev-wmac.h
|
||||
@@ -13,5 +13,6 @@
|
||||
#define _ATH79_DEV_WMAC_H
|
||||
|
||||
void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
|
||||
+bool ar93xx_wmac_read_mac_address(u8 *dest);
|
||||
|
||||
#endif /* _ATH79_DEV_WMAC_H */
|
||||
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
@@ -129,6 +129,14 @@
|
||||
#define QCA955X_NFC_BASE 0x1b000200
|
||||
#define QCA955X_NFC_SIZE 0xb8
|
||||
|
||||
+#define AR9300_OTP_BASE 0x14000
|
||||
+#define AR9300_OTP_STATUS 0x15f18
|
||||
+#define AR9300_OTP_STATUS_TYPE 0x7
|
||||
+#define AR9300_OTP_STATUS_VALID 0x4
|
||||
+#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
|
||||
+#define AR9300_OTP_STATUS_SM_BUSY 0x1
|
||||
+#define AR9300_OTP_READ_DATA 0x15f1c
|
||||
+
|
||||
/*
|
||||
* DDR_CTRL block
|
||||
*/
|
|
@ -0,0 +1,31 @@
|
|||
--- a/arch/mips/ath79/dev-wmac.c
|
||||
+++ b/arch/mips/ath79/dev-wmac.c
|
||||
@@ -279,6 +279,16 @@ bool __init ar93xx_wmac_read_mac_address
|
||||
return ret;
|
||||
}
|
||||
|
||||
+void __init ath79_wmac_disable_2ghz(void)
|
||||
+{
|
||||
+ ath79_wmac_data.disable_2ghz = true;
|
||||
+}
|
||||
+
|
||||
+void __init ath79_wmac_disable_5ghz(void)
|
||||
+{
|
||||
+ ath79_wmac_data.disable_5ghz = true;
|
||||
+}
|
||||
+
|
||||
void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
|
||||
{
|
||||
if (soc_is_ar913x())
|
||||
--- a/arch/mips/ath79/dev-wmac.h
|
||||
+++ b/arch/mips/ath79/dev-wmac.h
|
||||
@@ -13,6 +13,9 @@
|
||||
#define _ATH79_DEV_WMAC_H
|
||||
|
||||
void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
|
||||
+void ath79_wmac_disable_2ghz(void);
|
||||
+void ath79_wmac_disable_5ghz(void);
|
||||
+
|
||||
bool ar93xx_wmac_read_mac_address(u8 *dest);
|
||||
|
||||
#endif /* _ATH79_DEV_WMAC_H */
|
|
@ -0,0 +1,31 @@
|
|||
--- a/arch/mips/ath79/dev-wmac.c
|
||||
+++ b/arch/mips/ath79/dev-wmac.c
|
||||
@@ -76,10 +76,27 @@ static void __init ar913x_wmac_setup(voi
|
||||
|
||||
static int ar933x_wmac_reset(void)
|
||||
{
|
||||
+ int retries = 20;
|
||||
+
|
||||
ath79_device_reset_set(AR933X_RESET_WMAC);
|
||||
ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||
|
||||
- return 0;
|
||||
+ while (1) {
|
||||
+ u32 bootstrap;
|
||||
+
|
||||
+ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
|
||||
+ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (retries-- == 0)
|
||||
+ break;
|
||||
+
|
||||
+ udelay(10000);
|
||||
+ retries++;
|
||||
+ }
|
||||
+
|
||||
+ pr_err("ar933x: WMAC reset timed out");
|
||||
+ return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int ar933x_r1_get_wmac_revision(void)
|
|
@ -0,0 +1,28 @@
|
|||
--- a/drivers/net/wireless/ath/ath9k/hw.c
|
||||
+++ b/drivers/net/wireless/ath/ath9k/hw.c
|
||||
@@ -1374,7 +1374,10 @@ static bool ath9k_hw_set_reset(struct at
|
||||
|
||||
REGWRITE_BUFFER_FLUSH(ah);
|
||||
|
||||
- udelay(50);
|
||||
+ if (AR_SREV_9100(ah))
|
||||
+ mdelay(10);
|
||||
+ else
|
||||
+ udelay(50);
|
||||
|
||||
REG_WRITE(ah, AR_RTC_RC, 0);
|
||||
if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
|
||||
@@ -1385,8 +1388,12 @@ static bool ath9k_hw_set_reset(struct at
|
||||
if (!AR_SREV_9100(ah))
|
||||
REG_WRITE(ah, AR_RC, 0);
|
||||
|
||||
- if (AR_SREV_9100(ah))
|
||||
+ if (AR_SREV_9100(ah) && type != ATH9K_RESET_WARM) {
|
||||
+ if (ah->external_reset)
|
||||
+ ah->external_reset();
|
||||
+
|
||||
udelay(50);
|
||||
+ }
|
||||
|
||||
return true;
|
||||
}
|
|
@ -25,8 +25,11 @@ prepare() {
|
|||
# This adds the sysctl load just before the network comes up
|
||||
cat build_patches/invoke_sysctl_before_network.patch | patch -p0 -d $target
|
||||
|
||||
#backport ath9k-fixes from openwrt r35786
|
||||
#backport mac80211-patches from openwrt r35786 and r36664
|
||||
cp build_patches/mac80211/* $target/package/mac80211/patches
|
||||
|
||||
#backport kernelpatches from openwrt r36664
|
||||
cp build/linux/ar71xx/patches-3.3/* $target/target/ar71xx/linux/patches
|
||||
|
||||
#batman-adv: distributed arp table fixes
|
||||
cat build_patches/changeset_35324.diff | patch -p1 -d $target/feeds
|
||||
|
|
Loading…
Reference in New Issue